Mercurial > ecos
changeset 2539:11949247abb3
* cdl/hal_arm_at91sam7s.cdl: CDL for the MOR OSCCOUNT and
PLLR PLLCOUNT.
* include/hal_platform_setup.h: Turned the MOR OSCCOUNT
and the PLLR PLLCOUNT setup into CLD configurable
variables to allow a more flexible clock setup.
* include/hal_platform_setup.h: Added setup code for devices
that has a second flash controller i.e. the 512 devices
| author | asl |
|---|---|
| date | Tue, 02 Sep 2008 05:37:50 +0000 |
| parents | 8f5c64d663f7 |
| children | d3fd907caafd |
| files | packages/hal/arm/at91/at91sam7s/current/ChangeLog packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h |
| diffstat | 3 files changed, 46 insertions(+), 5 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/hal/arm/at91/at91sam7s/current/ChangeLog +++ b/packages/hal/arm/at91/at91sam7s/current/ChangeLog @@ -1,3 +1,13 @@ +2008-09-01 John Eigelaar <jeigelaar@mweb.co.za> + + * cdl/hal_arm_at91sam7s.cdl: CDL for the MOR OSCCOUNT and + PLLR PLLCOUNT. + * include/hal_platform_setup.h: Turned the MOR OSCCOUNT + and the PLLR PLLCOUNT setup into CLD configurable + variables to allow a more flexible clock setup. + * include/hal_platform_setup.h: Added setup code for devices + that has a second flash controller i.e. the 512 devices. + 2008-08-14 Jürgen Lambrecht <J.Lambrecht@televic.com> * include/plf_io.h: removed AT91_SPI_MR_MODFDIS, AT91_WSTC
--- a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl +++ b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl @@ -236,6 +236,16 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 { Whether a crystal or a XIN input clock is clocking the device." } + cdl_option CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT { + display "Startup time for the main oscillator" + flavor data + legal_values { 0 to 255 } + default_value 6 + description " + Specifies the number of Slow Clock cycles multiplied by 8 + for the Main Oscillator start-up time." + } + cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER { display "Divider for PLL clock" flavor data @@ -256,6 +266,16 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 { the PLL clock." } + cdl_option CYGNUM_HAL_ARM_AT91_PLL_COUNT { + display "Startup Counter for PLL clock" + flavor data + legal_values { 0 to 64 } + default_value 16 + description " + Specifies the number of slow clock cycles before the LOCK bit + is set in PMC_SR after PLL Register is written." + } + cdl_option CYGNUM_HAL_ARM_AT91_SLOW_CLOCK { display "Slow clock frequency" flavor data
--- a/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h +++ b/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h @@ -55,7 +55,7 @@ #include <cyg/hal/var_io.h> #include <cyg/hal/plf_io.h> - + // Macro to initialise the Memory Controller .macro _flash_init __flash_init__: @@ -73,20 +73,31 @@ # endif #endif str r1,[r0,#AT91_MC_FMR] +#if defined(AT91_MC_FMR1) + // If we have a second flash controller we need to set that up as well + str r1,[r0,#AT91_MC_FMR1] +#endif .endm // Macro to start the main clock. .macro _main_clock_init __main_clock_init__: ldr r0,=AT91_PMC + + // Check that we have a stable clock before we start switching +wait_pmc_sr_0: + ldr r1,[r0,#AT91_PMC_SR] + ands r1,r1,#AT91_PMC_SR_MCKRDY + beq wait_pmc_sr_0 + // Swap to the slow clock, just to be sure. ldr r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK) str r1,[r0,#AT91_PMC_MCKR] - // startup time + #if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK) ldr r1,=(AT91_PMC_MOR_OSCBYPASS) #else - ldr r1,=(AT91_PMC_MOR_OSCCOUNT(6)|AT91_PMC_MOR_MOSCEN) + ldr r1,=(AT91_PMC_MOR_OSCCOUNT(CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT)|AT91_PMC_MOR_MOSCEN) #endif str r1,[r0,#AT91_PMC_MOR] @@ -97,8 +108,8 @@ wait_pmc_sr_1: beq wait_pmc_sr_1 // Set the PLL multiplier and divider. 16 slow clocks go by - // before the LOCK bit is set. */ - ldr r1,=((AT91_PMC_PLLR_DIV(CYGNUM_HAL_ARM_AT91_PLL_DIVIDER))|(AT91_PMC_PLLR_PLLCOUNT(16))|(AT91_PMC_PLLR_MUL(CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER-1))) + // before the LOCK bit is set. */ + ldr r1,=((AT91_PMC_PLLR_DIV(CYGNUM_HAL_ARM_AT91_PLL_DIVIDER))|(AT91_PMC_PLLR_PLLCOUNT(CYGNUM_HAL_ARM_AT91_PLL_COUNT))|(AT91_PMC_PLLR_MUL(CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER-1))) str r1,[r0,#AT91_PMC_PLLR] // Wait for PLL locked indication
