Mercurial > ecos
changeset 3218:1f92f3f7cf61
Add clock gating management and API.
| author | vae |
|---|---|
| date | Sun, 07 Apr 2013 15:59:31 +0000 |
| parents | 10a2004b0d31 |
| children | 2294cb4fd519 |
| files | packages/hal/cortexm/kinetis/var/current/ChangeLog packages/hal/cortexm/kinetis/var/current/include/var_io.h packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h packages/hal/cortexm/kinetis/var/current/src/hal_diag.c packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c |
| diffstat | 7 files changed, 405 insertions(+), 220 deletions(-) [+] |
line wrap: on
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--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -1,3 +1,9 @@ +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * include/var_io.h, include/var_io_clkgat.h, include/var_io_devs.h, + * src/hal_diag.c, src/kinetis_ddram.c, src/kinetis_misc.c + Add clock gating management and API. [ Bugzilla 1001814 ] + 2012-11-06 Ilija Kocho <ilijak@siva.com.mk> * cdl/hal_cortexm_kinetis.cdl: Changes to Kinetis part builder related to
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011 Free Software Foundation, Inc. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -707,191 +707,27 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S 12 #define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val) \ VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val) -// SCGC1 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M 0x20 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S 5 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M 0x400 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S 10 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M 0x800 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S 11 -#define CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M | CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M) - -// SCGC2 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M 0x1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S 0 -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M 0x1000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S 12 -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M 0x2000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S 13 - -#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M) - -// SCGC3 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M 0x1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S 0 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M 0x10 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S 4 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M 0x1000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S 12 -#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC -# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0x4000 -# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 14 -#else -# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0 -# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 0 -#endif -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M 0x20000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S 17 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M 0x1000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S 24 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M 0x8000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S 27 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M 0x10000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S 28 - -#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M ) - -// SCGC4 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M 0x2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S 1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M 0x4 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S 2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M 0x40 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S 6 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M 0x80 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S 7 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M 0x400 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S 10 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M 0x800 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S 11 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M 0x1000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S 12 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M 0x2000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S 13 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M 0x40000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S 18 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M 0x80000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S 19 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M 0x100000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S 20 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M 0x10000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S 28 - -#define CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M |\ - CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M |\ - CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M) +//--------------------------------------------------------------------------- +// Clock distribution +// The following encodes the control register and clock bit number +// into clock configuration descriptor (CLKCD). +#define CYGHWR_HAL_KINETIS_SIM_SCGC(__reg,__bit) ((((__reg) - 1 ) & 0xF) + \ + (((__bit) << 8) & 0x1F00)) -// SCGC5 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M 0x1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S 0 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M 0x2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S 1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M 0x20 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S 5 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M 0x200 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S 9 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M 0x400 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S 10 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M 0x800 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S 11 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M 0x1000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S 12 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M 0x2000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S 13 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M 0x4000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S 14 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M -#define CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M) -#endif +// Macros to extract encoded values. +#define CYGHWR_HAL_KINETIS_SIM_SCGC_REG(__clkcd) (((__clkcd) & 0xF)) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(__clkcd) (((__clkcd) >> 8) & 0x1F) -// SCGC6 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M 0x1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S 0 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M 0x2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S 1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M 0x2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S 1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M 0x4 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S 2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M 0x10 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S 4 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_M 0x1000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_S 12 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M 0x2000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S 13 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M 0x8000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S 15 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M 0x40000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S 18 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M 0x200000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S 21 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M 0x400000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S 22 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M 0x800000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S 23 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M 0x1000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S 24 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M 0x2000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S 25 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M 0x8000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S 27 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M 0x20000000 -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S 29 +// Functions and macros to enable/disable clocks. +#define CYGHWR_HAL_SCGC_NONE (0xFFFFFFFF) +__externC void hal_clock_enable(cyg_uint32 clkcd); +__externC void hal_clock_disable(cyg_uint32 clkcd); -#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M) +#define CYGHWR_HAL_CLOCK_ENABLE(__clkcd) hal_clock_enable(__clkcd) +#define CYGHWR_HAL_CLOCK_DISABLE(__clkcd) hal_clock_disable(__clkcd) -// SCGC7 Bit Fields -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M 0x1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S 0 -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M 0x2 -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S 1 -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M 0x4 -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S 2 - -#define CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M \ - (CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M) +#include <cyg/hal/var_io_clkgat.h> // CLKDIV1 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M 0xF0000 @@ -986,21 +822,6 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_S 0 -// The following encodes the control register and clock bit number -// into 16 bit descriptor. -#define CYGHWR_HAL_CLOCK( __reg, __bit ) ((((__reg)-1)&0xF) + (((__bit)<<8)&0x1F00)) - -// Macros to extract encoded values. -#define CYGHWR_HAL_CLOCK_REG( __desc ) ((__desc)&0xF) -#define CYGHWR_HAL_CLOCK_BIT( __desc ) (((__desc)>>8)&0x1F) - -// Functions and macros to enable/disable clocks. -#define CYGHWR_HAL_KINETIS_CLOCK_NONE (0xFFFF) -__externC void hal_clock_enable( cyg_uint32 desc ); -__externC void hal_clock_disable( cyg_uint32 desc ); - -#define CYGHWR_HAL_CLOCK_ENABLE( __desc ) hal_clock_enable( __desc ) -#define CYGHWR_HAL_CLOCK_DISABLE( __desc ) hal_clock_disable( __desc ) //-------------------------------------------------------------------------- // AXBS - Crossbar switch @@ -1308,7 +1129,7 @@ enum{ #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE (0x04) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE (0x02) #define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01) - + //--------------------------------------------------------------------------- // MPU Memory Protection unit
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h @@ -0,0 +1,332 @@ +#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H +#define CYGONCE_HAL_VAR_IOCLKGAT_H +//=========================================================================== +// +// var_io_clkgat.h +// +// Kinetis clock gating +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2013-03-17 +// Purpose: Kinetis clock distribution macros +// Description: +// Usage: This file is included by <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//--------------------------------------------------------------------------- +// Clock distribution + +// SCGC1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S 5 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S 11 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_OSC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S) + +// SCGC2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S 13 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ENET \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S) + +// SCGC3 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_M 0x100 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0x4000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 14 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M 0x20000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S 17 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S 22 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S 28 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_NFC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DDR \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SDHC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LCDC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC3 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S) + +// SCGC4 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M 0x40 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S 6 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M 0x80 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S 7 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M 0x80000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S 19 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M 0x100000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S 28 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_EWM \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMT \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART2 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART3 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBOTG \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMP \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_VREF \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LLWU \ + CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S) + +// SCGC5 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_M 0x8 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S 3 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S 5 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M 0x200 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S 9 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M 0x4000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S 14 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_LPTIMER \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_REGFILE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICESR \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_TSI \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTD \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTE \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTF \ + CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S) + +// SCGC6 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_M 0x100000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M 0x200000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S 21 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M 0x400000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S 22 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S 23 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M 0x20000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S 29 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTFL \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2S \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_CRC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBHS \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBDCD \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PDB \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_PIT \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM1 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0 \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC \ + CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S) + +// SCGC7 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S 2 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMA \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S) +#define CYGHWR_HAL_KINETIS_SIM_SCGC_MPU \ + CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S) + +//----------------------------------------------------------------------------- +// end of var_io_clkgat.h + +#endif // CYGONCE_HAL_VAR_IOCLKGAT_H
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011 Free Software Foundation, Inc. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -73,6 +73,15 @@ #define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE 0x400EA000 #define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE 0x400EB000 +// UART Clock gating + +#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART0 +#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART1 +#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART2 +#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART3 +#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 +#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 + // UART PIN configuration // Note: May be overriden by plf_io.h @@ -140,6 +149,8 @@ // ENET // Lend some HAL dependent functions to the Ethernet device driver #define CYGADDR_IO_ETH_FREESCALE_ENET0_BASE (0x400C0000) +// Clock gating +#define CYGHWR_IO_FREESCALE_ENET0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_ENET #ifndef __ASSEMBLER__ @@ -159,12 +170,11 @@ #define CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK hal_get_peripheral_clock(); -#ifndef __ASSEMBLER__ +#define CYGHWR_IO_FREESCALE_DSPI0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0 +#define CYGHWR_IO_FREESCALE_DSPI1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1 +#define CYGHWR_IO_FREESCALE_DSPI2_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2 -# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) \ - hal_set_pin_function(__pin) - -#endif +# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) hal_set_pin_function(__pin) #ifndef KINETIS_PIN_SPI0_OUT_OPT #define KINETIS_PIN_SPI0_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \ @@ -359,6 +369,13 @@ #define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P #define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P +//Clock distribution +#define CYGHWR_IO_CLOCK_ENABLE(__scgc) hal_clock_enable(__scgc) + +#define CYGHWR_IO_FREESCALE_EDMA0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMA +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1 //----------------------------------------------------------------------------- // end of var_io_devs.h #endif // CYGONCE_HAL_VAR_IO_DEVS_H
--- a/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c +++ b/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011 Free Software Foundation, Inc. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -75,6 +75,7 @@ typedef struct { cyg_int32 isr_vector; cyg_uint32 rx_pin; cyg_uint32 tx_pin; + cyg_uint32 clock_gate; cyg_int32 baud_rate; cyg_int32 irq_state; } channel_data_t; @@ -84,37 +85,37 @@ channel_data_t plf_ser_channels[] = { { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX_TX, CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, #endif #ifdef CYGINT_HAL_FREESCALE_UART1 { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX_TX, CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, #endif #ifdef CYGINT_HAL_FREESCALE_UART2 { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART2_RX_TX, CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, #endif #ifdef CYGINT_HAL_FREESCALE_UART3 { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART3_RX_TX, CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, #endif #ifdef CYGINT_HAL_FREESCALE_UART4 { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART4_RX_TX, CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, #endif #ifdef CYGINT_HAL_FREESCALE_UART5 { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART5_RX_TX, CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX, - CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } + CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } #endif }; @@ -138,6 +139,8 @@ cyg_hal_plf_serial_init_channel(void* __ channel_data_t* chan = (channel_data_t*)__ch_data; CYG_ADDRESS uart_p = chan->base; + // Bring clock to the device + CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate); // Configure PORT pins hal_set_pin_function(chan->rx_pin); hal_set_pin_function(chan->tx_pin);
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2012 Free Software Foundation, Inc. +// Copyright (C) 2012, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -89,8 +89,8 @@ hal_cortexm_kinetis_ddrmc_init(const cyg cyg_uint32 cr_ix; cyg_uint32 cr_i; cyg_uint32 regval; - - sim_p->scgc3 |= CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M; + + CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_DDR); regval = sim_p->mcr & ~CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M; sim_p->mcr = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP;
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2010 Free Software Foundation, Inc. +// Copyright (C) 2010, 2013 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -277,14 +277,19 @@ hal_dump_pin_setting(cyg_uint32 pin) } } +//========================================================================== +// Clock distribution +// + void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR hal_clock_enable(cyg_uint32 desc) { volatile cyg_uint32 *scgc_p; - if(desc != CYGHWR_HAL_KINETIS_CLOCK_NONE) { - scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + CYGHWR_HAL_CLOCK_REG(desc); - *scgc_p |= 1 << CYGHWR_HAL_CLOCK_BIT(desc); + if(desc != CYGHWR_HAL_SCGC_NONE) { + scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + + CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc); + *scgc_p |= 1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc); } } @@ -293,9 +298,10 @@ hal_clock_disable(cyg_uint32 desc) { volatile cyg_uint32 *scgc_p; - if(desc != CYGHWR_HAL_KINETIS_CLOCK_NONE) { - scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + CYGHWR_HAL_CLOCK_REG(desc); - *scgc_p &= ~(1 << CYGHWR_HAL_CLOCK_BIT(desc)); + if(desc != CYGHWR_HAL_SCGC_NONE) { + scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 + + CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc); + *scgc_p &= ~(1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc)); } }