Mercurial > ecos
changeset 3056:2090db533f3f
* New package -- Freescale Kinetis variant HAL.
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new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -0,0 +1,57 @@ +2011-10-19 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + * cdl/kinetis_clocking.cdl: + * src/hal_diag.c: + * src/kinetis_misc.c: + * src/kinetis_clocking.c: + * include/hal_cache.h: + * include/hal_diag.h: + * include/plf_stub.h: + * include/variant.inc: + * include/var_arch.h: + * include/var_intr.h: + * include/var_io.h: + * include/var_io_devs.h: + * include/var_io_flexbus.h: + * include/pkgconf/mlt_kinetis_flash_sram2s_rom.h + * include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi + * include/pkgconf/mlt_kinetis_flash_sram2s_sram.h + * include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_sram.h + * include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h + * include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi + * include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h + * include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi + * include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h + * include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi + New package -- Freescale Kinetis variant HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl @@ -0,0 +1,628 @@ +##========================================================================== +## +## hal_cortexm_kinetis.cdl +## +## Cortex-M Freescale Kinetis variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2010-12-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS { + display "Freescale Kinetis Cortex-M4 Variant" + parent CYGPKG_HAL_CORTEXM + hardware + include_dir cyg/hal + define_header hal_cortexm_kinetis.h + description " + This package provides generic support for the Freescale Cortex-M4 + based Kinetis microcontroller family. + It is also necessary to select a variant and platform HAL package." + + compile hal_diag.c kinetis_misc.c kinetis_clocking.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + requires { CYGHWR_HAL_CORTEXM == "M4" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_kinetis.h>" + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS { + display "Kinetis part" + flavor data + calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM . + (CYGHWR_HAL_CORTEXM_KINETIS_FPU ? "F" : "D") . + (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM ? "X" : "N") . + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME } + description " + Kinetis family has several sub-families, with various peripheral + sets and CPU options. Each sub-family consists of several + members differing by sizes of on-chip FLASH and SRAM. This + control, enables the user to build Kinetis member part and so + tailor HAL for a specific microcontroller by selection of + microcontroller's properties such as microcontroller sub-family, + memory options, etc." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM { + display "Sub-family" + flavor data + default_value { 60 } + legal_values { 10 20 30 40 50 60 70 } + description " + Kinetis family consists of several sub-families differing by + features and CPU power." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU { + display "Floating Point Unit option" + implements CYGINT_HAL_CORTEXM_FPU + flavor bool + default_value { 0 } + description "Select whether the chip has Floating Point Unit." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME { + display "Flash name segment" + flavor data + default_value { 512 } + legal_values { 32 64 96 128 256 512 "1M0" } + description " + Flash size is represented in part name encoded as KiB + (e.g. 512) or MiB (e.g. 1M0)." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM { + display "FlexNVM option" + flavor bool + default_value { 0 } + description "Select whether the chip has FlexNVM." + } + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU exception priority level bits" + flavor data + default_value 4 + description " + This option defines the number of bits used to encode the + exception priority levels that this variant of the Cortex-M + CPU implements." + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING { + display "Clocking" + flavor data + no_define + calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG + description "Configure system clock and subsystem clocking." + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP { + display "System frequency clock setpoint" + flavor data + legal_values 32768 to 220000000 + default_value 96000000 + description "Desired system clock frequency" + } + script kinetis_clocking.cdl + } + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + default_value 0xE0 + description "Set clock ISR priority. Default setting is lowest priority." + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + description " + The period defined here is something of a fake, it is + expressed in terms of a notional 1MHz clock. The value + actually installed in the hardware is calculated from + the current settings of the clock generation hardware." + } + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + calculated { + (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ? + CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR + } + no_define + define -file system.h CYG_HAL_STARTUP + description " + Startup type defines what type of application shall be built. + Startup type can be defined by variant (CYG_HAL_STARTUP_VAR) + or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + + cdl_option CYG_HAL_STARTUP_VAR { + display "By variant" + flavor data + default_value { + (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ? + "ByPlatform" : "ROM" } + legal_values { "ROM" "SRAM" } + active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant")) + description " + 'ROM' startup builds a stand-alone application which will + be placed into flash. SRAM startup builds application + intended for loading in on-chip SRAM by means of JTAG/SWD. + Note: Variant Startup Type can be overriden/overloaded by + Platform Startup Type." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF { + display "FlexNVM configuration" + flavor none + no_define + active_if CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM + requires { + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <= + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE { + display "Enhanced EEPROM (EEE)" + flavor bool; + + cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE { + display "EEE Size \[Bytes\]" + flavor data + legal_values { 32 64 128 256 512 1024 2048 4096 } + default_value 4096 + } + + cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT { + display "EEE Split ratio" + flavor data + legal_values { 0 2 4 8 } + default_value 0 + description " + Enhanced EEPROM is split in two partitions that are + represented by separate sections in MLT files. + The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents + partition size ratio where EEE0 partition size is + 1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1 + is the rest. As a special arrangement + (CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where + split equals 2 but in MLT files whole EEE is counted + as a single section." + + cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE { + display "e_eeprom0 section size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ? + CYGHWR_HAL_KINETIS_EEE_SIZE / + CYGHWR_HAL_KINETIS_EEE_SPLIT : + CYGHWR_HAL_KINETIS_EEE_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE { + display "e_eeprom1 section size \[Bytes\]" + flavor data + active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 } + calculated { CYGHWR_HAL_KINETIS_EEE_SIZE - + CYGHWR_HAL_KINETIS_EEE0_SIZE } + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB { + display "FlexNVM partition used for EEE \[KiB\]" + flavor data + default_value 32 + legal_values { 32 64 128 192 224 256 } + } + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE { + display "FlexNVM D Flash" + flavor data + active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB < + CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB} + calculated { + 1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB - + CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB) + } + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM { + display "Flexram ordinary RAM" + flavor data + active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE } + calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE + } + + cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE { + display "Flexram size" + flavor data + default_value 4096 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB { + display "FlexNVM size \[KiB\]" + flavor data + calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { + (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF : + (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_rom" : + (CYG_HAL_STARTUP == "SRAM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_sram" : + "undefined" } + description " + Combination of 'Startup type' and 'Kinetis part' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED { + display "Unified on chip SRAM region" + flavor bool + default_value { 1 } + description " + Kinetis have two equal SRAM banks SRAM_L and SRAM_U that + occupy consecutive memory blocks with \(possibility for + simultaneous\) access from on separate buses. + SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000. + This option provides for selection between memory layout with + single (unified) (S)RAM region and layout with two separate + (S)RAM regions." + } + + cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION { + display "Utilize \".kinetis_misc\" section for HAL" + flavor bool + default_value { CYG_HAL_STARTUP == "ROM" } + active_if { CYG_HAL_STARTUP == "ROM" } + description " + Kinetis use FLASH locations between 0x400 and 0x40F for FLASH + security configuration. This leaves FLASH area below 0x400 + out of standard linker sections. Special section + \".kinetis_misc\" provides linker access to this area. + Setting this option instructs linker to place some HAL + (variant/platform) \"misc.\" functions in this area." + } + + cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION { + display "HAL diag. in \".kinetis_misc\" section" + flavor bool + active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION + default_value 0 + description " + By default only misc. HAL functions are stored in + \".kinetis_misc\" section. In addition HAL diagnostc + functions may be placed as well." + } + + cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES { + display "On chip memory resources" + flavor none + no_define + description " + View and manage on-chip memory resources. + Output is used for naming of 'mlt' files." + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB { + display "On chip Flash option \[KiB\]" + flavor data + calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0") + ? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB { + display "Kinetis on chip SRAM size \[KiB\]" + flavor data + calculated { + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 || + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512) ? 128 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256) ? 64 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128) ? 32 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 || + CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64) ? 16 : + (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32) ? 8 : + "Unknown" + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT { + display "SRAM layout" + flavor data + no_define + calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? + "unisram" : + "sram2s" + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT { + display "On-chip memory layout" + flavor data + no_define + calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM ? "flexnvm_": "flash_") + . CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE { + display "Kinetis on chip FLASH size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE { + display "Kinetis on chip SRAM size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE { + display "Kinetis onchip RAM bank size" + flavor data + calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 } + } + + cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE { + display "Kinetis on chip FLASH size" + flavor data + calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB + - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 } + } + + cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE { + display "Kinetis on chip FlexRAM size" + flavor data + active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM & + !CYGHWR_HAL_CORTEXM_KINETIS_EEE } + calculated { 4096 } + } + + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS { + display "Platform uses FlexBus" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS { + display "FlexBus" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS + description "FlexBus provides access for external memory." + + for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } { + + cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Platform uses Chip select [set ::chipsel]" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides chip select [set ::chipsel], and if + that chip select is used on target hardware." + } + + cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] { + display "Chip select [set ::chipsel]" + flavor bool + active_if CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] + description " + This option includes initialization data for + chip select [set ::chipsel]." + + cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS { + display "Port size (encoded)" + flavor data + calculated ( \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8 ? 1 : \ + CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3) + } + } + } + } + + cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF { + display "Flash configuration field" + flavor none + no_define + + active_if { CYG_HAL_STARTUP == "ROM" } + + description " + The program flash memory contains a 16-byte flash + configuration field that stores default protection settings + (loaded on reset) and security information that allows the MCU to + restrict access to the flash module. + Note: Changing some values in Flash configuration field may make + flash inaccessible and disable further re-programming of the flash + permanently. Consult respective Kinetis' documentation before dealing + with the Flash configuration field. Default values are equal + to the factory values." + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY { + display "Backdoor comparison key" + flavor data + default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT { + display "Program flash protection" + flavor data + default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" } + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC { + display "Flash security byte" + flavor data + default_value 0xfe + + description " + Note: FSEC default value is deliberately set to + 0xfe in order to disable chip lockout." + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT { + display "Flash nonvolatile option byte" + flavor data + default_value 0xff + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT { + display "Data flash protection byte" + flavor data + default_value 0xff + } + + cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT { + display "EEPROM protection byte" + flavor data + default_value 0xff + } + } + + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] { + display "Platform provides UART [set ::channel] HAL" + flavor bool + description " + This interface will be implemented if the specific + controller being used has on-chip UART [set ::channel], + and if that UART is accessible on the target hardware." + } + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS { + display "Platform provides HAL for UART[set ::channel] hardware flow control." + flavor bool + description " + This interface will be implemented if the specific + on-chip UART [set ::channel] has RTS/CTS flow control + that is accessible on the target hardware." + } + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS { + display "Build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package." + + cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Kinetis variant HAL package. These flags + are used in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Kinetis variant HAL package. These flags + are removed from the set of global flags if present." + } + } +} + +# EOF hal_cortexm_kinetis.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl @@ -0,0 +1,635 @@ +##========================================================================== +## +## kinetis_clocking.cdl +## +## Cortex-M Freescale Kinetis Clocking +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-10-19 +## +######DESCRIPTIONEND#### +## +##========================================================================== + + +# cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING +# display "Clocking" + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ { + display "System frequency actual value" + flavor data + calculated { + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC ? + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC : + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC ? + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC : + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV : + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV : + 0 + } + description "Operating system clock frequency." + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG { + display "MCG" + flavor data + no_define + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " . + ((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . ( + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ? + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS : + CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC) + + } + description "Multipurpose Clock Generator" + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK { + display "System clock source" + flavor data + default_value { "PLL" } + legal_values { + "PLL" "FLL" "EXT_REFCLK" + } + description " + Select one of 3 options for MCG output clock: + PLL or FLL oscillator or External reference clock." + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT { + display "EXT_REFCLK source clock settings" + flavor none + no_define + active_if { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") || + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") + } + description "Set External Reference Clock frequency and type." + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS { + display "Clock type" + flavor data + default_value { "OSC" } + legal_values { "OSC" "XTAL" "RTC"} + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000) + } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies + (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) || + ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000))) + } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768) + } + + description " + Ext reference can be External oscillator or a crystal + for the on-chip oscillator or Real Time Clock." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ { + display "Clock frequency" + flavor data + legal_values 0 to 50000000 + default_value { + is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ? + CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ : + 4000000 + } + description "External oscillator or crystal reference in Hz." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP { + display "XTAL parallel C \[pF\]" + flavor data + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } + default_value 0 + description " + The oscillator has 4 on-chip capacitors that combined + produce capacitance in parallel to the crystal." + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL { + display "FLL / PLL configuration" + flavor none + no_define + description " + PLL / FLL parameters are being calculated on a + base of required system frequrncy and output as well as + reference oscillator/frequency settings." + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP { + display "PLL/FLL output frequency set point" + flavor data + legal_values 32768 to 220000000 + calculated CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP + description "Desired PLL output frequency." + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC { + display "Reference clock source for FLL or PLL" + flavor data + default_value { "EXT_REFCLK" } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + + legal_values { "INT_RC_32KHZ" "EXT_REFCLK" } + description " + PLL/FLL oscillators can use one of 3 clock + references: External Reference Clock or Low (32768 Hz) + or High (2MHz) Frequency Internal oscillator" + } + + cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ { + display "Reference frequency." + flavor data + calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ? + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ : + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC + == "INT_RC_32KHZ" ? 32768 : 2000000 ) + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL { + display "FLL oscillator" + flavor none + no_define + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE { + display "Reference frequency range" + flavor data + legal_values 0 1 2 + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 : + CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 : + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 : + -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV { + display "Calculated FLL divider" + flavor data + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG { + display "FLL divider register value" + flavor data + legal_values 0 1 2 3 4 5 6 7 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS { + display "DCO Range Select" + flavor data + legal_values 0 1 2 3 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 { + display "DCO max. frequency with 32768 reference" + flavor data + legal_values 0 0x80 + default_value { + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) || + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 24000000)) ? + 0x80 : 0x00 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT { + display "FLL factor" + flavor data + calculated { + (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ? + ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 732 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) : + ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 640 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 : + (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 ) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN { + display "DCO input frequency" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG * + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64))) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK { + display "DCO input frequency check" + flavor data + no_define + legal_values { "OK" "NOK" "not applicable" } + calculated { + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ? + "OK" : "NOK" ) : + "NotApplicable" + } + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" } + requires { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) && + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV { + display "FLL output frequency actual value" + flavor data + calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN * + CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL { + display "PLL oscillator" + flavor none + no_define + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + calculated { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ? + 3800000 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ? + 3000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 : + 300000 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + legal_values 1 to 25 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 2000000 to 4000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV { + display "VCO Divider" + flavor data + legal_values 24 to 55 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV) : -1 + } + } + } + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC { + display "Internal Reference Clock" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 } + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "INT_REFCLK" } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI { + display "Use highh frequency internal osc." + flavor bool + default_value 1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC { + display "External Reference Clock" + flavor data + calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST { + display "Subsystem clocking" + flavor none + no_define + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS { + display "Peripheral bus" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX { + display "Frequency limit" + flavor data + default_value 50000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1) + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH { + display "Flash" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX { + display "Frequency limit" + flavor data + default_value 25000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { + !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1) + } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS { + display "Flex bus" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX { + display "Frequency limit" + flavor data + default_value 50000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP { + display "Calculated value" + flavor data + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <= + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ : + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX + } + legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS { + display "Divider" + flavor data + legal_values 1 to 16 + + default_value { + !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) : + (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1) + } + } + } + + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB { + display "USB clock" + flavor data + calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX { + display "Frequency limit" + flavor data + default_value 48000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC { + display "Fractional Divider" + flavor data + legal_values 1 to 2 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ < + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 : + ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) > + (CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 : + (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1)) + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV { + display "Divider" + flavor data + legal_values 1 to 8 + default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) % + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) ? + (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) : + ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN * + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC / + CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN { + display "USB divider input frequency" + flavor data + calculated { + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP { + display "Desired" + flavor data + calculated 48000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK { + display "Trace clock source" + flavor data + default_value { "CORE" } + legal_values { "CORE" "MCGOUT" } + + } + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT { + display "Enable Trace Clock out" + flavor bool + default_value 0 + } + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC { + } + + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC { + display "Real Time Clock" + flavor bool + default_value CYGINT_HAL_CORTEXM_KINETIS_RTC + + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP { + display "RTC XTAL parallel C \[pF\]" + flavor data + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 + 30 32 } + default_value 0 + description " + The Real Time Clock oscillator has 4 capacitors that + combined produce capacitance in parallel to the crystal." + } + } + +# EOF kinetis_clocking.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h @@ -0,0 +1,192 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2004-07-23 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// For Kinetis, for the time being these are empty macros. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h @@ -0,0 +1,92 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributor(s): ilijak +// Date: 2011-02-05 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_plf_diag_init(void); +__externC void hal_plf_diag_putc(char); +__externC cyg_uint8 hal_plf_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_plf_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc() +# endif + +#endif + + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi @@ -0,0 +1,45 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + ram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) + SECTION_data (ram, 0x20000400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram_u (0x20000000) +#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, 0x20000000 + 0x400, FOLLOWING (.got)) + SECTION_sram (sram_u, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h @@ -0,0 +1,18 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h @@ -0,0 +1,45 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +# define CYGMEM_REGION_flexnvm (0x10000000) +# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE) +# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE +# define CYGMEM_REGION_eeeprom0 (0x14000000) +# define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE) +# define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 +# define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE ) +# define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE) +# define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R) +# endif +#else +# define CYGMEM_REGION_flexram (0x14000000) +# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE) +# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi @@ -0,0 +1,67 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + ram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE +# endif +#else + flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE +#endif +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA) +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA) +# endif +#else + USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA) +#endif + SECTION_data (ram, 0x20000400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h @@ -0,0 +1,22 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram_u (0x20000000) +#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram_l, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram_u, 0x20000000 + 0x400, FOLLOWING (.got)) + SECTION_sram (sram_u, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h @@ -0,0 +1,42 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif + +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +# define CYGMEM_REGION_flexnvm (0x10000000) +# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE) +# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE +# define CYGMEM_REGION_eeeprom0 (0x14000000) +# define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE) +# define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 +# define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE ) +# define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE) +# define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R) +# endif +#else +# define CYGMEM_REGION_flexram (0x14000000) +# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE) +# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi @@ -0,0 +1,65 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE +# endif +#else + flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE +#endif +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) +#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE + USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA) +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE + USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA) +# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1 + USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA) +# endif +#else + USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA) +#endif + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h @@ -0,0 +1,18 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, +// 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:jskov, gthomas, jlarmour +// Date: 2008-07-30 +// Purpose: Platform HAL stub support for Kinetis variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Kinetis variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, ilijak +// Date: 2011-02-05 +// Purpose: Kinetis variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_intr.h @@ -0,0 +1,223 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for Kinetis variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for Freescale Kinetis variants are +// defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + +typedef enum { + CYGNUM_HAL_INTERRUPT_DMA0 + = CYGNUM_HAL_INTERRUPT_EXTERNAL, // DMA Channel 0 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA1, // DMA Channel 1 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA2, // DMA Channel 2 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA3, // DMA Channel 3 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA4, // DMA Channel 4 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA5, // DMA Channel 5 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA6, // DMA Channel 6 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA7, // DMA Channel 7 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA8, // DMA Channel 8 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA9, // DMA Channel 9 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA10, // DMA Channel 10 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA11, // DMA Channel 11 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA12, // DMA Channel 12 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA13, // DMA Channel 13 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA14, // DMA Channel 14 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA15, // DMA Channel 15 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA_ERROR, // DMA Error Int + CYGNUM_HAL_INTERRUPT_MCM, // Normal Int + CYGNUM_HAL_INTERRUPT_FTFL, // FTFL Int + CYGNUM_HAL_INTERRUPT_READ_COLLISION, // Read Collision Int + CYGNUM_HAL_INTERRUPT_LVD_LVW, // Low Volt Detect, Low Volt Warn + CYGNUM_HAL_INTERRUPT_LLW, // Low Leakage Wakeup + CYGNUM_HAL_INTERRUPT_WDOG, // WDOG Int + CYGNUM_HAL_INTERRUPT_RNGB, // RNGB Int + CYGNUM_HAL_INTERRUPT_I2C0, // I2C0 int + CYGNUM_HAL_INTERRUPT_I2C1, // I2C1 int + CYGNUM_HAL_INTERRUPT_SPI0, // SPI0 Int + CYGNUM_HAL_INTERRUPT_SPI1, // SPI1 Int + CYGNUM_HAL_INTERRUPT_SPI2, // SPI2 Int + CYGNUM_HAL_INTERRUPT_CAN0_ORED_MESSAGE_BUFFER,// CAN0 OR'd Msg Buffs Int + CYGNUM_HAL_INTERRUPT_CAN0_BUS_OFF, // CAN0 Bus Off Int + CYGNUM_HAL_INTERRUPT_CAN0_ERROR, // CAN0 Error Int + CYGNUM_HAL_INTERRUPT_CAN0_TX_WARNING, // CAN0 Tx Warning Int + CYGNUM_HAL_INTERRUPT_CAN0_RX_WARNING, // CAN0 Rx Warning Int + CYGNUM_HAL_INTERRUPT_CAN0_WAKE_UP, // CAN0 Wake Up Int + CYGNUM_HAL_INTERRUPT_CAN0_IMEU, // CAN0 Ind. Match El Update (IMEU) Int + CYGNUM_HAL_INTERRUPT_CAN0_LOST_RX, // CAN0 Lost Receive Int + CYGNUM_HAL_INTERRUPT_CAN1_ORED_MESSAGE_BUFFER, // CAN1 OR'd Msg Buffs Int + CYGNUM_HAL_INTERRUPT_CAN1_BUS_OFF, // CAN1 Bus Off Int + CYGNUM_HAL_INTERRUPT_CAN1_ERROR, // CAN1 Error Int + CYGNUM_HAL_INTERRUPT_CAN1_TX_WARNING, // CAN1 Tx Warning Int + CYGNUM_HAL_INTERRUPT_CAN1_RX_WARNING, // CAN1 Rx Warning Int + CYGNUM_HAL_INTERRUPT_CAN1_WAKE_UP, // CAN1 Wake Up Int + CYGNUM_HAL_INTERRUPT_CAN1_IMEU, // CAN1 Ind. Match El Update (IMEU) Int + CYGNUM_HAL_INTERRUPT_CAN1_LOST_RX, // CAN1 Lost Receive Int + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, // UART0 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART0_ERR, // UART0 Error int + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, // UART1 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART1_ERR, // UART1 Error int + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, // UART2 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART2_ERR, // UART2 Error int + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, // UART3 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART3_ERR, // UART3 Error int + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, // UART4 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART4_ERR, // UART4 Error int + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, // UART5 Receive/Transmit int + CYGNUM_HAL_INTERRUPT_UART5_ERR, // UART5 Error int + CYGNUM_HAL_INTERRUPT_ADC0, // ADC0 int + CYGNUM_HAL_INTERRUPT_ADC1, // ADC1 int + CYGNUM_HAL_INTERRUPT_CMP0, // CMP0 int + CYGNUM_HAL_INTERRUPT_CMP1, // CMP1 int + CYGNUM_HAL_INTERRUPT_CMP2, // CMP2 int + CYGNUM_HAL_INTERRUPT_FTM0, // FTM0 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_FTM1, // FTM1 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_FTM2, // FTM2 fault, overflow and channels int + CYGNUM_HAL_INTERRUPT_CMT, // CMT int + CYGNUM_HAL_INTERRUPT_RTC, // RTC int + CYGNUM_HAL_INTERRUPT_Reserved83, // Reserved int 83 + CYGNUM_HAL_INTERRUPT_PIT0, // PIT timer channel 0 int + CYGNUM_HAL_INTERRUPT_PIT1, // PIT timer channel 1 int + CYGNUM_HAL_INTERRUPT_PIT2, // PIT timer channel 2 int + CYGNUM_HAL_INTERRUPT_PIT3, // PIT timer channel 3 int + CYGNUM_HAL_INTERRUPT_PDB0, // PDB0 Int + CYGNUM_HAL_INTERRUPT_USB0, // USB0 int + CYGNUM_HAL_INTERRUPT_USBDCD, // USBDCD Int + CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER, // ENET MAC IEEE 1588 Timer Int + CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT, // ENET MAC Transmit Int + CYGNUM_HAL_INTERRUPT_ENET_RECEIVE, // ENET MAC Receive Int + CYGNUM_HAL_INTERRUPT_ENET_ERROR, // ENET MAC Error and miscelaneous Int + CYGNUM_HAL_INTERRUPT_I2S0, // I2S0 Int + CYGNUM_HAL_INTERRUPT_SDHC, // SDHC Int + CYGNUM_HAL_INTERRUPT_DAC0, // DAC0 int + CYGNUM_HAL_INTERRUPT_DAC1, // DAC1 int + CYGNUM_HAL_INTERRUPT_TSI0, // TSI0 Int + CYGNUM_HAL_INTERRUPT_MCG, // MCG Int + CYGNUM_HAL_INTERRUPT_LPTIMER, // LPTimer int + CYGNUM_HAL_INTERRUPT_LCD, // Segment LCD int + CYGNUM_HAL_INTERRUPT_PORTA, // Port A int + CYGNUM_HAL_INTERRUPT_PORTB, // Port B int + CYGNUM_HAL_INTERRUPT_PORTC, // Port C int + CYGNUM_HAL_INTERRUPT_PORTD, // Port D int + CYGNUM_HAL_INTERRUPT_PORTE, // Port E int + CYGNUM_HAL_INTERRUPT_Reserved108, // Reserved int 108 + CYGNUM_HAL_INTERRUPT_Reserved109, // Reserved int 109 + CYGNUM_HAL_INTERRUPT_Reserved110, // Reserved int 110 + CYGNUM_HAL_INTERRUPT_Reserved111, // Reserved int 111 + CYGNUM_HAL_INTERRUPT_Reserved112, // Reserved int 112 + CYGNUM_HAL_INTERRUPT_Reserved113, // Reserved int 113 + CYGNUM_HAL_INTERRUPT_Reserved114, // Reserved int 114 + CYGNUM_HAL_INTERRUPT_Reserved115, // Reserved int 115 + CYGNUM_HAL_INTERRUPT_Reserved116, // Reserved int 116 + CYGNUM_HAL_INTERRUPT_Reserved117, // Reserved int 117 + CYGNUM_HAL_INTERRUPT_Reserved118, // Reserved int 118 + CYGNUM_HAL_INTERRUPT_Reserved119 // Reserved int 119 +} KinetisExtInterrupt_e; + +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_Reserved119) + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_Reserved119 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+ \ + CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif + +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//========================================================================== +// Interrupt mask and config for variant-specific devices + +// PORT Pin interrupts + +#define CYGHWR_HAL_KINETIS_PIN_IRQ_VECTOR(__pin) \ + (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_KINETIS_PIN_PORT(__pin)) + +//=========================================================================== +// Interrupt resources exported by HAL to device drivers + +// Export Interrupt vectors to serial driver. + +#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART0_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART1_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART2_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART3_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART4_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART5_RX_TX + +// Export Interrupt vectors to ENET driver. + +#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER +#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT +#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_RECEIVE +#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_ERROR + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h @@ -0,0 +1,1043 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//=========================================================================== +// +// var_io.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal_cortexm_kinetis.h> + +#include <cyg/hal/plf_io.h> + +//=========================================================================== +// Cortex-M architecture +//--------------------------------------------------------------------------- +//-------------------------------------------------------------------------- +// Cortex-M architecture overrides +//--------------------------------------------------------------------------- +// VTOR - Vector Table Offset Register +#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED +# define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) - \ + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +# else +# define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM BIT_(29) +# endif +#endif + +//============================================================================= +// Kinetis system configuration +//--------------------------------------------------------------------------- +// Utilize Freescale Kinetis flash between startup vectors and 0x400 +// for misc funtions. +#ifdef CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION +# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR \ + CYGBLD_ATTRIB_SECTION(".kinetis_misc") +#else +# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +#endif + +//=========================================================================== +// KINETIS FLASH configuration field +//=========================================================================== + +// Note: KINETIS FLASH configuration field must be present in Kinetis flash +// image and ocupy addresses 0x00000400 to 0x0000040f. + +typedef struct cyghwr_hal_kinetis_flash_conf_s { + cyg_uint8 backdoor_key[8]; // 0x400 .. 0x407 + cyg_uint8 fprot[4]; // 0x408 .. 0x40b + cyg_uint8 fsec; // 0x40c + cyg_uint8 fopt; // 0x40d + cyg_uint8 feprot; // 0x40e + cyg_uint8 fdprot; // 0x40f +} cyghwr_hal_kinetis_flash_conf_t; + +__externC const cyghwr_hal_kinetis_flash_conf_t *hal_kinetis_flash_conf_p( void ); + +//=========================================================================== +// Kinetis Peripherals +//--------------------------------------------------------------------------- +// Oscillator + +#define CYGHWR_HAL_KINETIS_OSC_CR (0x40065000) +#define CYGHWR_HAL_KINETIS_OSC_CR_P ((volatile cyg_uint8*) 0x40065000) + +#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_M 0x01 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_S 0 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_M 0x02 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_S 1 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_M 0x04 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_S 2 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_M 0x08 +#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_S 3 +#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M 0x20 +#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_S 5 +#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M 0x80 +#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_S 7 + +//--------------------------------------------------------------------------- +// MCG + +typedef volatile struct cyghwr_hal_kinetis_mcg_s { + cyg_uint8 c1; // MCG Control 1 Register + cyg_uint8 c2; // MCG Control 2 Register + cyg_uint8 c3; // MCG Control 3 Register + cyg_uint8 c4; // MCG Control 4 Register + cyg_uint8 c5; // MCG Control 5 Register + cyg_uint8 c6; // MCG Control 6 Register + cyg_uint8 status; // MCG Status Register + cyg_uint8 mcg_res0; + cyg_uint8 atc; // MCG Auto Trim Control Register + cyg_uint8 mcg_res1; + cyg_uint8 atcvh; // MCG Auto Trim Compare Value High Register + cyg_uint8 atcvl; // MCG Auto Trim Compare Value Low Register +} cyghwr_hal_kinetis_mcg_t; + +#define CYGHWR_HAL_KINETIS_MCG_P ((cyghwr_hal_kinetis_mcg_t *)0x40064000) + +// C1 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_M 0x4 +#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_M 0x38 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(_div_) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S, _div_) +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M 0xC0 +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS(_clks_) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S, _clks_) +enum { + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_FLL_PLL, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_INT_REF, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF, + CYGHWR_HAL_KINETIS_MCG_C1_CLKS_RESERVED +}; +// C2 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C2_LP_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_C2_LP_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M 0x04 +#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_M 0x08 +#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_M 0x30 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S, __v) +// C3 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S, __v) +// C4 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_M 0x1E +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S 1 +#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_M 0x60 +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_S 7 +// C5 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_S 6 +// C6 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C6_CME_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C6_CME_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_S 7 +// S Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_S 0 +#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_S 1 +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_M 0x0C +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_S 2 +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_S_CLKST_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL CYGHWR_HAL_KINETIS_MCG_S_CLKST(0) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_INT CYGHWR_HAL_KINETIS_MCG_S_CLKST(1) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT CYGHWR_HAL_KINETIS_MCG_S_CLKST(2) +#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL CYGHWR_HAL_KINETIS_MCG_S_CLKST(3) +#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_S 4 +#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_S 5 +#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_S 6 +#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_S 7 +// ATC Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_S 5 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_S 7 +// ATCVH Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S 0 +#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S, __v) +// ATCVL Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_M 0xFF +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S 0 +#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v) + +//--------------------------------------------------------------------------- +// Real Time Clock + +typedef volatile struct cyghwr_hal_kinetis_rtc_s { + cyg_uint32 tsr; // Time Seconds Register + cyg_uint32 tpr; // Time Prescaler Register + cyg_uint32 tar; // Time Alarm Register + cyg_uint32 tcr; // Time Compensation Register + cyg_uint32 cr; // Control Register + cyg_uint32 sr; // Status Register + cyg_uint32 lr; // Lock Register + cyg_uint32 ier; // Enterrupt Enable Register + cyg_uint8 reserved[2016]; + cyg_uint32 war; // Write Access Register + cyg_uint32 rar; // Read Access Register +} cyghwr_hal_kinetis_rtc_t; + +#define CYGHWR_HAL_KINETIS_RTC_P ((cyghwr_hal_kinetis_rtc_t *)0x4003D000) + +#define CYGHWR_HAL_KINETIS_RTC_TCR_TCR_M (0x000000FF) +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S 8 +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S, _div_) +#define CYGHWR_HAL_KINETIS_RTC_TCR_CIC_S 16 +#define CYGHWR_HAL_KINETIS_RTC_TCR_TCV_S 24 + +#define CYGHWR_HAL_KINETIS_RTC_CR_SWR BIT_(0) +#define CYGHWR_HAL_KINETIS_RTC_CR_WPE BIT_(1) +#define CYGHWR_HAL_KINETIS_RTC_CR_SUP BIT_(2) +#define CYGHWR_HAL_KINETIS_RTC_CR_UM BIT_(3) +#define CYGHWR_HAL_KINETIS_RTC_CR_OSCE BIT_(8) +#define CYGHWR_HAL_KINETIS_RTC_CR_CLKO BIT_(9) +#define CYGHWR_HAL_KINETIS_RTC_CR_SCP \ + VALUE_(10, (CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP/2)) + +#define CYGHWR_HAL_KINETIS_RTC_SR_TCE BIT_(4) +#define CYGHWR_HAL_KINETIS_RTC_SR_TAF BIT_(2) +#define CYGHWR_HAL_KINETIS_RTC_SR_TOF BIT_(1) +#define CYGHWR_HAL_KINETIS_RTC_SR_TIF BIT_(0) + +//--------------------------------------------------------------------------- +// Watch dog + +// WDOG - Peripheral register structure +typedef volatile struct CygHwr_HAL_Kinetis_wdog_s { + cyg_uint16 StCtrlH; // Status and Control Register High + cyg_uint16 StCtrlL; // Status and Control Register Low + cyg_uint16 ToValH; // Time-out Value Register High + cyg_uint16 ToValL; // Time-out Value Register Low + cyg_uint16 WinH; // Window Register High + cyg_uint16 WinL; // Window Register Low + cyg_uint16 Refresh; // Refresh Register + cyg_uint16 Unlock; // Unlock Register + cyg_uint16 TmrOutH; // Timer Output Register High + cyg_uint16 TmrOutL; // Timer Output Register Low + cyg_uint16 RstCnt; // Reset Count Register + cyg_uint16 Presc; // Prescaler Register +} CygHwr_HAL_Kinetis_wdog_t; + +#define CYGHWR_HAL_KINETIS_WDOG_P ((CygHwr_HAL_Kinetis_wdog_t *)0x40052000) + +// STCTRLH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_M 0x0001 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_M 0x0002 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_S 1 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_M 0x0004 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_S 2 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_M 0x0008 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_S 3 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M 0x0010 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_S 4 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_M 0x0020 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_S 5 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_M 0x0040 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_S 6 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_M 0x0080 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_S 7 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_M 0x0100 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_S 8 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_M 0x0400 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_S 10 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_M 0x0800 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_S 11 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_M 0x3000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S 12 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S, __v) +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_M 0x4000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_S 14 +// STCTRLL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_M 0x8000 +#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_S 15 +// TOVALH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S, __v) +// TOVALL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S, __v) +// WINH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S, __v) +// WINL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S, __v) +// REFRESH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S, __v) +// UNLOCK Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S, __v) +// TMROUTH Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S, __v) +// TMROUTL Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S, __v) +// RSTCNT Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_M 0xFFFF +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S 0 +#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S, __v) +// PRESC Bit Fields +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_M 0x700 +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S 8 +#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL(__v) \ + VALUE(CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S, __v) + +#ifndef __ASSEMBLER__ + +__externC void hal_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p); +__externC void hal_wdog_disable(void); + +#endif // __ASSEMBLER__ + +//--------------------------------------------------------------------------- +// SIM - System Integration Module + +// SIM - Peripheral register structure +typedef volatile struct cyghwr_hal_kinetis_sim_s { + cyg_uint32 sopt1; // System Options Register 1 + cyg_uint8 reserved_0[4096]; + cyg_uint32 sopt2; // System Options Register 2 + cyg_uint8 reserved_1[4]; + cyg_uint32 sopt4; // System Options Register 4 + cyg_uint32 sopt5; // System Options Register 5 + cyg_uint32 sopt6; // System Options Register 6 + cyg_uint32 sopt7; // System Options Register 7 + cyg_uint8 Reserved_2[8]; + cyg_uint32 sdid; // System Device Identification Register + cyg_uint32 scgc1; // System Clock Gating Control Register 1 + cyg_uint32 scgc2; // System Clock Gating Control Register 2 + cyg_uint32 scgc3; // System Clock Gating Control Register 3 + cyg_uint32 scgc4; // System Clock Gating Control Register 4 + cyg_uint32 scgc5; // System Clock Gating Control Register 5 + cyg_uint32 scgc6; // System Clock Gating Control Register 6 + cyg_uint32 scgc7; // System Clock Gating Control Register 7 + cyg_uint32 clk_div1; // System Clock Divider Register 1 + cyg_uint32 clk_div2; // System Clock Divider Register 2 + cyg_uint32 fcfg1; // Flash Configuration Register 1 + cyg_uint32 fcfg2; // Flash Configuration Register 2 + cyg_uint32 uidh; // Unique Identification Register High + cyg_uint32 uidmh; // Unique Identification Register Mid-High + cyg_uint32 uidml; // Unique Identification Register Mid Low + cyg_uint32 uidl; // Unique Identification Register Low +} cyghwr_hal_kinetis_sim_t; + +#define CYGHWR_HAL_KINETIS_SIM_P ((cyghwr_hal_kinetis_sim_t *) 0x40047000) + +// SOPT1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_M 0xF000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_M 0x80000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_S 19 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_S 23 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_M 0x40000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_S 30 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_M 0x80000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_S 31 +// SOPT2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_M 0x300 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M 0x10000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_S 16 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_M 0x300000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_M 0x3000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_M 0x30000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S 28 +#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S, __val) +// SOPT4 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_M 0x100 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_M 0xC0000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_M 0x300000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_M 0x4000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_S 26 +// SOPT5 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_M 0x3 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_M 0xC +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_M 0x30 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_M 0xC0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S 6 +#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S, __val) +// SOPT6 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_M 0x1F000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_M 0xE0000000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S 29 +#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S, __val) +// SOPT7 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_M 0xF +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_M 0x80 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_S 7 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_M 0xF00 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S 8 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_S 15 +// SDID Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_M 0xF +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_M 0x70 +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_M 0xF000 +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val) +// SCGC1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S 11 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M | CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M) + +// SCGC2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S 13 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M) + +// SCGC3 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M 0x20000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S 17 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S 27 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M) + +// SCGC4 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S 2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M 0x40 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S 6 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M 0x80 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S 7 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M 0x80000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S 19 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M 0x100000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S 20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S 28 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M |\ + CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M |\ + CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M) + +// SCGC5 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S 5 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M 0x200 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S 9 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M 0x400 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S 10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M 0x800 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S 11 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S 13 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +// SCGC6 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M 0x10 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S 4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_M 0x1000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_S 12 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M 0x2000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S 13 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M 0x8000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S 15 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M 0x40000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S 18 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M 0x200000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S 21 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M 0x400000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S 22 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S 23 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M 0x1000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S 24 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M 0x2000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S 25 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M 0x8000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M 0x20000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S 29 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M) + +// SCGC7 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S 0 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S 2 + +#define CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M) + +// CLKDIV1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M 0xF0000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S 16 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_M 0xF00000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S 20 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_M 0xF000000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S 24 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_M 0xF0000000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S 28 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S, __val) +// CLKDIV2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_S 0 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_M 0xE +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S 1 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_M 0xFF00 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S 8 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_M 0xFFF00000 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S 20 +#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S, __val) +// FCFG1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_M 0xF00 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S 8 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_M 0xF0000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S 16 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_M 0xFF000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S 24 +#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S, __val) +// FCFG2 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_M 0x3F0000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S 16 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_M 0x800000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_S 23 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_M 0x3F000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S 24 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_M 0x80000000 +#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_S 31 +// UIDH Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S, __val) +// UIDMH Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S, __val) +// UIDML Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S, __val) +// UIDL Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S 0 +#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S, __val) + +//--------------------------------------------------------------------------- +// PORT - Peripheral register structure + +typedef volatile struct cyghwr_hal_kinetis_port_s { + cyg_uint32 pcr[32]; // Pin Control Register n, array + cyg_uint32 gpclr; // Global Pin Control Low Register + cyg_uint32 gpchr; // Global Pin Control High Register + cyg_uint8 reserved0[24]; + cyg_uint32 isfr; // Interrupt Status Flag Register + cyg_uint8 reserved1[28]; + cyg_uint32 dfer; // Digital Filter Enable Register + cyg_uint32 dfcr; // Digital Filter Clock Register + cyg_uint32 dfwr; // Digital Filter Width Register +} cyghwr_hal_kinetis_port_t; + +// PORT - Peripheral instance base addresses +#define CYGHWR_HAL_KINETIS_PORTA_P (cyghwr_hal_kinetis_port_t *)0x40049000 +#define CYGHWR_HAL_KINETIS_PORTB_P (cyghwr_hal_kinetis_port_t *)0x4004A000 +#define CYGHWR_HAL_KINETIS_PORTC_P (cyghwr_hal_kinetis_port_t *)0x4004B000 +#define CYGHWR_HAL_KINETIS_PORTD_P (cyghwr_hal_kinetis_port_t *)0x4004C000 +#define CYGHWR_HAL_KINETIS_PORTE_P (cyghwr_hal_kinetis_port_t *)0x4004D000 + +enum { + CYGHWR_HAL_KINETIS_PORTA, CYGHWR_HAL_KINETIS_PORTB, + CYGHWR_HAL_KINETIS_PORTC, CYGHWR_HAL_KINETIS_PORTD, + CYGHWR_HAL_KINETIS_PORTE +}; + +// PCR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_M 0x1 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_S 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_M 0x2 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_S 1 +#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M 0x4 +#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_S 2 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_M 0x10 +#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_S 4 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_M 0x20 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_S 5 +#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M 0x40 +#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_S 6 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_M 0x700 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S 8 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_M 0x8000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_S 15 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_M 0xF0000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S 16 +#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_M 0x1000000 +#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_S 24 + +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_ANALOG 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_DIS 0 +#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO 1 + +#define CYGHWR_HAL_KINETIS_PIN(__port, __bit, __mux, __cnf) \ + ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | (__bit << 27) \ + | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | __cnf) + +#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) ((__pin >> 20) & 0x7) +#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin) ((__pin >> 27 ) & 0x1f) +#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) (__pin & 0x010f8777) +#define CYGHWR_HAL_KINETIS_PIN_NONE (0xffffffff) + +// GPCLR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_M 0xFFFF +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S 0 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S 16 +#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S, __val) +// GPCHR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_M 0xFFFF +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S 0 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S, __val) +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S 16 +#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S, __val) +// ISFR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S 0 +#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S, __val) +// DFER Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_M 0xFFFFFFFF +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S 0 +#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S, __val) +// DFCR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_M 0x1 +#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_S 0 +// DFWR Bit Fields +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_M 0x1F +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S 0 +#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S, __val) + +#ifndef __ASSEMBLER__ + +// Pin configuration related functions +__externC void hal_set_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_setting(cyg_uint32 pin); + +#endif + +#define HAL_SET_PINS(_pin_array) \ +CYG_MACRO_START \ + const cyg_uint32 *_pin_p; \ + for(_pin_p = &_pin_array[0]; \ + _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \ + hal_set_pin_function(*_pin_p++)); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// FMC Flash Memory Controller + +#define CYGHWR_HAL_KINETIS_FMC_BASE (0x4001F000) +#define CYGHWR_HAL_KINETIS_FMC_PFAPR (CYGHWR_HAL_KINETIS_FMC_BASE) +#define CYGHWR_HAL_KINETIS_FMC_PFB0CR (CYGHWR_HAL_KINETIS_FMC_BASE + 4) +#define CYGHWR_HAL_KINETIS_FMC_PFB1CR (CYGHWR_HAL_KINETIS_FMC_BASE + 8) + +enum { + CYGHWR_HAL_KINETIS_FMC_CACHE_W0, + CYGHWR_HAL_KINETIS_FMC_CACHE_W1, + CYGHWR_HAL_KINETIS_FMC_CACHE_W2, + CYGHWR_HAL_KINETIS_FMC_CACHE_W3, + CYGHWR_HAL_KINETIS_FMC_CACHE_WAYS +}; + +enum { + CYGHWR_HAL_KINETIS_FMC_CACHE_S0, + CYGHWR_HAL_KINETIS_FMC_CACHE_S1, + CYGHWR_HAL_KINETIS_FMC_CACHE_S2, + CYGHWR_HAL_KINETIS_FMC_CACHE_S3, + CYGHWR_HAL_KINETIS_FMC_CACHE_S4, + CYGHWR_HAL_KINETIS_FMC_CACHE_S5, + CYGHWR_HAL_KINETIS_FMC_CACHE_S6, + CYGHWR_HAL_KINETIS_FMC_CACHE_S7, + CYGHWR_HAL_KINETIS_FMC_CACHE_SIDES +}; + +#define CYGHWR_HAL_KINETIS_FMC_TAG(__way,__side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + __way*0x20 + __side*4) +#define CYGHWR_HAL_KINETIS_FMC_DATA_U(__way,side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + --way*0x20 + __side*8) +#define CYGHWR_HAL_KINETIS_FMC_DATA_L(__way,side) \ + (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + --way*0x40 + __side*8) + +#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << (__master + 16)) +enum { + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_NO_ACCESS, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RO, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_WO, + CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RW +}; +#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP(__master, __access) \ + (__access <<(2 * __master)) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_RWSC_M (0xf0000000) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << __way) << 24) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_ALL \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << __way) << 20) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_ALL \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_SBINV (1 << 19) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BMW (7 << 17) + +enum{ + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_LRU, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_res0, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW01IF23D, + CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW02ID3D +}; +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC (__cache_repl_con) \ + (__cache_repl_con << 5) + +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE (0x10) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE (0x08) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE (0x04) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE (0x02) +#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01) + +//--------------------------------------------------------------------------- +// MPU Memory Protection unit + +typedef volatile struct cyghwr_hal_kinetis_mpu_s { + cyg_uint32 cesr; // Control/Error Status Register + cyg_uint8 reserved0[12]; + struct { + cyg_uint32 ear; // Error Address Register, Slave Port n + cyg_uint32 edr; // Error Detail Register, Slave Port n + } slave_port[5]; + cyg_uint8 reserved1[968]; + struct { // Region Descriptors, Word 0..Region Descriptor n, Word 3 + cyg_uint32 word[4]; + }reg_desc[12]; + cyg_uint8 reserved2[832]; + cyg_uint32 reg_daac[12]; // Region Descriptor Alternate Access Control n +} cyghwr_hal_kinetis_mpu_t; + +#define CYGHWR_HAL_KINETIS_MPU_P (cyghwr_hal_kinetis_mpu_t *)0x4000d000 + +//--------------------------------------------------------------------------- +// FlexBus +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS +# include <cyg/hal/var_io_flexbus.h> +#endif + +//============================================================================= +// DEVS: +// Following macros may also be, and usually are borrwed by some device drivers. +//----------------------------------------------------------------------------- +#include <cyg/hal/var_io_devs.h> + +// End Peripherals + +//----------------------------------------------------------------------------- +// end of var_io.h + +#endif // CYGONCE_HAL_VAR_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h @@ -0,0 +1,148 @@ +#ifndef CYGONCE_HAL_VAR_IO_DEVS_H +#define CYGONCE_HAL_VAR_IO_DEVS_H +//=========================================================================== +// +// var_io_devs.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant IO provided to various device drivers +// Description: +// Usage: #include <cyg/hal/var_io.h> //var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//============================================================================= +// DEVS: +// Following macros may be, and usually are borrwed by some device drivers. +//----------------------------------------------------------------------------- +// Freescale UART +// Borrow some HAL resources to Freescale UART driver +// UART macros are used by both: +// src/hal_diag.c +// devs/serial/<version>/src/ser_freescale_uart.c + +#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE 0x4006A000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE 0x4006B000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE 0x4006C000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE 0x4006D000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE 0x400EA000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE 0x400EB000 + +// UART PIN configuration +// Note: May be overriden by plf_io.h + +#define CYGHWR_HAL_KINETIS_PORT_PIN_NONE CYGHWR_HAL_KINETIS_PIN_NONE + +#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX +# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX +# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX +# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX +# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX +# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +#endif + +// Lend some HAL dependent functions to the UART serial device driver + +#ifndef __ASSEMBLER__ + +# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \ + hal_freescale_uart_setbaud(__uart_p, _baud_) + +# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \ + hal_set_pin_function(__pin) + +// Set baud rate +__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif + +//--------------------------------------------------------------------------- +// ENET +// Lend some HAL dependent functions to the Ethernet device driver +#define CYGADDR_IO_ETH_FREESCALE_ENET0_BASE (0x400C0000) + +#ifndef __ASSEMBLER__ + +# define CYGHWR_IO_FREESCALE_ENET_PIN(__pin) \ + hal_set_pin_function(__pin) + +#endif + +//----------------------------------------------------------------------------- +// end of var_io_devs.h +#endif // CYGONCE_HAL_VAR_IO_DEVS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h @@ -0,0 +1,173 @@ +#ifndef CYGONCE_HAL_VAR_IO_FLEXBUS_H +#define CYGONCE_HAL_VAR_IO_FLEXBUS_H +//=========================================================================== +// +// var_io_flexbus.h +// +// Kinetis FlexBus specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//--------------------------------------------------------------------------- +// FlexBus + +// FlexBus chip select control registers +typedef struct cyghwr_hal_kinetis_fbcs_s{ + cyg_uint32 csar; // Chip select address register + cyg_uint32 csmr; // Chip select mask register + cyg_uint32 cscr; // Chip select control register +} cyghwr_hal_kinetis_fbcs_t; + +#define CYGNUM_HAL_KINETIS_FBCS_N 6 // Kinetis has up to 6 chip selects + +// FlexBus control +typedef volatile struct cyghwr_hal_kinetis_fb_s { + cyghwr_hal_kinetis_fbcs_t csel[CYGNUM_HAL_KINETIS_FBCS_N]; //Chip Selects + cyg_uint8 reserved[24]; + cyg_uint32 cspmcr; //Chip select port multiplexing control register +} cyghwr_hal_kinetis_fb_t; + +#define CYGHWR_HAL_KINETIS_FB_P ((cyghwr_hal_kinetis_fb_t *) 0x4000C000) + +// CSAR - Chip Select Address Register +// CSAR Bit Fields +#define CYGHWR_HAL_FB_CSAR_BA_M 0xFFFF0000 +#define CYGHWR_HAL_FB_CSAR_BA_S 16 +#define CYGHWR_HAL_FB_CS_AR_BA(__val) VALUE_(CYGHWR_HAL_FB_CSAR_BA_S, __val) + +// CSMR - Chup Select Mask Register +// CSMR Bit Fields +#define CYGHWR_HAL_FB_CSMR_V_M 0x1 +#define CYGHWR_HAL_FB_CSMR_V_S 0 +#define CYGHWR_HAL_FB_CSMR_WP_M 0x100 +#define CYGHWR_HAL_FB_CSMR_WP_S 8 +#define CYGHWR_HAL_FB_CSMR_BAM_M 0xFFFF0000 +#define CYGHWR_HAL_FB_CSMR_BAM_S 16 +#define CYGHWR_HAL_FB_CS_MR_BAM(__val) VALUE_(CYGHWR_HAL_FB_CSMR_BAM_S, __val) + +// CSCR - Chip Select Control register +// CSCR Bit Fields +#define CYGHWR_HAL_FB_CSCR_BSTW_M 0x8 +#define CYGHWR_HAL_FB_CSCR_BSTW_S 3 +#define CYGHWR_HAL_FB_CSCR_BSTR_M 0x10 +#define CYGHWR_HAL_FB_CSCR_BSTR_S 4 +#define CYGHWR_HAL_FB_CSCR_BEM_M 0x20 +#define CYGHWR_HAL_FB_CSCR_BEM_S 5 +#define CYGHWR_HAL_FB_CSCR_PS_M 0xC0 +#define CYGHWR_HAL_FB_CSCR_PS_S 6 +#define CYGHWR_HAL_FB_CSCR_AA_M 0x100 +#define CYGHWR_HAL_FB_CSCR_AA_S 8 +#define CYGHWR_HAL_FB_CSCR_BLS_M 0x200 +#define CYGHWR_HAL_FB_CSCR_BLS_S 9 +#define CYGHWR_HAL_FB_CSCR_WS_M 0xFC00 +#define CYGHWR_HAL_FB_CSCR_WS_S 10 +#define CYGHWR_HAL_FB_CSCR_WRAH_M 0x30000 +#define CYGHWR_HAL_FB_CSCR_WRAH_S 16 +#define CYGHWR_HAL_FB_CSCR_RDAH_M 0xC0000 +#define CYGHWR_HAL_FB_CSCR_RDAH_S 18 +#define CYGHWR_HAL_FB_CSCR_ASET_M 0x300000 +#define CYGHWR_HAL_FB_CSCR_ASET_S 20 +#define CYGHWR_HAL_FB_CSCR_EXALE_M 0x400000 +#define CYGHWR_HAL_FB_CSCR_EXALE_S 22 +#define CYGHWR_HAL_FB_CSCR_SWSEN_M 0x800000 +#define CYGHWR_HAL_FB_CSCR_SWSEN_S 23 +#define CYGHWR_HAL_FB_CSCR_SWS_M 0xFC000000 +#define CYGHWR_HAL_FB_CSCR_SWS_S 26 + +// CSPMCR Bit Fields +#define CYGHWR_HAL_FB_CSPMCR_G5_M 0xF000 +#define CYGHWR_HAL_FB_CSPMCR_G5_S 12 +#define CYGHWR_HAL_FB_CSPMCR_G4_M 0xF0000 +#define CYGHWR_HAL_FB_CSPMCR_G4_S 16 +#define CYGHWR_HAL_FB_CSPMCR_G3_M 0xF00000 +#define CYGHWR_HAL_FB_CSPMCR_G3_S 20 +#define CYGHWR_HAL_FB_CSPMCR_G2_M 0xF000000 +#define CYGHWR_HAL_FB_CSPMCR_G2_S 24 +#define CYGHWR_HAL_FB_CSPMCR_G1_M 0xF0000000 +#define CYGHWR_HAL_FB_CSPMCR_G1_S 28 + +// FlexBus control pin multiplexing +#define CYGHWR_HAL_FB_CSPMCR(__group, __val) VALUE_(__group, __val) + +#define CYGHWR_HAL_FB_CSPMCR_G1_ALE \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G1_CS1 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G1_TS \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G2_CS4 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G2_TSIZ0 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G3_CS5 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G3_TSIZ1 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G4_TST \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G4_CS2 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G4_BE_15_8 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 2) + +#define CYGHWR_HAL_FB_CSPMCR_G5_TA \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 0) +#define CYGHWR_HAL_FB_CSPMCR_G5_CS3 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 1) +#define CYGHWR_HAL_FB_CSPMCR_G5_BE_7_0 \ + CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 2) + +//----------------------------------------------------------------------------- +// end of var_io_flexbus.h +#endif // CYGONCE_HAL_VAR_IO_FLEXBUS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/variant.inc @@ -0,0 +1,53 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, ilijak +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_kinetis.h> + +//========================================================================== +// EOF variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c @@ -0,0 +1,407 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-04 +// Purpose: HAL diagnostic input/output +// Description: Implementations of HAL diagnostic input/output support. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + */ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/var_io.h> // +#include <cyg/io/ser_freescale_uart.h> // UART registers + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + cyg_int32 isr_vector; + cyg_uint32 rx_pin; + cyg_uint32 tx_pin; + cyg_int32 baud_rate; + cyg_int32 irq_state; +} channel_data_t; + +channel_data_t plf_ser_channels[] = { +#ifdef CYGINT_HAL_FREESCALE_UART0 + { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, + CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART1 + { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, + CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART2 + { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, + CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART3 + { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, + CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART4 + { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, + CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART5 + { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, + CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } +#endif +}; + +#if defined(CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION) && \ + CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION +# define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR \ + CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +#else +# define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +#endif + +//----------------------------------------------------------------------------- + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_putc(void *__ch_data, char c); + + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = chan->base; + + // Configure PORT pins + hal_set_pin_function(chan->rx_pin); + hal_set_pin_function(chan->tx_pin); + + // 8-1-no parity. + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0); + CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate); + // Enable RX and TX + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, + (CYGHWR_DEV_FREESCALE_UART_C2_TE | + CYGHWR_DEV_FREESCALE_UART_C2_RE)); +} + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_putc(void* __ch_data, char ch_out) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint32 uart_s1; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)); + + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + cyg_uint8 ch_in; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF)) + return false; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + *p_ch_in = ch_in; + + return true; +} + +cyg_uint8 CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in) +{ + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // delay in .1 ms steps + delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10; + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base; + cyg_uint8 ser_port_reg; + int ret = 0; + va_list ap; + + CYGARC_HAL_SAVE_GP(); + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + cyg_hal_plf_serial_init_channel(chan); + ret = 0; + break; + default: + break; + } + + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + int res = 0; + cyg_uint8 ch_in; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + if( cyg_hal_is_break( (char *) &ch_in , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + int chan_i; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channels + for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) { + cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]); + + // Setup procs in the vector table + CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); +#endif +} + +void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + cyg_hal_plf_serial_init(); +} + +#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +//============================================================================= +// Non-Virtual vector HAL diagnostics + +// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void hal_plf_diag_init(void) +{ + cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +void hal_plf_diag_putc(char c) +{ + cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 hal_plf_diag_getc(void) +{ + return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c @@ -0,0 +1,339 @@ +//========================================================================== +// +// kinetis_clocking.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2011-10-19 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#include <cyg/io/ser_freescale_uart.h> + +//=========================================================================== +// Forward declarations +//=========================================================================== + +cyg_uint32 hal_cortexm_systick_clock; +cyg_uint32 hal_kinetis_sysclk; +cyg_uint32 hal_kinetis_busclk; + +cyg_uint32 hal_get_cpu_clock(void); + +void hal_start_main_clock(void); +void hal_set_clock_dividers(void); +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC +void hal_start_rtc_clock(void); +#endif + + +//========================================================================== +// Setup up system clocks +// +// Set up clocks from configuration. In the future this should be extended so +// that clock rates can be changed at runtime. + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_clocks( void ) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT + cyghwr_hal_kinetis_port_t *port_p = CYGHWR_HAL_KINETIS_PORTA_P; +#endif +#if !defined(CYG_HAL_STARTUP_RAM) +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC + // Real Time Clock + hal_start_rtc_clock(); +# endif + // Main clock - MCG + hal_start_main_clock(); +#endif + hal_kinetis_sysclk=hal_get_cpu_clock(); + hal_kinetis_busclk=hal_kinetis_sysclk / + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS; + hal_cortexm_systick_clock=hal_kinetis_sysclk; + // Trace clock +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M; +#else + sim_p->sopt2 &= ~CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M; +#endif +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT + port_p->pcr[6] = CYGHWR_HAL_KINETIS_PORT_PCR_MUX(0x7); +#endif +} + + +#define MCG_WAIT_WHILE(_condition_) do{}while(_condition_) + +// Setup MCG +// Note: Currently only PBE mode is supported and tested. + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_main_clock(void) +{ + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; +#if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\ + defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; +#endif +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT +# if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL || \ + defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC + volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P; +# endif + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + // Set the main oscillator + *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2; +# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC + // Select exteranal oscillator + *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M | + CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + // Select RTC clock source for MCG reference + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + +#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + // Enter FBE mode + mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE( + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE) +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + | CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + ; + mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV( + CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG) +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + |CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF) +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL + ; + +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + // Wait for oscillator start up + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M)); +# endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + // Wait for reference clock to switch to external reference + MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M); + // Wait for status flags update + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ +defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT +# else + CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL +# endif + ); +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + // Set peripheral dividers before switching to high frequency. + hal_set_clock_dividers(); +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL + // Configure FLL + mcg_p->c4 = (mcg_p->c4 & 0x1f) | + (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 | + CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS( + CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS)); + +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL + // Configure PLL and enter PBE mode + mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) | + CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M; + mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24); + + // Switch to PBE mode + mcg_p->c6 |= CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M; + + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != + CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT); + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M)); + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M)); + + // Enter PEE mode + mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M; + MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != + CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL); +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M; +# endif + +#endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) +} + +cyg_uint32 CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_get_cpu_clock(void) +{ + cyg_uint32 freq; +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; + + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) * + ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24); +#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV; +#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + freq = CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC; +#else // ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_none +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_end + + return freq; +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_set_clock_dividers(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + + sim_p->clk_div1 = CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(0) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS-1) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS-1) | + CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4( + CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH-1); + + sim_p->clk_div2 = CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV( + CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV-1) | + (CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC==2 ? + CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M : 0); +} + +#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_rtc_clock(void) +{ + cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P; + + rtc_p->ier=0; // Disable RTC interrupts + + //Start RTC clock if not already started + if(!(rtc_p->cr & CYGHWR_HAL_KINETIS_RTC_CR_OSCE)){ + rtc_p->cr = CYGHWR_HAL_KINETIS_RTC_CR_OSCE | + CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP; +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + { + volatile cyg_uint32 busycnt; + for(busycnt=1000000; busycnt; busycnt--) + __asm__ volatile ("nop\n"); + } +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + } +} +#endif + + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current clock settings. + + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud) +{ + cyg_uint32 sbr, brfa; + cyg_uint32 regval; + + switch(uart_p) { + case CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE: + sbr = hal_kinetis_sysclk/(16*baud); + break; + case CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE: + case CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE: + sbr = hal_kinetis_busclk/(16*baud); + break; + default: + sbr=0; + break; + } + if(sbr) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + regval &= 0xE0; + regval |= sbr >> 8; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF)); + brfa = (((32*hal_kinetis_busclk)/(16*baud))-(32*sbr)); + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + regval &= 0xE0; + regval |= brfa & 0x1f; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + } +} + +//========================================================================== +// EOF kinetis_clocking.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c @@ -0,0 +1,201 @@ +//========================================================================== +// +// kinetis_misc.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + + + +// Clock related functions are in kinetis_clocking.c +void hal_start_clocks( void ); + +#ifdef CYG_HAL_STARTUP_ROM + +//=========================================================================== +// KINETIS FLASH configuration field +//=========================================================================== + +// Note: KINETIS FLASH configuration field must be present in Kinetis flash +// image and ocupy addresses 0x00000400 to 0x0000040f. + +// For ".flash_conf" section definition see MLT files. + +const cyghwr_hal_kinetis_flash_conf_t CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD +__attribute__((section(".flash_conf"), used)) = { + .backdoor_key = CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY, + .fprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT, + .fsec = CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC, + .fopt = CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT, + .feprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT, + .fdprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT +}; + +const cyghwr_hal_kinetis_flash_conf_t * +CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_flash_conf_p( void ) +{ + return &CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD; +} + +#endif // CYG_HAL_STARTUP_ROM + +//=== KINETIS FLASH security configuration END. ============================ + + +//========================================================================== +// Setup variant specific hardware +//========================================================================= + + +void hal_variant_init( void ) +{ + hal_start_clocks(); + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +} + + +//=========================================================================== +// The WDOG at Freescale Kinetis is enabled after reset. hal_wdog_disable +// provides functionality for disabling it at startup. +//=========================================================================== + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_wdog_unlock_simple(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p) +{ + wdog_p->Unlock = 0xC520; + wdog_p->Unlock = 0xD928; +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_kinetis_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p) +{ + CYGARC_CPSID( i ); + hal_kinetis_wdog_unlock_simple(wdog_p); + CYGARC_CPSIE( i ); +} + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_wdog_disable(void) +{ + volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p = CYGHWR_HAL_KINETIS_WDOG_P; + hal_kinetis_wdog_unlock_simple(wdog_p); + wdog_p->StCtrlH = CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M; +} + +//========================================================================== +// Pin configuration functions +// + +static cyghwr_hal_kinetis_port_t * const Ports[] = { + CYGHWR_HAL_KINETIS_PORTA_P, CYGHWR_HAL_KINETIS_PORTB_P, + CYGHWR_HAL_KINETIS_PORTC_P, CYGHWR_HAL_KINETIS_PORTD_P, + CYGHWR_HAL_KINETIS_PORTE_P +}; + +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_set_pin_function(cyg_uint32 pin) +{ + cyghwr_hal_kinetis_port_t *port_p; + + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)]; + port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)] = + CYGHWR_HAL_KINETIS_PIN_FUNC(pin); + } +} + +void +hal_dump_pin_function(cyg_uint32 pin) +{ + cyghwr_hal_kinetis_port_t *port_p; + + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)]; + diag_printf("Port %d: %p[%d] fun=%x\n", + CYGHWR_HAL_KINETIS_PIN_PORT(pin), + port_p, + CYGHWR_HAL_KINETIS_PIN_BIT(pin), + port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)]); + } +} + +void +hal_dump_pin_setting(cyg_uint32 pin) +{ + if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) { + diag_printf("Pin: 0x%08x Port=%d bit=%d fun=%x\n", + pin, + CYGHWR_HAL_KINETIS_PIN_PORT(pin), + CYGHWR_HAL_KINETIS_PIN_BIT(pin), + CYGHWR_HAL_KINETIS_PIN_FUNC(pin)); + } +} + + +//========================================================================== +// EOF kinetis_misc.c