Mercurial > ecos
changeset 2650:2bff610f66e7
Contribute eCosCentric's MCFxxxx variant HAL, replacing the old
code.
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--- a/packages/hal/m68k/mcf52xx/var/current/ChangeLog +++ b/packages/hal/m68k/mcf52xx/var/current/ChangeLog @@ -1,13 +1,162 @@ -2004-04-22 Jani Monoses <jani@iv.ro> +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl, doc/mcf52xx.sgml, include/hal_diag.h, + include/var_arch.h, include/var_cache.h, include/var_intr.h, + include/var_io.h, src/hal_diag.c, src/mcf52xx_asm.S: minor + clean-ups. + +2008-09-01 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h (HAL_MCF52xx_QSPIx_QCRn_QSPI_CS_CSn): fix typo + +2008-05-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h (HAL_MCF52xx_GPTx_PORT): fix typo. + +2008-03-18 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: add definitions for 32-bit CAN devices, PWM, + RTC, MDHA, RNG and SKHA modules which are now common to many + ColdFire processors. + +2008-02-28 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl, src/mcf52xx.c, src/mcf52xx_asm.S: add + variant-level support for a profiling timer using an + mcf5282-compatible PIT. + +2008-02-14 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h, include/var_intr.h: add support for interrupt + controllers with set/clear mask registers. + +2007-03-21 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h (HAL_INTERRUPT_SET_LEVEL): Two-controller + version of this macro was same as single controller version. Fixed + to deal with two controllers. + +2007-02-04 Bart Veer <bartv@ecoscentric.com> + + * src/hal_diag.c (hal_mcf52xx_diag_uart_init): in configurations + where the diag init code can get called multiple times, detect + this and skip reinitializations. + +2006-12-11 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: add virtual vector support for dynamic + baud rates, for those platforms which support it. + +2006-12-03 Bart Veer <bartv@ecoscentric.com> + + * include/var_intr.h: fix support for processors with two + interrupt controllers. + +2006-10-02 John Dallaway <jld@ecoscentric.com> + + * doc/mcf52xx.sgml: Fix minor typographical errors. + +2006-09-25 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: Bring up to date following recent changes in + M68K HALs. + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: fix ethernet and uart definitions. Add + QSPI_CS_CSn(). + + * include/var_arch.h: fix typo + + * src/hal_diag.c, include/hal_diag.h, cdl/hal_m68k_mcf52xx.cdl: + Sort out interaction with virtual vectors. - * cdl/hal_m68k_mcf52xx.cdl : - Invoke tail with stricter syntax that works in latest coreutils. +2006-09-05 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: Use HZ rather than MHZ to calculate SPI baud + rates. + + * include/var_intr.h: HAL_VSR_SET() is now optional. + + * include/var_arch.h: improved versions of the LSBIT() and MSBIT() + HAL macros. + + * src/hal_diag.c, include/hal_diag.h, cdl/hal_m68k_mcf52xx.cdl: + Generalize HAL diagnostics support. + +2006-08-22 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: provide definitions for most of the mcf5282 + on-chip devices, since these are now regularly encountered on + other ColdFires so the definitions can be shared. + + * include/var_intr.h: provide default implementations of various + interrupt/clock/reset macros for processors that have + mcf5282-compatible on-chip devices. + + * include/var.inc: provide default implementations of + hal_context_extract_isr_vector here instead of the processor HALs + + * src/hal_diag.c, include/hal_diag.h: generalize the diagnostics + support, including a bitbucket option. + +2006-03-10 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: Add reference to MCF52xx variant + documentation. + +2005-04-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: Define a HAL variant header in + <pkgconf/system.h> + +2004-03-03 Bart Veer <bartv@ecoscentric.com> + + * src/hal_diag.c (hal_mcf52xx_serial_control): Add support for + RedBoot's baudrate command, if appropriate for the platform. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: move cacr/acr/rambar/rombar definitions to the + processor HAL. These are not as generic as initially thought. + + * include/var.inc: make it easier for processors to override + savestate settings. + + * doc/mcf52xx.sgml: update to reflect MCF5282 support + +2003-08-01 Bart Veer <bartv@ecoscentric.com> + + * include/var.inc: hal_context_extract_sr is no longer needed and + has been removed. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: fix various typos etc. + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: Add documentation + +2003-07-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: + Move some UART definitions to the processor HAL because they are + not available on all MCF52xx processors + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support //=========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -31,9 +180,6 @@ 2004-04-22 Jani Monoses <jani@iv.ro> // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //===========================================================================
--- a/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl +++ b/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl @@ -1,70 +1,269 @@ # ==================================================================== # -# hal_m68k_mcf52xx.cdl +# hal_m68k_mcfxxxx.cdl # -# mcf52xx variant architectural HAL package configuration data +# mcfxxxx variant architectural HAL package configuration data # # ==================================================================== #####ECOSGPLCOPYRIGHTBEGIN#### -## ------------------------------------------- -## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## -## eCos is free software; you can redistribute it and/or modify it under -## the terms of the GNU General Public License as published by the Free -## Software Foundation; either version 2 or (at your option) any later version. -## -## eCos is distributed in the hope that it will be useful, but WITHOUT ANY -## WARRANTY; without even the implied warranty of MERCHANTABILITY or -## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -## for more details. -## -## You should have received a copy of the GNU General Public License along -## with eCos; if not, write to the Free Software Foundation, Inc., -## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -## -## As a special exception, if other files instantiate templates or use macros -## or inline functions from this file, or you compile this file and link it -## with other works to produce a work based on this file, this file does not -## by itself cause the resulting work to be covered by the GNU General Public -## License. However the source code for this file must still be made available -## in accordance with section (3) of the GNU General Public License. -## -## This exception does not invalidate any other reasons why a work based on -## this file might be covered by the GNU General Public License. -## -## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -## at http://sources.redhat.com/ecos/ecos-license/ -## ------------------------------------------- +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003,2005,2006,2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with eCos; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +# +# As a special exception, if other files instantiate templates or use macros +# or inline functions from this file, or you compile this file and link it +# with other works to produce a work based on this file, this file does not +# by itself cause the resulting work to be covered by the GNU General Public +# License. However the source code for this file must still be made available +# in accordance with section (3) of the GNU General Public License. +# +# This exception does not invalidate any other reasons why a work based on +# this file might be covered by the GNU General Public License. +# ------------------------------------------- #####ECOSGPLCOPYRIGHTEND#### # ==================================================================== +#####DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== -cdl_package CYGPKG_HAL_M68K_MCF52xx { - display "68k/Coldfire version 2 core HAL" +cdl_package CYGPKG_HAL_M68K_MCFxxxx { + display "M68k/ColdFire variant HAL" + doc ref/hal-m68k-mcfxxxx.html parent CYGPKG_HAL_M68K requires CYGPKG_HAL_M68K hardware - include_dir cyg/hal - define_header hal_m68k_mcf52xx.h + include_dir cyg/hal + compile mcf52xx.c mcf52xx_asm.S + + description "The M68k/ColdFire variant HAL package provides + generic support for the Freescale ColdFire family of + processors." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_m68k_mcfxxxx.h>" + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_DIAGNOSTICS { + display "HAL diagnostics support" + flavor none + description " + The MCFxxxx variant HAL has support for outputting diagnostics via an + on-chip UART compatible with the ones found on the MCF5282, or for + discarding all diagnostic output. In some development environments the + diagnostics channel can also be used for communication between gdb + on the host and the gdb stubs on the target. In virtual vector + configurations where the application runs on top of RedBoot the + diagnostics channel is provided by RedBoot so changing the channel + requires reconfiguring RedBoot." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT { + display "Platform uses default MCFxxxx diagnostics support" + flavor bool + description " + The MCFxxxx variant HAL has support for outputting diagnostics via + an on-chip UART compatible with the ones found on the MCF5282. + If a platform can use this default diagnostics support then the + platform HAL will implement this interface. If some other mechanism + should be used for generating diagnostics output, for example because + none of the UARTs are available, then the platform HAL can provide its + own facilities." + + define_proc { + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS\t1" + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL\t0" + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL\t0" + } + } - description "The 68k/Coldfire version 2 core HAL package provides - generic support for the version 2 Coldfire core. It is also - necessary to select a specific target platform HAL package." + cdl_option CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT { + display "Port to use for HAL diagnostics" + flavor data + compile hal_diag.c + active_if !CYGSEM_HAL_USE_ROM_MONITOR || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS + active_if CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT + legal_values { + (CYGHWR_HAL_M68K_MCFxxxx_UART0 ? "uart0" : "") + (CYGHWR_HAL_M68K_MCFxxxx_UART1 ? "uart1" : "") + (CYGHWR_HAL_M68K_MCFxxxx_UART2 ? "uart2" : "") + "<invalid>" + } + requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "<invalid>" } + default_value { + CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_DEFAULT ? CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_DEFAULT : + CYGHWR_HAL_M68K_MCFxxxx_UART0 ? "uart0" : + CYGHWR_HAL_M68K_MCFxxxx_UART1 ? "uart1" : + CYGHWR_HAL_M68K_MCFxxxx_UART2 ? "uart2" : + "discard" + } + + description " + This option controls which of the on-chip UARTs will be used for + the HAL diagnostics channel. A UART connected to an RS232 transceiver + is required." + } - define_proc { - puts $::cdl_header "#include <pkgconf/hal_m68k.h>" + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD { + display "Baud rate to use for HAL diagnostics" + flavor data + active_if CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT + legal_values { 9600 19200 38400 115200 } + default_value { is_enabled(CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD) ? + CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD : 38400 + } + # For platforms which implement dynamic baud rates + define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option selects the baud rate used for the diagnostics port." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI { + display "Interrupt priority for HAL diagnostics UART" + flavor data + active_if CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT + active_if CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + legal_values CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX + default_value { is_loaded(CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_DIAG) ? + CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_DIAG : CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX } + description " + When the HAL diagnostics channel is used for gdb traffic it may + at times be in interrupt-driven rather than polled mode, to allow + a ctrl-C to halt the application. This configuration option + selects the interrupt priority." + } } - compile var_startup.c var_misc.c var_arch.S - - make { - <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S - $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< - @echo $@ ": \\" > $(notdir $@).deps - @tail -n +2 vectors.tmp >> $(notdir $@).deps - @echo >> $(notdir $@).deps - @rm vectors.tmp + + # This component will be filled in by the processor/platform HAL's. + cdl_component CYGPKG_HAL_M68K_MCFxxxx_REGISTERS { + display "Hardware configuration" + flavor none + no_define + description " + ColdFire processors usually have a number of on-chip memories: an + instruction cache, some RAM, and possibly some ROM. Some aspects of + these can be configured by selecting the values for certain key + registers, for example the RAMBAR internal ram base register." } + if { 0 } { + cdl_component CYGPKG_HAL_M68K_MCFxxxx_MAC { + display "Support for the MAC unit" + active_if CYGINT_HAL_M68K_MCFxxxx_HARDWARE_MAC + flavor none + description " + If the target processor has a hardware multiply/accumulate unit then + this component defines additional configuration options related + to that unit." + + cdl_option CYGIMP_HAL_M68K_MCFxxxx_MAC_SAVE { + display "Save MAC state during context switch" + default_value 1 + description " + By default the MAC context gets saved during a context switch and + whenever an interrupt occurs. This can be suppressed if the application + does not actually use this unit, or if it does so from only one + thread." + } + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_EMAC { + display "Support for the enhanced MAC unit" + active_if CYGINT_HAL_M68K_MCFxxxx_HARDWARE_EMAC + flavor none + description " + If the target processor has an enhanced multiply/accumulate unit then + this component defines additional configuration options related + to that unit." + + cdl_option CYGIMP_HAL_M68K_MCFxxxx_EMAC_SAVE { + display "Save EMAC state during context switch" + default_value 1 + description " + By default the EMAC context gets saved during a context switch and + whenever an interrupt occurs. This can be suppressed if the application + does not actually use this unit, or if it does so from only one + thread." + } + } + } + + cdl_component CYGHWR_HAL_M68K_MCFxxxx_HARDWARE { + display "Optional hardware units" + flavor none + no_define + description " + Some ColdFire hardware units such as the multiply/accumulator are + optional. This component keeps track of which units are actually + available on the current target so that other configuration options + and the eCos source code can adapt accordingly." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_HARDWARE_MAC { + display "Multiply/accumulate unit" + flavor bool + description " + This interface will be implemented if the specific processor being + used has a MAC (multiply/accumulate) unit." + } + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_HARDWARE_EMAC { + display "Enhanced multiply/accumulate unit" + flavor bool + description " + This interface will be implemented if the specific processor being + used has an EMAC (enhanced multiply/accumulate) unit." + } + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_SOFTWARE { + display "Optional software units" + flavor none + no_define + description " + The MCFxxxx variant HAL can provide default implementations of some + software units such as profiling timer support for ColdFire processors + sharing appropriate characteristics." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER { + display "Use standard profile timer" + active_if CYGPKG_PROFILE_GPROF + implements CYGINT_PROFILE_HAL_TIMER + flavor bool + + description " + The MCFxxxx variant HAL can provide gprof profiling timer support + on all ColdFire processors with a spare MCF5282-compatible PIT timer." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER_ISR_PRIORITY { + display "Profile timer interrupt priority" + active_if CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER + flavor data + legal_values CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX + default_value { is_loaded(CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_PROFILING_TIMER) ? + CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_PROFILING_TIMER : CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN } + description " + This configuration option controls the priority used for the + profiling timer interrupts. Typically this should be a high + priority, making it possible to get profiling info for lower + priority interrupt handlers when nested interrupt handling + is enabled." + } + } } -
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/doc/mcf52xx.sgml @@ -0,0 +1,483 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- mcfxxxx.sgml --> +<!-- --> +<!-- mcfxxxx variant HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####COPYRIGHTBEGIN#### --> +<!-- --> +<!-- Copyright (C) 2003,2004,2006,2008 --> +<!-- Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- --> +<!-- ####COPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-mcfxxxx"><title>Freescale MCFxxxx Variant Support</title> + +<refentry id="m68k-mcfxxxx"> + <refmeta> + <refentrytitle>MCFxxxx ColdFire Processors</refentrytitle> + </refmeta> + <refnamediv> + <refname><varname>CYGPKG_HAL_M68K_MCFxxxx</varname></refname> + <refpurpose>eCos Support for Freescale MCFxxxx Processors</refpurpose> + </refnamediv> + + <refsect1 id="m68k-mcfxxxx-description"><title>Description</title> + <para> +The Freescale ColdFire family is a range of processors including the +MCF5206 and the MCF5282. From a programmer's perspective these +processors all share basically the same processor core, albeit with +minor differences in the instruction set. They differ in areas like +performance, on-chip peripherals and caches. Even when it comes to +peripherals there is a lot of commonality. For example many but not +all Coldfire processors use the same basic interrupt controller(s) as +the MCF5282. Similarly the on-chip UARTs tend to use the same basic +design although there are variations in the number of UARTs, the fifo +sizes, and in certain details. + </para> + <para> + The MCFxxxx variant HAL package +<varname>CYGPKG_HAL_M68K_MCFxxxx</varname> provides support for +various features that are common to many but not all Coldfire +processors. This includes HAL diagnostics via an on-chip UART and +interrupt controller management for those processors which have +MCF5282-compatible controllers. The variant HAL complements the M68K +architectural HAL package. An eCos configuration should also include a +processor-specific HAL package such as +<varname>CYGPKG_HAL_M68K_MCF5272</varname> to support the +chip-specific peripherals and cache details, and a platform HAL +package such as <varname>CYGPKG_HAL_M68K_M5272C3</varname> to support +board-level details like external memory chips. The processor or +platform HAL can override the functionality provided by the variant +HAL. + </para> + </refsect1> + + <refsect1 id="m68k-mcfxxxx-config"><title>Configuration</title> + <para> +The MCFxxxx variant HAL package should be loaded automatically when +eCos is configured for appropriate target hardware. It should never be +necessary to load this package explicitly. Unloading the package +should only happen as a side effect of switching target hardware. + </para> + <para> +On most ColdFire platforms the variant HAL will provide the HAL +diagnostics support via one of the UARTs. Some platforms may provide +their own HAL diagnostics facility, for example output via an LCD. The +variant HAL diagnostics support is active if the processor or platform +implements the +<varname>CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT</varname> +interface. It is also active only in configurations which do not rely +on an underlying rom monitor such as RedBoot: +if <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> is enabled then the +default diagnostics channel will automatically be inherited from +RedBoot. The variant HAL then provides a number of configuration +options related to diagnostics: + </para> + <variablelist> + <varlistentry> + <term><varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname></term> + <listitem><para> +This selects the destination for HAL diagnostics. The number of UARTs +available depends on the processor, and on any given board some of the +UARTs may not be connected. Hence the variant HAL looks for +configuration options +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname>, +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART1</varname> and +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART2</varname> to see which on-chip +UARTs are actually available on the processor and target hardware, and +uses this information to let the user select a UART. + </para> + <para> +When a UART is in use as the HAL diagnostics channel, that UART +should not be used for any other purpose. In particular application +code should avoid using it for I/O via the serial driver. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname></term> + <listitem><para> +When a UART is selected for HAL diagnostics this option specifies the +default baud rate. The most common setting is 38400. That provides a +compromise between performance and reliability, especially in +electrically noisy environments such as an industrial environment or a +test farm. Some platforms may define +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD</varname> +to handle scenarios where another default baud rate is preferable, +typically for compatibility with existing software. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI</varname></term> + <listitem><para> +Usually the HAL diagnostics channel is driven in polled mode but in +some scenarios interrupts are required. For example, when debugging an +application over a serial line on top of the gdb stubs provided by +RedBoot, the user should be able to interrupt the application with a +control-C. The application will not be polling the HAL diagnostics +UART at this point so instead the eCos interrupt management code +interacts with the gdb stubs to do the right thing. This configuration +option selects the interrupt priority. It should be noted that on some +processors with MCF5282-compatible interrupt controllers all +priorities for enabled interrupts should be unique, and it is the +responsibility of application developers to ensure this condition is +satisfied. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="m68k-mcfxxxx-port"><title>The HAL Port</title> + <para> +This section describes how the MCFxxxx variant HAL package implements +parts of the eCos HAL specification. It should be read in conjunction +with similar sections from the architectural and processor HAL +documentation. + </para> + + <refsect2 id="m68k-mcfxxxx-port-io"><title>HAL I/O</title> + <para> +The <filename class="headerfile">cyg/hal/var_io.h</filename> header +provides various definitions for on-chip peripherals, where the +current processor has peripherals compatible with the MCF5282's. +This header is automatically included by the architectural +<filename class="headerfile">cyg/hal/hal_io.h</filename> so other +packages and application code will usually only include the latter. + </para> + <para> +It is up to the processor HAL to specify exactly what <filename +class="headerfile">var_io.h</filename> should export. For example the +MCF5213's <filename class="headerfile">proc_io.h</filename> header +contains the following: + </para> + <programlisting width=72> +# define HAL_MCFxxxx_HAS_MCF5282_INTC 1 +# define HAL_MCFxxxx_INTC0_BASE (HAL_MCF521x_IPSBAR + 0x00000C00) + </programlisting> + <para> +This enables support within the variant HAL for a single +MCF5282-compatible interrupt controller, and cases <filename +class="headerfile">var_io.h</filename> to export symbols such as: + </para> + <programlisting width=72> +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC +// Two 32-bit interrupt mask registers +# define HAL_MCFxxxx_INTCx_IMRH 0x0008 +# define HAL_MCFxxxx_INTCx_IMRL 0x000C +… +# define HAL_MCFxxxx_INTCx_ICRxx_IL_MASK (0x07 << 3) +# define HAL_MCFxxxx_INTCx_ICRxx_IL_SHIFT 3 + </programlisting> + <para> +Symbols such as <varname>HAL_MCFxxxx_INTCx_IMRH</varname> can be used +to access the relevant hardware registers via +<function>HAL_READ_UINT32</function> and +<function>HAL_WRITE_UINT32</function>. Symbols like +<varname>HAL_MCFxxxx_INTCx_ICRxx_IL_MASK</varname> can be used to +generate or decode the contents of the hardware registers. + </para> + <para> +The header file does mostly use a naming convention, but is not +guaranteed to be totally consistent. There may also be discrepancies +with the documentation because the manuals for the various Coldfire +processors are not always consistent about their naming schemes. +All I/O definitions provided by the variant HAL will start with +<literal>HAL_MCFxxxx_</literal>, followed by the name of the +peripheral. If a peripheral is likely to be a singleton, for example +an on-chip flash unit, then the name is unadorned. If there may be +several instances of the peripheral then the name will be followed by +a lower case x. For example: + </para> + <programlisting width=72> +# define HAL_MCFxxxx_CFM_CR 0x0000 +… +# define HAL_MCFxxxx_UARTx_UMR 0x00 + </programlisting> + <para> +Register names will be relative to some base address such as +<varname>HAL_MCFxxxx_CFM_BASE</varname> or +<varname>HAL_MCFxxxx_UART0_BASE</varname>, so code accessing a +register would look like: + </para> + <programlisting width=72> + HAL_READ_UINT32(HAL_MCFxxxx_CFM_BASE + HAL_MCFxxxx_CFM_PROT, reg); + … + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UTB, '*'); + </programlisting> + <para> +Usually the register names are singletons, but in some cases such as +the interrupt controller priority registers there may be multiple +instances of the register and the names will be suffixed +appropriately. For example +<varname>HAL_MCFxxxx_INTCx_ICRxx_IL_MASK</varname> indicates the field +<literal>IL</literal> within one of the <literal>ICR</literal> +registers within one of the interrupt controllers. + </para> + <para> +As mentioned earlier the processor HAL's <filename +class="headerfile">proc_io.h</filename> will control which definitions +are exported by <filename class="headerfile">var_io.h</filename>. +Sometimes the processor HAL will then go on to undefine or redefine +some of the symbols, to reflect incompatibilities between the +processor's devices and the equivalent devices on the MCF5282. There +may also be additional symbols for the devices, and there will be +additional definitions for any processor-specific hardware. In +particular GPIO pin handling is handled by the processor HAL, not by +the variant HAL. Application developers should examine <filename +class="headerfile">proc_io.h</filename> as well as +<filename class="headerfile">var_io.h</filename> and the +processor-specific documentation to see exactly what I/O definitions +are provided. When porting to a new Coldfire processor it is best to +start with an existing processor HAL and copy +code as appropriate. A search for <literal>_HAS_</literal> in +<filename class="headerfile">var_io.h</filename> will also be +informative. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-context"><title>Thread Contexts and Setjmp/Longjmp</title> + <para> +All MCFxxxx processors support interrupts and exceptions in a uniform +way. When an interrupt or exception occurs the hardware pushes the +current program counter, the status register, and an additional 16-bit +word containing information about the interrupt source, for a total of +64 bits. Hence the PCSR part of a thread context consists of two +32-bit integers, and the variant HAL provides appropriate C and +assembler macros to examine and manipulate these. + </para> + <para> +Not all MCFxxxx processors have hardware floating point, so support +for this is left to the processor HAL package. Some MCFxxxx processors +have additional hardware units such as a multiply-accumulator, but +these are not currently supported by eCos. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-diag"><title>HAL Diagnostics</title> + <para> +The various MCFxxxx processors usually have one or more UARTs based on +very similar hardware. The variant HAL package can provide HAL +diagnostic support using such a UART. There are some minor differences +such as fifo sizes, and the UARTs will be accessed at different memory +locations. These differences are handled by a small number of macros +provided by the processor and platform HAL. + </para> + <para> +The MCFxxxx variant HAL only provides HAL diagnostic support via a +UART if the processor or platform HAL does not provide an alternative +implementation. That copes with situations where the on-chip UARTs are +not actually accessible on the target board and an alternative +communication channel must be used. + </para> + <para> +If the variant HAL should implement HAL diagnostics then the processor +or platform HAL should implement the CDL interface +<varname>CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT</varname>. It +should also define one or more of +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname>, +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART1</varname> and +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART2</varname>, and ensure that any +multi-purpose GPIO pins are set correctly. The variant HAL will take +care of the rest. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-cache"><title>Cache Handling</title> + <para> +The various MCFxxxx processors all have very different caches, so +support for these is deferred to the processor HAL. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-exceptions"><title>Exceptions</title> + <para> +All MCFxxxx processors support synchronous exceptions in a uniform +way, with the hardware pushing sufficient information on to the stack +to identify the nature of the exception. This means that the architectural +entry point <function>hal_m68k_exception_vsr</function> can be used as +the default VSR for all exceptions, with no need for separate +trampoline functions. + </para> + <para> +The variant HAL does not provide any special support for recovering +from exceptions. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-interrupts"><title>Interrupts</title> + <para> +All MCFxxxx processors supports interrupts in a uniform way. When an +interrupt occurs the hardware pushes sufficient information on to the +stack to identify the interrupt. Therefore the architectural entry +point <function>hal_m68k_interrupt_vsr</function> can be used as the +default VSR for all interrupts, with the variant just supplying a +small number of macros that allow the generic code to extract details of +the interrupt source. There is no need for separate trampoline +functions for every interrupt source. + </para> + <para> +On processors which have MCF5282-compatible interrupt and edge port +modules the variant HAL can provide the +<function>HAL_INTERRUPT_MASK</function>, +<function>HAL_INTERRUPT_UNMASK</function>, +<function>HAL_INTERRUPT_SET_LEVEL</function>, +<function>HAL_INTERRUPT_ACKNOWLEDGE</function> and +<function>HAL_INTERRUPT_CONFIGURE</function> macros. There is support +for processors with a single interrupt controller or with two separate +interrupt controllers. Otherwise these macros are left to the +processor HAL. The allocation of interrupt vectors to the various +on-chip devices is also a characteristic of the processor HAL. +<filename class="headerfile">proc_intr.h</filename> should be +consulted for appropriate definitions, for example +<varname>CYGNUM_HAL_ISR_UART0</varname>. + </para> + <para> +The mask and umask operations are straightforward: if the interrupt +controller has the <literal>SIMR</literal> and <literal>CIMR</literal> +registers those will be used; otherwise the <literal>IRM</literal> +registers will be updated by a read-modify-write cycle. The +acknowledge macro is only relevant for external interrupts coming in +via the edge port module and will clear the interrupt by writing to +the <literal>EPIER</literal> register. There is no simple way to clear +interrupts generated by the on-chip peripherals, so that is the +responsibility of the various device drivers or of application code. +The configure macro is only relevant for external interrupts and +involves manipulating the edge port module. + </para> + <para> +The <function>HAL_INTERRUPT_SET_LEVEL</function> macro is used +implicitly by higher level code such as +<function>cyg_interrupt_create</function>. With MCF5282-compatible +interrupt controllers the priority level corresponds to +the <literal>ICRxx</literal> register. The exact format depends on the +processor. Interrupt priorities corresponding to IPL level 7 are +non-maskable. Such interrupts cannot be managed safely by the usual +eCos ISR and DSR mechanisms. Instead application code will have to +install a custom VSR and manage the entire interrupt. + </para> + <para> +Some MCF5282-compatible interrupt controllers have a major +restriction: all interrupt priorities within each controller must be +unique. If two interrupts go off at the same time and have exactly the +same priority then the controllers' behaviour is undefined. In a +typical application some of the interrupts will be handled by eCos +device drivers while others will be handled directly by application +code. Since eCos cannot know which interrupts may get used, it cannot +allocate unique priorities. Instead this has to be left to the +application developer. eCos does provide configuration options such as +<varname>CYGNUM_KERNEL_COUNTERS_CLOCK_ISR_PRIORITY</varname> and +<varname>CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_ISR_PRIORITY</varname> to +provide control over the eCos-managed interrupts, and provides default +values for these which are unique. + </para> + <caution><para> +Non-unique interrupt priorities can lead to very confusing system +behaviour. For example on an MCF5282, if the PIT3 system clock +(interrupt 0x3a) and ethernet RX frame (interrupt 0x1b) are +accidentally given the same priority and go off at the same time, the +interrupt controller may actually issue an interrupt 0x3b, the bitwise +or of the two interrupt numbers. That interrupt belongs to the on-chip +flash module. There may not be an installed handler for that interrupt +at all, and even if there is a handler it will only manipulate the +flash hardware and not clear the system clock and ethernet interrupts. +Hence the system is likely to go into a spin, continually trying to +service the wrong interrupt. To track down such problems during +debugging it may prove useful to install a breakpoint on the +<function>hal_arch_default_isr</function> function. + </para></caution> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-clock"><title>Clock Support</title> + <para> +On processors with an MCF5282-compatible programmable interrupt timer +module or PIT, the variant HAL can provide the +<function>HAL_CLOCK_INITIALIZE</function>, +<function>HAL_CLOCK_RESET</function>, +<function>HAL_CLOCK_READ</function> and +<function>HAL_CLOCK_LATENCY</function> macros. These macros are used +by the eCos kernel to implement the system clock and may be used for +other purposes in non-kernel configurations. When multiple timers are +available it is up to the processor or platform HAL to select which +one gets used for the system clock. It is also up to the processor or +platform HAL to provide various clock-related configuration options +such as <varname>CYGNUM_HAL_RTC_PERIOD</varname>. Those options need +to take into account the processor clock speed, which is usually a +characteristic of the platform and hence not known to the variant HAL. + </para> + <para> +When porting to a new Coldfire processor, the processor or platform +HAL should define the symbols +<varname>CYGNUM_HAL_INTERRUPT_RTC</varname>, +<varname>_HAL_MCFxxxx_CLOCK_PIT_BASE_</varname>, and +<varname>_HAL_MCFxxxx_CLOCK_PIT_PRE_</varname>. Existing ports can be +examined for more details. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-reset"><title>Reset</title> + <para> +On processors with an MCF5282-compatible reset module or RST, the +variant HAL can provide the <function>HAL_PLATFORM_RESET</function> +macro. That macro is typically used by the gdb stubs support inside +RedBoot to reset the hardware between debug sessions, ensuring that +each session runs in as close to pristine hardware as possible. The +macro uses the <literal>SOFTRST</literal> bit of the +<varname>RCR</varname> register. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-bitindex"><title>Bit Indexing</title> + <para> +By default the variant HAL will provide versions of +<function>HAL_LSBIT_INDEX</function> and +<function>HAL_MSBIT_INDEX</function> which are more efficient than the +default ones in the architectural HAL. The implementation uses the +<command>ff1.l</command> and <command>bitrev.l</command> instructions. +If the Coldfire processor does not support these instructions then +the processor HAL should define +<varname>_HAL_M68K_MCFxxxx_NO_FF1_</varname>. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-other-hal"><title>Other Issues</title> + <para> +The MCFxxxx variant HAL does not affect the implementation of data +types, stack size definitions, idle thread processing, linker scripts, +SMP support, system startup, or debug support. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-other"><title>Other Functionality</title> + <para> +The MCFxxxx variant HAL only implements functionality defined in the +eCos HAL specification and does not export any additional functions. + </para> + </refsect2> + </refsect1> +</refentry> + +</part>
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/hal_diag.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// MCFxxxx HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +// On most ColdFire platforms the mcfxxxx variant HAL provides the HAL +// diagnostics support via a UART. The +// CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT interface +// enables this. +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) && !defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS) +# include <cyg/hal/hal_if.h> +# define HAL_DIAG_INIT() hal_if_diag_init() +# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +# define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#elif !defined(CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT) +// Allow the platform HAL to provide the diagnostics channel. +# include <cyg/hal/plf_diag.h> +#else + +externC void hal_mcfxxxx_diag_uart_init(cyg_uint8*, cyg_uint32); +externC void hal_mcfxxxx_diag_uart_putc(void*, char c); +externC cyg_uint8 hal_mcfxxxx_diag_uart_getc(void*); + +# if defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart0) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART0_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART0 +# elif defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart1) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART1_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART1 +# elif defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart2) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART2_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART2 +# else +# error Diagnostics channel UART base not defined. +# endif + +// Even if the standard diagnostics facilities are enabled, allow the +// platform HAL to override things. +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() \ + CYG_MACRO_START \ + hal_mcfxxxx_diag_uart_init((cyg_uint8*) (_HAL_MCFxxxx_DIAG_UART_BASE_), \ + CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD); \ + CYG_MACRO_END +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(_c_) \ + CYG_MACRO_START \ + hal_mcfxxxx_diag_uart_putc((void*)_HAL_MCFxxxx_DIAG_UART_BASE_, _c_); \ + CYG_MACRO_END +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(_c_) \ + CYG_MACRO_START \ + (_c_) = hal_mcfxxxx_diag_uart_getc((void*)(_HAL_MCFxxxx_DIAG_UART_BASE_)); \ + CYG_MACRO_END +# endif + +#endif // VV/MCFxxxx_DIAGNOSTICS + +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var.inc @@ -0,0 +1,114 @@ +##============================================================================= +## +## var.inc +## +## mcfxxxx variant assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +// ---------------------------------------------------------------------------- +// Generic support for the MAC and eMAC units. +// Not yet implemented. + +// ---------------------------------------------------------------------------- +// Now include the cpu-specific header, which can define context macros +// including the MAC, eMAC, and possibly other state +#include <cyg/hal/proc.inc> + +// ---------------------------------------------------------------------------- +// Thread context support. Usually this is generic for all ColdFires, +// but it is possible for processor or platform code to override +// these definitions. + +// The 68K exception and interrupt VSR's can be used directly since the +// vector number is part of the hardware state automatically pushed onto +// the stack. Since there are no trampolines there is no need to adjust +// the stack before returning. +#ifndef HAL_CONTEXT_PCSR_RTE_ADJUST +# define HAL_CONTEXT_PCSR_RTE_ADJUST 0 +#endif + +#ifndef HAL_CONTEXT_PCSR_SAVE_SR_DEFINED + .macro hal_context_pcsr_save_sr reg=%sp,off=0,scratch=%d0 + mov.l #0x40000000, \scratch + mov.w %sr, \scratch + mov.l \scratch, (hal_context_pcsr_offset+\off)(\reg) + .endm +#endif + +// Get the ISR vector out of the context. This is encoded in one +// byte in the exception frame. There are two versions depending +// on the number of ISR vectors. If < 64, i.e. if an interrupt +// falls in the range 64 <= isrvec < 128, then a simple mask +// will do the trick. If > 164, i.e. if an interrupt falls in +// the range 64 <= isrvec < 256, then a subtract is required. + +#ifndef HAL_CONTEXT_EXTRACT_ISR_DEFINED + +# if HAL_M68K_VSR_COUNT > 128 + + .macro hal_context_extract_isr_vector_shl2 reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x03FC, \isr + subi.l #0x0100, \isr + .endm + + .macro hal_context_extract_isr_vector reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x03FC, \isr + lsr.l #2, \isr + subi.l #0x040, \isr + .endm + +# else + .macro hal_context_extract_isr_vector_shl2 reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x00FC, \isr + .endm + + .macro hal_context_extract_isr_vector reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x0FC, \isr + lsr.l #2, \isr + .endm +# endif +#endif + +#------------------------------------------------------------------------------ +# end of var.inc
--- a/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h @@ -7,11 +7,10 @@ // Architecture variant specific abstractions // //============================================================================= -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// +// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc. // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. @@ -34,183 +33,109 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= #include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> #include <cyg/infra/cyg_type.h> - #include <cyg/hal/proc_arch.h> -// The ColdFire family of processors has a simplified exception stack -// frame that looks like the following: -// -// 3322222222221111 111111 -// 1098765432109876 5432109876543210 -// 8 +----------------+----------------+ -// | Program Counter | -// 4 +----------------+----------------+ -// |Fmt/FS/Vector/FS| SR | -// SP --> 0 +----------------+----------------+ -// -// The stack self-aligns to a 4-byte boundary at an exception, with -// the Fmt/FS/Vector/FS field indicating the size of the adjustment -// (SP += 0,1,2,3 bytes). - -// Define the Fmt/FS/Vector/FS word. -// The first four bits are the format word which tells the -// RTI instruction how to align the stack. -#define HAL_MCF52XX_RD_SF_FORMAT_MSK ((CYG_WORD16)0xF000) -// These bits are the vector number of the exception. -#define HAL_MCF52XX_RD_SF_VECTOR_MSK ((CYG_WORD16)0x03FC) -// These are bits 3-2, and 1-0 of the fault status used -// for bus and address errors. -#define HAL_MCF52XX_RD_SF_FS32_MSK ((CYG_WORD16)0x0C00) -#define HAL_MCF52XX_RD_SF_FS10_MSK ((CYG_WORD16)0x0003) - -// Macros to access fields in the format vector word. - -#define HAL_MCF52XX_RD_SF_FORMAT(_fmt_vec_word_) \ - ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FORMAT_MSK) >> 12) - -#define HAL_MCF52XX_RD_SF_VECTOR(_fmt_vec_word_) \ - ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_VECTOR_MSK) >> 2) +// ---------------------------------------------------------------------------- +// Context support. ColdFire exceptions/interrupts are simpler than the +// 68000 variants, with a much more regular exception frame. Usually the +// hardware simply pushes two longs on to the stack. The program counter +// is at the top. Then the 16-bit status register. Then some extra +// information identifying the exception number etc. If the stack was not +// aligned when the exception occurred) (which should not happen for +// eCos code) then the hardware will do some extra stack alignment and +// store this information in a fmt field. That possibility is ignored +// for now. -#define HAL_MCF52XX_RD_SF_FS(_fmt_vec_word_) \ - (((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS32_MSK) >> 8) \ - | (((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS10_MSK)) - -/***************************************************************************** - Exception handler saved context. Some exceptions contain extra -information following this common exception handler context. -*****************************************************************************/ -typedef struct -{ - - // Data regs D0-D7 - - #define HAL_EXC_NUM_D_REGS 8 - CYG_WORD32 d[HAL_EXC_NUM_D_REGS]; - - // Address regs A0-A6 - - #define HAL_EXC_NUM_A_REGS 7 - CYG_ADDRESS a[HAL_EXC_NUM_A_REGS]; - - // Stack Pointer - - CYG_ADDRESS sp; - - // 16-bit format/vector word - - CYG_WORD16 fmt_vec_word; - - // Status Reg - - CYG_WORD16 sr; - - // Program Counter - +#define HAL_CONTEXT_PCSR \ + cyg_uint32 sr_vec; \ CYG_ADDRESS pc; -} __attribute__ ((aligned, packed)) HAL_SavedRegisters_exception; - -#ifndef HAL_GENERIC_SAVED_CONTEXT -/***************************************************************************** -HAL_GENERIC_SAVED_CONTEXT -- Generic saved context structure - - This structure could contain a normal saved context or an exception -context. +// An exception aligns the stack to a 32-bit boundary, and the fmt part +// of the exception frame encodes how much adjustment was done. The +// 0x40000000 specifies 0 bytes adjustment since the code should be +// running with stacks always aligned. +#define HAL_CONTEXT_PCSR_INIT(_regs_, _entry_, _sr_) \ + CYG_MACRO_START \ + (_regs_)->sr_vec = 0x40000000 | (cyg_uint32)(_sr_); \ + (_regs_)->pc = (CYG_ADDRESS)(_entry_); \ + CYG_MACRO_END -*****************************************************************************/ -#define HAL_GENERIC_SAVED_CONTEXT \ -typedef union \ -{ \ - HAL_SavedRegisters_normal normal; \ - HAL_SavedRegisters_exception exception; \ -} __attribute__ ((aligned, packed)) HAL_SavedRegisters; -#endif // HAL_GENERIC_SAVED_CONTEXT - -//----------------------------------------------------------------------------- -// Thread register state manipulation for GDB support. - -// Translate a stack pointer as saved by the thread context macros above into -// a pointer to a HAL_SavedRegisters structure. -#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ - (_regs_) = (HAL_SavedRegisters *)(_sp_) - -// Copy a set of registers from a HAL_SavedRegisters structure into a -// GDB ordered array. +#define HAL_CONTEXT_PCSR_GET_SR(_regs_, _sr_) \ + CYG_MACRO_START \ + _sr_ = (_regs_)->sr_vec & 0x0000FFFF; \ + CYG_MACRO_END -/* there are 180 bytes of registers on a 68020 w/68881 */ -/* many of the fpa registers are 12 byte (96 bit) registers */ -/* -#define NUMREGBYTES 180 -enum regnames {D0,D1,D2,D3,D4,D5,D6,D7, - A0,A1,A2,A3,A4,A5,A6,A7, - PS,PC, - FP0,FP1,FP2,FP3,FP4,FP5,FP6,FP7, - FPCONTROL,FPSTATUS,FPIADDR - }; -*/ +#define HAL_CONTEXT_PCSR_GET_PC(_regs_, _pc_) \ + CYG_MACRO_START \ + _pc_ = (_regs_)->pc; \ + CYG_MACRO_END -#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ - CYG_MACRO_START \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ - int _i_; \ - \ - for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \ - *_regval_++ = (_regs_)->nml_ctxt.d[_i_]; \ - \ - for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \ - *_regval_++ = (_regs_)->nml_ctxt.a[_i_]; \ - \ - *_regval_++ = (_regs_)->nml_ctxt.sp; \ - *_regval_++ = (CYG_ADDRWORD) ((_regs_)->nml_ctxt.sr); \ - *_regval_++ = (_regs_)->nml_ctxt.pc; \ - /* Undefined registers */ \ - for ( _i_ = 0; _i_ < 8; _i_++ ) \ - { \ - *((CYG_WORD16*)_regval_)++ = _i_; \ - *((CYG_WORD16*)_regval_)++ = _i_; \ - *((CYG_WORD16*)_regval_)++ = _i_; \ - } \ - *_regval_++ = 0xBADC0DE0; \ - *_regval_++ = 0xBADC0DE1; \ - *_regval_++ = 0xBADC0DE2; \ +#define HAL_CONTEXT_PCSR_SET_SR(_regs_, _sr_) \ + CYG_MACRO_START \ + (_regs_)->sr_vec = ((_regs_)->sr_vec & 0xFFFF0000) | (_sr_); \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_SET_PC(_regs_, _pc_) \ + CYG_MACRO_START \ + (_regs_)->pc = (CYG_ADDRESS)(_pc_); \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_GET_EXCEPTION(_regs_, _code_) \ + CYG_MACRO_START \ + (_code_) = (((_regs_)->sr_vec) >> 18) & 0x000000FF; \ CYG_MACRO_END -// Copy a GDB ordered array into a HAL_SavedRegisters structure. -#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ - CYG_MACRO_START \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ - int _i_; \ - \ - for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \ - (_regs_)->nml_ctxt.d[_i_] = *_regval_++; \ - \ - for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \ - (_regs_)->nml_ctxt.a[_i_] = *_regval_++; \ - \ - (_regs_)->nml_ctxt.sp = *_regval_++; \ - (_regs_)->nml_ctxt.sr = (CYG_WORD16) (*_regval_++); \ - (_regs_)->nml_ctxt.pc = *_regval_++; \ +// ---------------------------------------------------------------------------- +// LSBIT/MSBIT. Most ColdFires have ff1 and bitrev instructions which +// allow for more efficient implementations than the default ones in +// the architectural HAL. +#ifndef _HAL_M68K_MCFxxxx_NO_FF1_ +# define HAL_LSBIT_INDEX(_index_, _mask_) \ + CYG_MACRO_START \ + cyg_uint32 _tmp_ = (_mask_); \ + int _idx_; \ + if (0 == _tmp_) { \ + _idx_ = -1; \ + } else { \ + __asm__ volatile ( \ + "move.l %1, %0 ; \n" \ + "bitrev.l %0 ; \n" \ + "ff1.l %0 ; \n" \ + : "=d" (_idx_) \ + : "d" (_mask_) \ + ); \ + } \ + _index_ = _idx_; \ CYG_MACRO_END -/* ************************************************************************ */ -/* These routines write to the special purpose registers in the ColdFire */ -/* core. Since these registers are write-only in the supervisor model, no */ -/* corresponding read routines exist. */ +# define HAL_MSBIT_INDEX(_index_, _mask_) \ + CYG_MACRO_START \ + cyg_uint32 _tmp_ = (_mask_); \ + int _idx_; \ + __asm__ volatile ( \ + "move.l %1, %0 ; \n" \ + "ff1.l %0\n" \ + : "=d" (_idx_) \ + : "d" (_tmp_) \ + ); \ + _index_ = 31 - _idx_; \ + CYG_MACRO_END -externC void mcf52xx_wr_vbr(CYG_WORD32); -externC void mcf52xx_wr_cacr(CYG_WORD32); -externC void mcf52xx_wr_acr0(CYG_WORD32); -externC void mcf52xx_wr_acr1(CYG_WORD32); -externC void mcf52xx_wr_rambar(CYG_WORD32); +#endif //----------------------------------------------------------------------------- #endif // CYGONCE_HAL_VAR_ARCH_H
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/include/var_basetype.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef CYGONCE_HAL_VAR_BASETYPE_H -#define CYGONCE_HAL_VAR_BASETYPE_H - -//============================================================================= -// -// var_basetype.h -// -// Standard types for this architecture variant. -// -//============================================================================= -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//============================================================================= - -// Use defaults for this architecture. - -// TEMPORARY TO REMOVE WARNINGS! The 68k architecture compiler complains -// when the object file alignment is greater than 2. - -#ifndef CYGARC_ALIGNMENT -#define CYGARC_ALIGNMENT 2 -#endif -#ifndef CYGARC_P2ALIGNMENT -#define CYGARC_P2ALIGNMENT 1 -#endif - -//----------------------------------------------------------------------------- -#endif // CYGONCE_HAL_VAR_BASETYPE_H -
--- a/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h @@ -4,14 +4,13 @@ // // var_cache.h // -// Variant HAL cache control API +// mcfxxxx cache details // //============================================================================= -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// +// Copyright (C) 2003,2008 Free Software Foundation, Inc. // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. @@ -34,141 +33,19 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //============================================================================= - -#include <pkgconf/hal.h> -#include <cyg/infra/cyg_type.h> - -// We currently just enable the instruction cache on startup. There is -// no data cache. - -//----------------------------------------------------------------------------- -// Cache dimensions - these vary between the 8xx sub-models - -// Data cache -#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line -#define HAL_DCACHE_WAYS 1 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 0 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line -#define HAL_ICACHE_WAYS 1 // Associativity of the cache - -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Global control of data cache - -// Enable the data cache -#define HAL_DCACHE_ENABLE() - -// Disable the data cache -#define HAL_DCACHE_DISABLE() - -// Invalidate the entire cache -// Note: Any locked lines will not be invalidated. -#define HAL_DCACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() - -// Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -//#define HAL_DCACHE_WRITE_MODE( _mode_ ) - -//#define HAL_DCACHE_WRITETHRU_MODE 0 -//#define HAL_DCACHE_WRITEBACK_MODE 1 - - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. -#define HAL_DCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -#define HAL_DCACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -#define HAL_DCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Data cache line control +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -#define HAL_DCACHE_FLUSH( _base_ , _size_ ) - -// Invalidate cache lines in the given range without writing to memory. -#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - -// Write dirty cache lines to memory for the given address range. -#define HAL_DCACHE_STORE( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of reading -// from it later. -#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) - -// Allocate and zero the cache lines associated with the given range. -#define HAL_DCACHE_ZERO( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() +// Most ColdFires have caches, but the details vary widely. For now +// always leave it up to the processor HAL. +#include <cyg/hal/proc_cache.h> -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() - -// Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. -#define HAL_ICACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -#define HAL_ICACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -#define HAL_ICACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - -//----------------------------------------------------------------------------- #endif // ifndef CYGONCE_VAR_CACHE_H -// End of var_cache.h -
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/include/var_gen_types.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef _VAR_GEN_TYPES_H -#define _VAR_GEN_TYPES_H -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== - -/* - - ********************* - * * - * General Types * - * * - ********************* - - Define some simple variable sizes for the mcf52xx architecture. - -*/ - -// We use the defaults for the m68k architecture. - -#endif // _VAR_GEN_TYPES_H -
--- a/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h @@ -4,15 +4,14 @@ // // var_intr.h // -// mcf52xx Variant interrupt and clock support +// mcfxxxx Variant interrupt and clock support // // //========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// +// Copyright (C) 2003,2006,2007,2008 Free Software Foundation, Inc. // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. @@ -35,12 +34,16 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //========================================================================== +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> @@ -48,6 +51,446 @@ // Include any processor specific interrupt definitions. #include <cyg/hal/proc_intr.h> +// ColdFire defines some extra exceptions +// The debug vector is for hardware breakpoints. These are not used +// at present. +#define CYGNUM_HAL_VECTOR_DEBUG 12 +#define CYGNUM_HAL_VECTOR_FORMAT 14 + +// The following implementation should suffice for most platforms. If +// any of them need special VSR's then they can define their own version. +#if !defined(HAL_VSR_SET_TO_ECOS_HANDLER) && !defined(_HAL_M68K_NO_VSR_SET_) +# define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_) \ + CYG_MACRO_START \ + if ( (_vector_) <= CYGNUM_HAL_VECTOR_TRAPLAST) { \ + HAL_VSR_SET( (_vector_), &hal_m68k_exception_vsr, (_poldvsr_) ); \ + } else { \ + HAL_VSR_SET( (_vector_), &hal_m68k_interrupt_vsr, (_poldvsr_) ); \ + } \ + CYG_MACRO_END +#endif + +// ---------------------------------------------------------------------------- +// On ColdFires with 5282-style interrupt controllers, many of the +// interrupt-related macros can be provided here rather than duplicated +// in the processor HALs. Of course there complications, for example there +// may be one or two interrupt controllers. + +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC + +# ifndef HAL_INTERRUPT_MASK +// Masking interrupts is straightforward: there are 32-bit read-write +// mask registers. Often the vector argument will be a constant so the +// compiler gets a chance to optimise these macros. There is also some +// compile-time optimization based around the maximum number of +// interrupt vectors. to avoid worrying about interrupts 32-63 if only +// the bottom half of INTC0 is of interest, or interrupts 96-127 if +// only the bottom half of INTC1 is of interest. +// +// Some newer ColdFire registers have additional set/clear mask +// registers. + +# ifdef HAL_MCFxxxx_INTCx_SIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, (_vector_)); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (_vec_ < 64) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_); \ + } else { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_ - 64); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif +# else // ! SIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _shift_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + _shift_ -= 32; \ + } \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ |= (0x01 << _shift_); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _shift_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + } else if ((CYGNUM_HAL_ISR_MAX < 64) || (_shift_ < 64)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFx2xx_INTCx_IMRH; \ + _shift_ -= 32; \ + } else if ((CYGNUM_HAL_ISR_MAX < 96) || (_shift_ < 96)) { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + _shift_ -= 64; \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + _shift_ -= 96; \ + } \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ |= (0x01 << _shift_); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // SIMR +# endif // !defined(HAL_INTERRUPT_MASK) + +// Care has to be taken with bit 0 of the IMRL registers. Writing a 1 to +// this masks all interrupts. +# ifndef HAL_INTERRUPT_UNMASK +# ifdef HAL_MCFxxxx_INTCx_CIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, (_vector_)); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (_vec_ < 64) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_); \ + } else { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_ - 64); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif +# else +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << _vec_) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 32)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << _vec_) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else if ((CYGNUM_HAL_ISR_MAX < 64) || (_vec_ < 64)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 32)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else if ((CYGNUM_HAL_ISR_MAX < 96) || (_vec_ < 96)) { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << (_vec_ - 64)) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 96)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // HAL_MCFxxxx_INTCx_CIMR +# endif // !defined(HAL_INTERRUPT_UNMASK) + +# ifndef HAL_INTERRUPT_SET_LEVEL +// Each interrupt vector has its own priority register. This consists +// of an M68K IPL level between 1 and 7, plus a priority within each +// level between 0 and 7, giving a total of 56 legal priorities. All +// active interrupt vectors within each interrupt vector must be given +// unique priorities, otherwise the system's behaviour is undefined +// (and can include the interrupt controller supplying the wrong +// interrupt vector in the IACK cycle). +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) + +# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \ + HAL_WRITE_UINT8(_reg_, _prilevel_); \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + if( _vec_ < 64 ) \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \ + else \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_ - 64;\ + HAL_WRITE_UINT8(_reg_, _prilevel_); \ + CYG_MACRO_END + +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // !defined(HAL_INTERRUPT_SET_LEVEL) + +#endif // HAL_MCFxxxx_HAS_MCF5282_INTC + +#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT +// There is no acknowledgement support inside the interrupt +// controller. Instead each device has its own way of clearing the +// interrupt, so it is left to device drivers to clear interrupts at +// an appropriate time. The exception is for the edge port interrupts +// which can be handled easily here. +# ifndef HAL_INTERRUPT_ACKNOWLEDGE +# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \ + } \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT) +# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \ + } else if ((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT1_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT1_VECBASE)); \ + } \ + CYG_MACRO_END + + +# else +# error At most two edge port modules are supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many +# endif // !defined(HAL_INTERRUPT_ACKNOWLEDGE) + +# ifndef HAL_INTERRUPT_CONFIGURE + +// Interrupt level/edge control only applies to the edge port +// interrupts. It is possible to select level-low, rising edge, or +// falling edge. The hardware does not support level-high. It does +// support rising-or-falling edge, but the eCos API does not export +// that functionality. Instead code can manipulate the edge port +// registers directly. +// +// This macro also manipulates the edge port data direction and +// interrupt enable registers, to ensure that the edge port really +// will generate interrupts. + +# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + cyg_uint32 _base_; \ + cyg_uint16 _reg16_; \ + cyg_uint8 _reg8_; \ + _base_ = HAL_MCFxxxx_EPORT0_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + _reg16_ &= ~(0x03 << (2 * _vec_)); \ + if (_level_triggered_) { \ + /* 00 is level-triggered so nothing to be done */ \ + } else if (_up_) { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \ + } else { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \ + } \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + _reg8_ &= ~(0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + _reg8_ |= (0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + } \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) || \ + ((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX))) { \ + cyg_uint32 _base_; \ + cyg_uint16 _reg16_; \ + cyg_uint8 _reg8_; \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + _base_ = HAL_MCFxxxx_EPORT0_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \ + } else { \ + _base_ = HAL_MCFxxxx_EPORT1_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT1_VECBASE; \ + } \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + _reg16_ &= ~(0x03 << (2 * _vec_)); \ + if (_level_triggered_) { \ + /* 00 is level-triggered so nothing to be done */ \ + } else if (_up_) { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \ + } else { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \ + } \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + _reg8_ &= ~(0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + _reg8_ |= (0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + } \ + CYG_MACRO_END + +# else +# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many +# endif // !defined(HAL_INTERRUPT_CONFIGURE) + +#endif + +#ifndef HAL_INTERRUPT_MASK +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_MASK() macro +#endif +#ifndef HAL_INTERRUPT_UNMASK +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_UNMASK() macro +#endif +#ifndef HAL_INTERRUPT_SET_LEVEL +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_SET_LEVEL() macro +#endif +#ifndef HAL_INTERRUPT_ACKNOWLEDGE +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_ACKNOWLEDGE() macro +#endif +#ifndef HAL_INTERRUPT_CONFIGURE +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_CONFIGURE() macro +#endif + +// ---------------------------------------------------------------------------- +// On ColdFires with 5282-style programmable interrupt timers, typically +// one of those will be used for the system clock. +#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT + +# if (!defined(HAL_CLOCK_INIITALIZE) || !defined(HAL_CLOCK_RESET) || !defined(HAL_CLOCK_READ)) +# if !defined(_HAL_MCFxxxx_CLOCK_PIT_BASE_) +# error The processor HAL should specify the programmable interrupt timer used for the system clock +# elif !defined(_HAL_MCFxxxx_CLOCK_PIT_PRE_) +# error The processor or platform HAL should specify the timer prescaler +# else + +# if !defined(HAL_CLOCK_INITIALIZE) +# define HAL_CLOCK_INITIALIZE(_period_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD); \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \ + HAL_MCFxxxx_PITx_PCSR_EN); \ + CYG_MACRO_END +# endif + +# if !defined(HAL_CLOCK_RESET) +// The clock resets automatically but the interrupt must be cleared. This could +// be done by rewriting the period, but that introduces a risk of drift. A +// better approach is to write the PIF bit in the control register, which means +// writing all the other bits as well. +// +// Note: this could interfere with power management since the doze/halted +// bits may get cleared inadvertently. +# define HAL_CLOCK_RESET(_vector_, _period_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \ + HAL_MCFxxxx_PITx_PCSR_EN); \ + CYG_MACRO_END +# endif + +# if !defined(HAL_CLOCK_READ) +# define HAL_CLOCK_READ(_pvalue_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + cyg_uint16 _period_, _counter_; \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PCNTR, _counter_); \ + *(_pvalue_) = _period_ - _counter_; \ + CYG_MACRO_END +# endif +# endif +# endif +#endif + +#ifndef HAL_CLOCK_INITIALIZE +# error Processor or platform HAL should have provided HAL_CLOCK_INITIALIZE() macro +#endif +#ifndef HAL_CLOCK_RESET +# error Processor or platform HAL should have provided HAL_CLOCK_RESET() macro +#endif +#ifndef HAL_CLOCK_READ +# error Processor or platform HAL should have provided HAL_CLOCK_READ() macro +#endif + +#ifndef HAL_CLOCK_LATENCY +# define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_) +#endif + +// ---------------------------------------------------------------------------- +// Where possible use a 5282-compatible reset controller to generate a +// software reset. The architectural HAL has a fall-back +// implementation which goes through the reset exception vector slot. +#if !defined(HAL_PLATFORM_RESET) && defined(HAL_MCFxxxx_HAS_MCF5282_RST) +# define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_RST_BASE + HAL_MCFxxxx_RST_RCR, \ + HAL_MCFxxxx_RST_RCR_SOFTRST); \ + CYG_MACRO_END +# endif + //--------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_VAR_INTR_H -
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_io.h @@ -0,0 +1,2108 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H + +//============================================================================= +// +// var_io.h +// +// Details of mcfxxxx memory-mapped hardware +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +// Most coldfire processors share some/most of their on-chip +// peripherals with the mcf5282, so that is treated as the base +// device. The goal is to reduce the effort needed to support each +// ColdFire processor. The processor HAL still has the ability to +// override any of the settings to cope with differences between +// its processor and the 5282, with a small risk that device drivers +// are tied too closely to the 5282 implementation and need extra +// effort. The processor HAL also has to supply some information that +// is inherently too processor-specific, e.g. interrupt assignments +// and GPIO pin management. +// +// This header is #include'd by hal_io.h from the architectural HAL. +// It then #include's proc_io.h for the first time, giving the processor +// HAL a chance to define symbols such as: +// +// HAL_MCFxxxx_HAS_MCF5282_WD +// HAL_MCFxxxx_WD_BASE +// HAL_MCFxxxx_HAS_MCF5282_ETH +// HAL_MCFxxxx_ETH0_BASE +// +// The value of HAS_MCF5282_<module> corresponds to the number of +// devices. The _BASE symbols correspond to the absolute base +// addresses, e.g. (IPSBAR+0x0C00). For singleton devices there will +// be only a single base addresses, otherwise separate base addresses +// should be supplied for each device instance. +// +// Once the processor HAL has defined which mcf5282-compatible devices +// are present, this header file provides the appropriate I/O +// definitions. proc_io.h is then #include'd again so that it can undo +// some of these definitions, e.g. when some h/w functionality +// available on the 5282 is not present, or to extend the definitions +// if a device offers more than functionality than the 5282 +// equivalent. Definitions for devices not present on a 5282 can be +// provided by either the first or second pass of proc_io.h. Finally +// proc_io.h will include plf_io.h, allowing platform-specific code to +// override some of the definitions or to provide additional ones for +// off-chip devices. +// +// During the second pass through proc_io.h, if a processor HAL +// #undef's a var_io.h definition then that can cause problems with +// device driver portability. There is no perfect way to handle that, +// if h/w is not 100% compatible then device drivers will struggle. +// Additional symbols will typically not be used by device drivers so +// do not cause any portability problems, but eCos will not exploit +// the extra functionality either. +// +// Symbols take the form: +// HAL_MCFxxxx_<module>_<register> +// HAL_MCFxxxx_<module>x_<register> +// HAL_MCFxxxx_<module>_<register>_<field> +// HAL_MCFxxxx_<module>x_<register>_<field> +// +// The x version is used when there may be multiple instances of a +// given device, e.g. multiple UARTs or multiple interrupt +// controllers. + +// First read in the processor-specific header so we know which +// peripherals are common. The header will be read in again at +// the end to allow the processor HAL to override some of the +// settings defined here. +#include <cyg/hal/proc_io.h> + +// ---------------------------------------------------------------------------- +// System registers. Note that these are not memory-mapped, they are +// accessed via the movec instruction. + +// The cache control register and the access control registers +// go together. +#ifdef HAL_MCFxxxx_HAS_MCF5282_CACR_ACR +# define HAL_MCFxxxx_CACR 0x0002 +# define HAL_MCFxxxx_CACR_CENB (0x01 << 31) +# define HAL_MCFxxxx_CACR_CPD (0x01 << 28) +# define HAL_MCFxxxx_CACR_CPDI (0x01 << 28) +# define HAL_MCFxxxx_CACR_CFRZ (0x01 << 27) +# define HAL_MCFxxxx_CACR_CINV (0x01 << 24) +# define HAL_MCFxxxx_CACR_DISI (0x01 << 23) +# define HAL_MCFxxxx_CACR_DISD (0x01 << 22) +# define HAL_MCFxxxx_CACR_INVI (0x01 << 21) +# define HAL_MCFxxxx_CACR_INVD (0x01 << 20) +# define HAL_MCFxxxx_CACR_CEIB (0x01 << 10) +# define HAL_MCFxxxx_CACR_DCM (0x01 << 9) +# define HAL_MCFxxxx_CACR_DBWE (0x01 << 8) +# define HAL_MCFxxxx_CACR_DWP (0x01 << 5) +# define HAL_MCFxxxx_CACR_EUSP (0x01 << 4) +# define HAL_MCFxxxx_CACR_CLNF_MASK (0x03 << 0) +# define HAL_MCFxxxx_CACR_CLNF_SHIFT 0 + +// The two access control registers. These provide some control +// over external memory accesses. +# define HAL_MCFxxxx_ACR0 0x0004 +# define HAL_MCFxxxx_ACR1 0x0005 + +# define HAL_MCFxxxx_ACRx_AB_MASK (0x00FF << 24) +# define HAL_MCFxxxx_ACRx_AB_SHIFT 24 +# define HAL_MCFxxxx_ACRx_AM_MASK (0x00FF << 16) +# define HAL_MCFxxxx_ACRx_AM_SHIFT 16 +# define HAL_MCFxxxx_ACRx_EN (0x01 << 15) +# define HAL_MCFxxxx_ACRx_SM_MASK (0x03 << 13) +# define HAL_MCFxxxx_ACRx_SM_SHIFT 13 +# define HAL_MCFxxxx_ACRx_SM_USER_ONLY (0x00 << 13) +# define HAL_MCFxxxx_ACRx_SM_SUPERVISOR_ONLY (0x01 << 13) +# define HAL_MCFxxxx_ACRx_SM_ALWAYS (0x02 << 13) +# define HAL_MCFxxxx_ACRx_CM (0x01 << 6) +# define HAL_MCFxxxx_ACRx_BUFW (0x01 << 5) +# define HAL_MCFxxxx_ACRx_BWE (0x01 << 5) +# define HAL_MCFxxxx_ACRx_WP (0x01 << 2) +#endif // HAL_MCFxxxx_HAS_MCF5282_CACR_ACR + +#ifdef HAL_MCFxxxx_HAS_MCF5282_RAMBAR +# define HAL_MCFxxxx_RAMBAR 0x0C05 +# define HAL_MCFxxxx_RAMBAR_BA_MASK (0x00FFFF0000 << 0) +# define HAL_MCFxxxx_RAMBAR_BA_SHIFT 0 +# define HAL_MCFxxxx_RAMBAR_PRI_MASK (0x03 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_SHIFT 10 +# define HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU (0x03 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA (0x02 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU (0x01 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA (0x00 << 10) +# define HAL_MCFxxxx_RAMBAR_SPV (0x01 << 9) +# define HAL_MCFxxxx_RAMBAR_WP (0x01 << 8) +# define HAL_MCFxxxx_RAMBAR_CI (0x01 << 5) +# define HAL_MCFxxxx_RAMBAR_SC (0x01 << 4) +# define HAL_MCFxxxx_RAMBAR_SD (0x01 << 3) +# define HAL_MCFxxxx_RAMBAR_UC (0x01 << 2) +# define HAL_MCFxxxx_RAMBAR_UD (0x01 << 1) +# define HAL_MCFxxxx_RAMBAR_V (0x01 << 0) +#endif + +#ifdef HAL_MCFxxxx_HAS_MCF5282_FLASHBAR +# define HAL_MCFxxxx_FLASHBAR 0x0C04 +# define HAL_MCFxxxx_FLASHBAR_BA_MASK (0x00FFF80000 << 0) +# define HAL_MCFxxxx_FLASHBAR_BA_SHIFT 0 +# define HAL_MCFxxxx_FLASHBAR_WP (0x01 << 8) +# define HAL_MCFxxxx_FLASHBAR_CI (0x01 << 5) +# define HAL_MCFxxxx_FLASHBAR_SC (0x01 << 4) +# define HAL_MCFxxxx_FLASHBAR_SD (0x01 << 3) +# define HAL_MCFxxxx_FLASHBAR_UC (0x01 << 2) +# define HAL_MCFxxxx_FLASHBAR_UD (0x01 << 1) +# define HAL_MCFxxxx_FLASHBAR_V (0x01 << 0) +#endif + +#ifdef HAL_MCFxxxx_HAS_MCF5282_VBR +# define HAL_MCFxxxx_VBR 0x0801 +#endif + +// ---------------------------------------------------------------------------- +// SCM. For convenience this encapsulates the SCM system control +// module, the PMM power management module, the CCM chip configuration +// module, and the CLOCK clock module. These are interrelated in +// various ways, so are likely to be all present or all absent. + +#ifdef HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM +// IPSBAR, 32 bits, controls the base address of the on-chip +// peripherals. This is equivalent to the MBAR register on other +// processors, but is only accessible via IPSBAR rather than as a +// control register. This is a bit strange - in theory IPSBAR could be +// disabled, making it inaccessible without a reset. +# define HAL_MCFxxxx_SCM_IPSBAR 0x00000000 +// RAMBAR, 32 bits. In practise this should always be a copy of the +// control register, or rather of the bits that are supported in the SCM. +# define HAL_MCFxxxx_SCM_RAMBAR 0x00000008 +// Core reset status register, 8 bits. +# define HAL_MCFxxxx_SCM_CRSR 0x00000010 +// Core watchdog control register, 8 bits. +# define HAL_MCFxxxx_SCM_CWCR 0x00000011 +// Core watchdog service register, 8 bits +# define HAL_MCFxxxx_SCM_CWSR 0x00000013 +// Bus master park register, 32 bits +# define HAL_MCFxxxx_SCM_MPARK 0x0000001C +// Master privilege register, 8 bits +# define HAL_MCFxxxx_SCM_MPR 0x00000020 +// The access control registers, 9 * 8 bits. +# define HAL_MCFxxxx_SCM_PACR0 0x00000024 +# define HAL_MCFxxxx_SCM_PACR1 0x00000025 +# define HAL_MCFxxxx_SCM_PACR2 0x00000026 +# define HAL_MCFxxxx_SCM_PACR3 0x00000027 +# define HAL_MCFxxxx_SCM_PACR4 0x00000028 +# define HAL_MCFxxxx_SCM_PACR5 0x0000002A +# define HAL_MCFxxxx_SCM_PACR6 0x0000002B +# define HAL_MCFxxxx_SCM_PACR7 0x0000002C +# define HAL_MCFxxxx_SCM_PACR8 0x0000002E +# define HAL_MCFxxxx_SCM_GPACR0 0x00000030 +# define HAL_MCFxxxx_SCM_GPACR1 0x00000031 + + +# define HAL_MCFxxxx_SCM_IPSBAR_BA_MASK 0xC0000000 +# define HAL_MCFxxxx_SCM_IPSBAR_BA_SHIFT 30 +# define HAL_MCFxxxx_SCM_IPSBAR_V (0x01 << 0) + +# define HAL_MCFxxxx_SCM_RAMBAR_BA_MASK (0x00FFFF << 16) +# define HAL_MCFxxxx_SCM_RAMBAR_BA_SHIFT 16 +# define HAL_MCFxxxx_SCM_RAMBAR_BDE (0x01 << 9) + +# define HAL_MCFxxxx_SCM_CRSR_EXT (0x01 << 7) +# define HAL_MCFxxxx_SCM_CRSR_CWDR (0x01 << 5) + +# define HAL_MCFxxxx_SCM_CWCR_CWE (0x01 << 7) +# define HAL_MCFxxxx_SCM_CWCR_CWRI (0x01 << 6) +# define HAL_MCFxxxx_SCM_CWCR_CWT_MASK (0x07 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_SHIFT 3 +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_9 (0x00 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_11 (0x01 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_13 (0x02 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_15 (0x03 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_19 (0x04 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_23 (0x05 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_27 (0x06 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_31 (0x07 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWTA (0x01 << 2) +# define HAL_MCFxxxx_SCM_CWCR_CWTAVAL (0x01 << 1) +# define HAL_MCFxxxx_SCM_CWCR_CWTIF (0x01 << 0) + +// The magic values that should be written to the watchdog service register +# define HAL_MCFxxxx_SCM_CWSR_MAGIC0 0x0055 +# define HAL_MCFxxxx_SCM_CWSR_MAGIC1 0x00AA + +// Bus master parking. M3 is ethernet, M2 is DMA, M1 is internal, +// M0 is the ColdFire core. +# define HAL_MCFxxxx_SCM_MPARK_M2_P_EN (0x01 << 25) +# define HAL_MCFxxxx_SCM_MPARK_BCR24BIT (0x01 << 24) +# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_MASK (0x03 << 22) +# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_SHIFT 22 +# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_MASK (0x03 << 20) +# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_SHIFT 20 +# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_MASK (0x03 << 18) +# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_SHIFT 18 +# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_MASK (0x03 << 16) +# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_SHIFT 16 +# define HAL_MCFxxxx_SCM_MPARK_FIXED (0x01 << 14) +# define HAL_MCFxxxx_SCM_MPARK_TIMEOUT (0x01 << 13) +# define HAL_MCFxxxx_SCM_MPARK_PRKLAST (0x01 << 12) +# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_MASK (0x0F << 8) +# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_SHIFT 8 + +# define HAL_MCFxxxx_SCM_MPR_M3 (0x01 << 3) +# define HAL_MCFxxxx_SCM_MPR_M2 (0x01 << 2) +# define HAL_MCFxxxx_SCM_MPR_M1 (0x01 << 1) +# define HAL_MCFxxxx_SCM_MPR_M0 (0x01 << 0) + +// Each access control register is split into two nibbles +# define HAL_MCFxxxx_SCM_PACRx_LOCK1 (0x01 << 7) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_MASK (0x07 << 4) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_SHIFT 4 +# define HAL_MCFxxxx_SCM_PACRx_LOCK0 (0x01 << 3) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_MASK (0x07 << 0) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_SHIFT 0 + +// The access granted. Separated into supervisor and user. +// R for read access, W for write access, N for no-access. +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_RW 0x04 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_R 0x05 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_N 0x00 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_R 0x02 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_N 0x01 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_N_N 0x07 + +// Exactly which PACR nibbles control which on-chip peripherals +// is a processor property so defined in proc_io.h + +# define HAL_MCFxxxx_SCM_GPACR_LOCK (0x01 << 7) +# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_MASK (0x0F << 0) +# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_SHIFT 0 + +// Read/Write/eXecute/No access in supervisor and user modes +# define HAL_MCFxxxx_SCM_GPACR_RW_N 0x00 +# define HAL_MCFxxxx_SCM_GPACR_R_N 0x01 +# define HAL_MCFxxxx_SCM_GPACR_R_R 0x02 +# define HAL_MCFxxxx_SCM_GPACR_RW_RW 0x04 +# define HAL_MCFxxxx_SCM_GPACR_RW_R 0x05 +# define HAL_MCFxxxx_SCM_GPACR_N_N 0x07 +# define HAL_MCFxxxx_SCM_GPACR_RWX_N 0x08 +# define HAL_MCFxxxx_SCM_GPACR_RX_N 0x09 +# define HAL_MCFxxxx_SCM_GPACR_RX_RX 0x0A +# define HAL_MCFxxxx_SCM_GPACR_X_N 0x0B +# define HAL_MCFxxxx_SCM_GPACR_RWX_RWX 0x0C +# define HAL_MCFxxxx_SCM_GPACR_RWX_RX 0x0D +# define HAL_MCFxxxx_SCM_GPACR_RWX_X 0x0F + +// Power management. This can get confusing because there is an +// overlap with the chip configuration module, the reset module, and +// the system controller module. There are two registers, one in the +// SCM part of the address space, the other in the reset +// controller/chip configuration. Assume a single device. + +// 8-bit interrupt control register +# define HAL_MCFxxxx_PMM_LPICR 0x00000012 +// 8-bit control register. +# define HAL_MCFxxxx_PMM_LPCR 0x00110007 + +# define HAL_MCFxxxx_PMM_LPICR_ENBSTOP (0x01 << 7) +# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_MASK (0x07 << 4) +# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_SHIFT 4 + +# define HAL_MCFxxxx_PMM_LPCR_LPMD_MASK (0x03 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_SHIFT 6 +# define HAL_MCFxxxx_PMM_LPCR_LPMD_STOP (0x03 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_WAIT (0x02 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_DOZE (0x01 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_RUN (0x00 << 6) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_MASK (0x03 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_SHIFT 3 +# define HAL_MCFxxxx_PMM_LPCR_STPMD_CLKOUT_PLL_OSC_PMM (0x00 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_PLL_OSC_PMM (0x01 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_OSC_PMM (0x02 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_PMM (0x03 << 3) +# define HAL_MCFxxxx_PMM_LPCR_LVDSE (0x01 << 1) + +// The clock module. Assume a single device. +// Synthesizer control register, 16 bits +# define HAL_MCFxxxx_CLOCK_SYNCR 0x00120000 +// Synthesizer status register, 8 bits +# define HAL_MCFxxxx_CLOCK_SYNSR 0x00120002 + +# define HAL_MCFxxxx_CLOCK_SYNCR_LOLRE (0x01 << 15) +# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_MASK (0x07 << 12) +# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_SHIFT 12 +# define HAL_MCFxxxx_CLOCK_SYNCR_LOCRE (0x01 << 11) +# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_MASK (0x07 << 8) +# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_SHIFT 8 +# define HAL_MCFxxxx_CLOCK_SYNCR_LOCEN (0x01 << 7) +# define HAL_MCFxxxx_CLOCK_SYNCR_DISCLK (0x01 << 6) +# define HAL_MCFxxxx_CLOCK_SYNCR_FWKUP (0x01 << 5) +# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_MASK (0x03 << 2) +# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_SHIFT 2 + +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLMODE (0x01 << 7) +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLSEL (0x01 << 6) +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLREF (0x01 << 5) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCKS (0x01 << 4) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCK (0x01 << 3) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCS (0x01 << 2) + +// Chip configuration module +// Four 16-bit registers: chip configuration, low-power control, reset +// configuration, and chip identification. LPCR is described in the +// power management section. +# define HAL_MCFxxxx_CCM_CCR 0x00110004 +# define HAL_MCFxxxx_CCM_RCON 0x00110008 +# define HAL_MCFxxxx_CCM_CIR 0x0011000A + +# define HAL_MCFxxxx_CCM_CCR_LOAD (0x01 << 15) +# define HAL_MCFxxxx_CCM_CCR_MODE_MASK (0x07 << 8) +# define HAL_MCFxxxx_CCM_CCR_MODE_SHIFT 8 +# define HAL_MCFxxxx_CCM_CCR_MODE_SINGLE_CHIP (0x06 << 8) +# define HAL_MCFxxxx_CCM_CCR_MODE_MASTER (0x07 << 8) +# define HAL_MCFxxxx_CCM_CCR_SZEN (0x01 << 6) +# define HAL_MCFxxxx_CCM_CCR_PSTEN (0x01 << 5) +# define HAL_MCFxxxx_CCM_CCR_BME (0x01 << 3) +# define HAL_MCFxxxx_CCM_CCR_BMT_MASK (0x07 << 0) +# define HAL_MCFxxxx_CCM_CCR_BMT_SHIFT 0 +# define HAL_MCFxxxx_CCM_CCR_BMT_65536 0x00 +# define HAL_MCFxxxx_CCM_CCR_BMT_32768 0x01 +# define HAL_MCFxxxx_CCM_CCR_BMT_16384 0x02 +# define HAL_MCFxxxx_CCM_CCR_BMT_8192 0x03 +# define HAL_MCFxxxx_CCM_CCR_BMT_4096 0x04 +# define HAL_MCFxxxx_CCM_CCR_BMT_2048 0x05 +# define HAL_MCFxxxx_CCM_CCR_BMT_1024 0x06 +# define HAL_MCFxxxx_CCM_CCR_BMT_512 0x07 + +# define HAL_MCFxxxx_CCM_RCON_RCSC_MASK (0x03 << 8) +# define HAL_MCFxxxx_CCM_RCON_RCSC_SHIFT 8 +# define HAL_MCFxxxx_CCM_RCON_RPLLSEL (0x01 << 7) +# define HAL_MCFxxxx_CCM_RCON_RPLLREF (0x01 << 6) +# define HAL_MCFxxxx_CCM_RCON_RLOAD (0x01 << 5) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_MASK (0x03 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_SHIFT 3 +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_INTERNAL (0x00 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_16 (0x01 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_8 (0x02 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_32 (0x03 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTSEL (0x01 << 2) +# define HAL_MCFxxxx_CCM_RCON_MODE (0x01 << 0) + +# define HAL_MCF5282_CCM_CIR_PIN_MASK (0x00FF << 8) +# define HAL_MCF5282_CCM_CIR_PIN_SHIFT 8 +# define HAL_MCF5282_CCM_CIR_PRN_MASK (0x00FF << 0) +# define HAL_MCF5282_CCM_CIR_PRN_SHIFT 0 + +#endif // HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_RST +// Reset controller +// Two 8-bit registers, reset control and reset status +# define HAL_MCFxxxx_RST_RCR 0x00000000 +# define HAL_MCFxxxx_RST_RSR 0x00000001 + +# define HAL_MCFxxxx_RST_RCR_SOFTRST (0x01 << 7) +# define HAL_MCFxxxx_RST_RCR_FRCRSTOUT (0x01 << 6) +# define HAL_MCFxxxx_RST_RCR_LVDF (0x01 << 4) +# define HAL_MCFxxxx_RST_RCR_LVDIE (0x01 << 3) +# define HAL_MCFxxxx_RST_RCR_LVDRE (0x01 << 2) +# define HAL_MCFxxxx_RST_RCR_LVDE (0x01 << 0) + +# define HAL_MCFxxxx_RST_RSR_LVD (0x01 << 6) +# define HAL_MCFxxxx_RST_RSR_SOFT (0x01 << 5) +# define HAL_MCFxxxx_RST_RSR_WDR (0x01 << 4) +# define HAL_MCFxxxx_RST_RSR_POR (0x01 << 3) +# define HAL_MCFxxxx_RST_RSR_EXT (0x01 << 2) +# define HAL_MCFxxxx_RST_RSR_LOC (0x01 << 1) +# define HAL_MCFxxxx_RST_RSR_LOL (0x01 << 0) +#endif + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_WD +// Watchdog timer. Only a single device. +// Four 16-bit registers: control, modulus, count and service +# define HAL_MCFxxxx_WD_WCR 0x00000000 +# define HAL_MCFxxxx_WD_WMR 0x00000002 +# define HAL_MCFxxxx_WD_WCNTR 0x00000004 +# define HAL_MCFxxxx_WD_WSR 0x00000006 + +# define HAL_MCFxxxx_WD_WCR_WAIT (0x01 << 3) +# define HAL_MCFxxxx_WD_WCR_DOZE (0x01 << 2) +# define HAL_MCFxxxx_WD_WCR_HALTED (0x01 << 1) +# define HAL_MCFxxxx_WD_WCR_EN (0x01 << 0) + +// The modulus and count registers are just 16 bits of counter data +// The magic numbers for the service register +# define HAL_MCF5282_WD_WSR_MAGIC0 0x5555 +# define HAL_MCF5282_WD_WSR_MAGIC1 0xAAAA + +#endif // HAL_MCFxxxx_HAS_MCF5282_WD + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CS +// Chip select module. Assume a single device. + +// Seven sets of registers, a 16-bit address register, a 32-bit +// mask register and a 16-bit control register +# define HAL_MCFxxxx_CS_CSAR0 0x00000080 +# define HAL_MCFxxxx_CS_CSMR0 0x00000084 +# define HAL_MCFxxxx_CS_CSCR0 0x0000008A +# define HAL_MCFxxxx_CS_CSAR1 0x0000008C +# define HAL_MCFxxxx_CS_CSMR1 0x00000090 +# define HAL_MCFxxxx_CS_CSCR1 0x00000096 +# define HAL_MCFxxxx_CS_CSAR2 0x00000098 +# define HAL_MCFxxxx_CS_CSMR2 0x0000009C +# define HAL_MCFxxxx_CS_CSCR2 0x000000A2 +# define HAL_MCFxxxx_CS_CSAR3 0x000000A4 +# define HAL_MCFxxxx_CS_CSMR3 0x000000A8 +# define HAL_MCFxxxx_CS_CSCR3 0x000000AE +# define HAL_MCFxxxx_CS_CSAR4 0x000000B0 +# define HAL_MCFxxxx_CS_CSMR4 0x000000B4 +# define HAL_MCFxxxx_CS_CSCR4 0x000000BA +# define HAL_MCFxxxx_CS_CSAR5 0x000000BC +# define HAL_MCFxxxx_CS_CSMR5 0x000000C0 +# define HAL_MCFxxxx_CS_CSCR5 0x000000C6 +# define HAL_MCFxxxx_CS_CSAR6 0x000000C8 +# define HAL_MCFxxxx_CS_CSMR6 0x000000CC +# define HAL_MCFxxxx_CS_CSCR6 0x000000D2 + +// The address register is just the top 16 bits of the address. +# define HAL_MCFxxxx_CS_CSMRx_BAM_MASK (0x00FFFF << 16) +# define HAL_MCFxxxx_CS_CSMRx_BAM_SHIFT 16 +# define HAL_MCFxxxx_CS_CSMRx_WP (0x01 << 8) +# define HAL_MCFxxxx_CS_CSMRx_AM (0x01 << 6) +# define HAL_MCFxxxx_CS_CSMRx_CI (0x01 << 5) +# define HAL_MCFxxxx_CS_CSMRx_SC (0x01 << 4) +# define HAL_MCFxxxx_CS_CSMRx_SD (0x01 << 3) +# define HAL_MCFxxxx_CS_CSMRx_UC (0x01 << 2) +# define HAL_MCFxxxx_CS_CSMRx_UD (0x01 << 1) +# define HAL_MCFxxxx_CS_CSMRx_V (0x01 << 0) + +# define HAL_MCFxxxx_CS_CSCRx_WS_MASK (0x000F << 10) +# define HAL_MCFxxxx_CS_CSCRx_WS_SHIFT 10 +# define HAL_MCFxxxx_CS_CSCRx_AA (0x01 << 8) +# define HAL_MCFxxxx_CS_CSCRx_PS_MASK (0x03 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_SHIFT 6 +# define HAL_MCFxxxx_CS_CSCRx_PS_32 (0x00 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_8 (0x01 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_16 (0x02 << 6) +# define HAL_MCFxxxx_CS_CSCRx_BEM (0x01 << 5) +# define HAL_MCFxxxx_CS_CSCRx_BSTR (0x01 << 4) +# define HAL_MCFxxxx_CS_CSCRx_BSTW (0x01 << 3) + +#endif // HAL_MCFxxxx_HAS_MCF5282_CS + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_SDRAMC +// SDRAM controller. Assume a single device. + +// A 16-bit overall control register +# define HAL_MCFxxxx_SDRAMC_DCR 0x00000040 +// Two sets of two 32-bit registers +# define HAL_MCFxxxx_SDRAMC_DACR0 0x00000048 +# define HAL_MCFxxxx_SDRAMC_DMR0 0x0000004C +# define HAL_MCFxxxx_SDRAMC_DACR1 0x00000050 +# define HAL_MCFxxxx_SDRAMC_DMR1 0x00000054 + +# define HAL_MCFxxxx_SDRAMC_DCR_NAM (0x01 << 13) +# define HAL_MCFxxxx_SDRAMC_DCR_COC (0x01 << 12) +# define HAL_MCFxxxx_SDRAMC_DCR_IS (0x01 << 11) +# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_MASK (0x03 << 9) +# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_SHIFT 9 +# define HAL_MCFxxxx_SDRAMC_DCR_RC_MASK (0x01FF << 0) +# define HAL_MCFxxxx_SDRAMC_DCR_RC_SHIFT 0 + +# define HAL_MCFxxxx_SDRAMC_DACRx_BA_MASK (0x03FFF << 18) +# define HAL_MCFxxxx_SDRAMC_DACRx_BA_SHIFT 18 +# define HAL_MCFxxxx_SDRAMC_DACRx_RE (0x01 << 15) +# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_MASK (0x03 << 12) +# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_SHIFT 12 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_MASK (0x07 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_SHIFT 8 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_17 0x00 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_18 0x01 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_19 0x02 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_20 0x03 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_21 0x04 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_22 0x05 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_23 0x06 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_24 0x07 +# define HAL_MCFxxxx_SDRAMC_DACRx_IMRS (0x01 << 6) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_MASK (0x03 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_SHIFT 4 +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_32 (0x00 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_8 (0x01 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_16 (0x02 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_IP (0x01 << 3) + +# define HAL_MCFxxxx_SDRAMC_DMRx_BA_MASK (0x03FFF << 18) +# define HAL_MCFxxxx_SDRAMC_DMRx_BA_SHIFT 18 +# define HAL_MCFxxxx_SDRAMC_DMRx_WP (0x01 << 8) +# define HAL_MCFxxxx_SDRAMC_DMRx_CI (0x01 << 6) +# define HAL_MCFxxxx_SDRAMC_DMRx_AM (0x01 << 5) +# define HAL_MCFxxxx_SDRAMC_DMRx_SC (0x01 << 4) +# define HAL_MCFxxxx_SDRAMC_DMRx_SD (0x01 << 3) +# define HAL_MCFxxxx_SDRAMC_DMRx_UC (0x01 << 2) +# define HAL_MCFxxxx_SDRAMC_DMRx_UD (0x01 << 1) +# define HAL_MCFxxxx_SDRAMC_DMRx_V (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_SDRAMC + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CFM + +// The CFM module - on-chip flash. Assume a single device. +// Configuration register, 16 bits. +# define HAL_MCFxxxx_CFM_CR 0x0000 +// Clock divider register, 8 bits. +# define HAL_MCFxxxx_CFM_CLKD 0x0002 +// Security register, 32 bits +# define HAL_MCFxxxx_CFM_SEC 0x0008 +// Protection register, 32 bits +# define HAL_MCFxxxx_CFM_PROT 0x0010 +// Supervisor access register, 32 bits +# define HAL_MCFxxxx_CFM_SACC 0x0014 +// Data access register, 32 bits +# define HAL_MCFxxxx_CFM_DACC 0x0018 +// User status register, 8 bits +# define HAL_MCFxxxx_CFM_USTAT 0x0020 +// Command register, 8 bits +# define HAL_MCFxxxx_CFM_CMD 0x0024 + +# define HAL_MCFxxxx_CFM_CR_LOCK (0x01 << 10) +# define HAL_MCFxxxx_CFM_CR_PVIE (0x01 << 9) +# define HAL_MCFxxxx_CFM_CR_AEIE (0x01 << 8) +# define HAL_MCFxxxx_CFM_CR_CBEIE (0x01 << 7) +# define HAL_MCFxxxx_CFM_CR_CCIE (0x01 << 6) +# define HAL_MCFxxxx_CFM_CR_KEYACC (0x01 << 5) + +# define HAL_MCFxxxx_CFM_CLKD_DIVLD (0x01 << 7) +# define HAL_MCFxxxx_CFM_CLKD_PRDIV8 (0x01 << 6) +# define HAL_MCFxxxx_CFM_CLKD_DIV_MASK (0x3F << 0) +# define HAL_MCFxxxx_CFM_CLKD_DIV_SHIFT 0 + +# define HAL_MCFxxxx_CFM_SEC_KEYEN (0x01 << 31) +# define HAL_MCFxxxx_CFM_SEC_SECSTAT (0x01 << 30) +# define HAL_MCFxxxx_CFM_SEC_SEC_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_CFM_SEC_SEC_SHIFT 0 +# define HAL_MCFxxxx_CFM_SEC_SEC_MAGIC 0x4AC8 + +// The PROT protection register is just 32 bits, each bit protecting +// one flash sector. 0 means not protected. + +// The SACC supervisor access register similarly is 32 bits controlling +// access to the flash. 0 allows access in both user and supervisor modes. + +// The DACC data access register is 32 bits determining whether or not +// each sector can contain code. 0 means code is possible. + +# define HAL_MCFxxxx_CFM_USTAT_CBEIF (0x01 << 7) +# define HAL_MCFxxxx_CFM_USTAT_CCIF (0x01 << 6) +# define HAL_MCFxxxx_CFM_USTAT_PVIOL (0x01 << 5) +# define HAL_MCFxxxx_CFM_USTAT_ACCERR (0x01 << 4) +# define HAL_MCFxxxx_CFM_USTAT_BLANK (0x01 << 2) + +# define HAL_MCFxxxx_CFM_CMD_RDARY1 0x05 +# define HAL_MCFxxxx_CFM_CMD_PGERSVER 0x06 +# define HAL_MCFxxxx_CFM_CMD_PGM 0x20 +# define HAL_MCFxxxx_CFM_CMD_PGERS 0x40 +# define HAL_MCFxxxx_CFM_CMD_MASERS 0x41 + +# if !defined(__ASSEMBLER__) && !defined(__LDI__) +// On reset some of the CFM settings are initialized from a structure +// @ offset 0x00000400 in the flash. When booting from the internal +// flash the FLASHBAR register is initialized to address 0, read-only +// and valid. Presumably it is expected that the first 1K will be +// filled with exception vectors, so the next 24 bytes are used for +// flash settings. Real code can follow afterwards. +typedef struct hal_mcfxxxx_cfm_security_settings { + cyg_uint64 cfm_backdoor_key; + cyg_uint32 cfm_prot; + cyg_uint32 cfm_sacc; + cyg_uint32 cfm_dacc; + cyg_uint32 cfm_sec; +} hal_mcfxxxx_cfm_security_settings; +# endif + +#endif // HAL_MCFxxxx_HAS_MCF5282_CFM + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC +// Support one or more INTC controllers, depending on the number of +// interrup sources. + +// Two 32-bit interrupt pending registers +# define HAL_MCFxxxx_INTCx_IPRH 0x0000 +# define HAL_MCFxxxx_INTCx_IPRL 0x0004 +// Two 32-bit interrupt mask registers +# define HAL_MCFxxxx_INTCx_IMRH 0x0008 +# define HAL_MCFxxxx_INTCx_IMRL 0x000C +// Two 32-bit interrupt force registers +# define HAL_MCFxxxx_INTCx_INTFRCH 0x0010 +# define HAL_MCFxxxx_INTCx_INTFRCL 0x0014 +// 8-bit interrupt request level register +# define HAL_MCFxxxx_INTCx_IRLR 0x0018 +// 8-bit interrupt acknowledge level/priority register +# define HAL_MCFxxxx_INTCx_IACKLPR 0x0019 +// 64 8-bit interrupt control registers, determining the priorities +// of each interrupt source. ICR00 is actually invalid but useful for +// array indexing. +# define HAL_MCFxxxx_INTCx_ICR00 0x0040 +// 8-bit ACK registers. These can be checked in an interrupt handler +// to chain, avoiding the overheads of another interrupt, but at +// the cost of a couple of extra cycles even when no other interrupts +// are pending. Unless the interrupt load is very heavy this is +// likely to be a bad trade off. +# define HAL_MCFxxxx_INTCx_SWIACK 0x00E0 +# define HAL_MCFxxxx_INTCx_L1IACK 0x00E4 +# define HAL_MCFxxxx_INTCx_L2IACK 0x00E8 +# define HAL_MCFxxxx_INTCx_L3IACK 0x00EC +# define HAL_MCFxxxx_INTCx_L4IACK 0x00F0 +# define HAL_MCFxxxx_INTCx_L5IACK 0x00F4 +# define HAL_MCFxxxx_INTCx_L6IACK 0x00F8 +# define HAL_MCFxxxx_INTCx_L7IACK 0x00FC + +// Global IACK registers, all 8-bits +# define HAL_MCFxxxx_INTC_GSWACKR 0x0FE0 +# define HAL_MCFxxxx_INTC_GL1IACKR 0x0FE4 +# define HAL_MCFxxxx_INTC_GL2IACKR 0x0FE8 +# define HAL_MCFxxxx_INTC_GL3IACKR 0x0FEC +# define HAL_MCFxxxx_INTC_GL4IACKR 0x0FF0 +# define HAL_MCFxxxx_INTC_GL5IACKR 0x0FF4 +# define HAL_MCFxxxx_INTC_GL6IACKR 0x0FF8 +# define HAL_MCFxxxx_INTC_GL7IACKR 0x0FFC + +// The pending, mask and force registers are just 32 bits with one bit +// per interrupt source. +// +// The IRLR registers is just 8 bits with one bit per interrupt +// priority level. Priority level 0 corresponds to no pending +// interrupts, of course. + +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_MASK (0x07 << 4) +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_SHIFT 4 +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_MASK (0x0F << 0) +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_SHIFT 0 + +# define HAL_MCFxxxx_INTCx_ICRxx_IL_MASK (0x07 << 3) +# define HAL_MCFxxxx_INTCx_ICRxx_IL_SHIFT 3 +# define HAL_MCFxxxx_INTCx_ICRxx_IP_MASK (0x07 << 0) +# define HAL_MCFxxxx_INTCx_ICRxx_IP_SHIFT 0 + +# ifdef HAL_MCFxxxx_HAS_INTC_SIMCIMETC +# undef HAL_MCFxxxx_INTCx_IACKLPR +# define HAL_MCFxxxx_INTCx_ICONFIG 0x0000001A +# define HAL_MCFxxxx_INTCx_SIMR 0x0000001C +# define HAL_MCFxxxx_INTCx_CIMR 0x0000001D +# define HAL_MCFxxxx_INTCx_CLMASK 0x0000001E +# define HAL_MCFxxxx_INTCx_SLMASK 0x0000001F + +# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_MASK (0x7F << 9) +# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_SHIFT 9 +# define HAL_MCFxxxx_INTCx_ICONFIG_EMASK (0x01 << 5) +# endif + +#endif // HAL_MCFxxxx_HAS_MCF5282_INTC + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT +// Edge port module, pins which can be configured to trigger interrupts. + +// Pin assignment register, 16 bits +# define HAL_MCFxxxx_EPORTx_EPPAR 0x0000 +// Data direction register, 8 bits +# define HAL_MCFxxxx_EPORTx_EPDDR 0x0002 +// Interrupt enable register, 8 bits +# define HAL_MCFxxxx_EPORTx_EPIER 0x0003 +// Data register (output), 8 bits +# define HAL_MCFxxxx_EPORTx_EPDR 0x0004 +// Pin data register (input), 8 bits +# define HAL_MCFxxxx_EPORTx_EPPDR 0x0005 +// Flag register +# define HAL_MCFxxxx_EPORTx_EPFR 0x0006 + +// EPPAR is split into 2 bits per pin, the others use 1 bit per pin +// with bit 0 unused. +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_MASK (0x03 << 14) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_SHIFT 14 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_MASK (0x03 << 12) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_SHIFT 12 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_MASK (0x03 << 10) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_SHIFT 10 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_MASK (0x03 << 8) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_SHIFT 8 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_MASK (0x03 << 6) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_SHIFT 6 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_MASK (0x03 << 4) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_SHIFT 4 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_MASK (0x03 << 2) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_SHIFT 2 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_MASK (0x03 << 0) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_SHIFT 0 + +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_LEVEL 0x00 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING 0x01 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING 0x02 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_BOTH 0x03 + +#endif // HAL_MCFxxxx_HAS_MCF5282_EPORT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_DMA +// DMA. Support an arbitrary number of channels, although +// the DMA_REQC register effectively limits the number to 8. + +// DMA request controller, 1 32-bit register. This is assumed relative +// to SCM. It is in addition to the per-channel register definitions. +# define HAL_MCFxxxx_DMA_REQC 0x00000014 + +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 7) +# define HAL_MCFxxxx_DMA_REQC_DMAC7_MASK (0x0F << 28) +# define HAL_MCFxxxx_DMA_REQC_DMAC7_SHIFT 28 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 6) +# define HAL_MCFxxxx_DMA_REQC_DMAC6_MASK (0x0F << 24) +# define HAL_MCFxxxx_DMA_REQC_DMAC6_SHIFT 24 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 5) +# define HAL_MCFxxxx_DMA_REQC_DMAC5_MASK (0x0F << 20) +# define HAL_MCFxxxx_DMA_REQC_DMAC5_SHIFT 20 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 4) +# define HAL_MCFxxxx_DMA_REQC_DMAC4_MASK (0x0F << 16) +# define HAL_MCFxxxx_DMA_REQC_DMAC4_SHIFT 16 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 3) +# define HAL_MCFxxxx_DMA_REQC_DMAC3_MASK (0x0F << 12) +# define HAL_MCFxxxx_DMA_REQC_DMAC3_SHIFT 12 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 2) +# define HAL_MCFxxxx_DMA_REQC_DMAC2_MASK (0x0F << 8) +# define HAL_MCFxxxx_DMA_REQC_DMAC2_SHIFT 8 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 1) +# define HAL_MCFxxxx_DMA_REQC_DMAC1_MASK (0x0F << 4) +# define HAL_MCFxxxx_DMA_REQC_DMAC1_SHIFT 4 +#endif +# define HAL_MCFxxxx_DMA_REQC_DMAC0_MASK (0x0F << 0) +# define HAL_MCFxxxx_DMA_REQC_DMAC0_SHIFT 0 + +// Each DMA channel has 32-bit source, destination and control +// registers, a count register (up to 24 bits), and a 1-byte status +// register +# define HAL_MCFxxxx_DMAx_SARx 0x00000000 +# define HAL_MCFxxxx_DMAx_DARx 0x00000004 +# define HAL_MCFxxxx_DMAx_DCRx 0x00000008 +# define HAL_MCFxxxx_DMAx_BCRx 0x0000000C +# define HAL_MCFxxxx_DMAx_DSRx 0x00000010 + +# define HAL_MCFxxxx_DMAx_DCRx_INT (0x01 << 31) +# define HAL_MCFxxxx_DMAx_DCRx_EEXT (0x01 << 30) +# define HAL_MCFxxxx_DMAx_DCRx_CS (0x01 << 29) +# define HAL_MCFxxxx_DMAx_DCRx_AA (0x01 << 28) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_MASK (0x07 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_SHIFT 25 +# define HAL_MCFxxxx_DMAx_DCRx_BWC_PRIORITY (0x00 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_512_16384 (0x01 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_1024_32768 (0x02 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_2048_65536 (0x03 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_4096_131072 (0x04 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_8192_262144 (0x05 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_16384_524288 (0x06 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_32678_1048576 (0x07 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_SINC (0x01 << 22) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_MASK (0x03 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_SHIFT 20 +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LONGWORD (0x00 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_BYTE (0x01 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_WORD (0x02 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LINE (0x03 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_DINC (0x01 << 19) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_MASK (0x03 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_SHIFT 17 +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LONGWORD (0x00 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_BYTE (0x01 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_WORD (0x02 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LINE (0x03 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_START (0x01 << 16) +# define HAL_MCFxxxx_DMAx_DCRx_AT (0x01 << 15) + +# define HAL_MCFxxxx_DMAx_DSRx_CE (0x01 << 6) +# define HAL_MCFxxxx_DMAx_DSRx_BES (0x01 << 5) +# define HAL_MCFxxxx_DMAx_DSRx_BED (0x01 << 4) +# define HAL_MCFxxxx_DMAx_DSRx_REQ (0x01 << 2) +# define HAL_MCFxxxx_DMAx_DSRx_BSY (0x01 << 1) +# define HAL_MCFxxxx_DMAx_DSRx_DONE (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_DMA + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT +// Programmable interrupt timer modules + +# define HAL_MCFxxxx_PITx_PCSR 0x00000000 +# define HAL_MCFxxxx_PITx_PMR 0x00000002 +# define HAL_MCFxxxx_PITx_PCNTR 0x00000004 + +# define HAL_MCFxxxx_PITx_PCSR_PRE_MASK (0x0F < 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_SHIFT 8 +# define HAL_MCFxxxx_PITx_PCSR_PRE_2 (0x00 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_4 (0x01 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_8 (0x02 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_16 (0x03 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_32 (0x04 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_64 (0x05 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_128 (0x06 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_256 (0x07 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_512 (0x08 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_1024 (0x09 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_2048 (0x0A << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_4096 (0x0B << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_8192 (0x0C << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_16384 (0x0D << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_32768 (0x0E << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_65536 (0x0F << 8) +# define HAL_MCFxxxx_PITx_PCSR_DOZE (0x01 << 6) +# define HAL_MCFxxxx_PITx_PCSR_HALTED (0x01 << 5) +# define HAL_MCFxxxx_PITx_PCSR_DBG HAL_MCFxxxx_PITx_PCSR_HALTED +# define HAL_MCFxxxx_PITx_PCSR_OVW (0x01 << 4) +# define HAL_MCFxxxx_PITx_PCSR_PIE (0x01 << 3) +# define HAL_MCFxxxx_PITx_PCSR_PIF (0x01 << 2) +# define HAL_MCFxxxx_PITx_PCSR_RLD (0x01 << 1) +# define HAL_MCFxxxx_PITx_PCSR_EN (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_PIT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_GPT + +// General purpose timer modules +// 8-bit input capture/output compare register +# define HAL_MCFxxxx_GPTx_IOS 0x0000 +// 8-bit compare force register +# define HAL_MCFxxxx_GPTx_CFORC 0x0001 +// 8-bit output compare 3 mask register +# define HAL_MCFxxxx_GPTx_OC3M 0x0002 +// 8-bit output compare 3 data register +# define HAL_MCFxxxx_GPTx_OC3D 0x0003 +// 16-bit counter registers +# define HAL_MCFxxxx_GPTx_CNT 0x0004 +// 8-bit system control register 1 +# define HAL_MCFxxxx_GPTx_SCR1 0x0006 +// 8-bit toggle-on-overflow register +# define HAL_MCFxxxx_GPTx_TOV 0x0008 +// 8-bit control register 1 +# define HAL_MCFxxxx_GPTx_CTL1 0x0009 +// 8-bit control register 2 +# define HAL_MCFxxxx_GPTx_CTL2 0x000B +// 8-bit interrupt enable register +# define HAL_MCFxxxx_GPTx_IE 0x000C +// 8-bit system control register 2 +# define HAL_MCFxxxx_GPTx_SCR2 0x000D +// 8-bit flag registers +# define HAL_MCFxxxx_GPTx_FLG1 0x000E +# define HAL_MCFxxxx_GPTx_FLG2 0x000F +// 16-bit channel registers +# define HAL_MCFxxxx_GPTx_C0 0x0010 +# define HAL_MCFxxxx_GPTx_C1 0x0012 +# define HAL_MCFxxxx_GPTx_C2 0x0014 +# define HAL_MCFxxxx_GPTx_C3 0x0016 +// 8-bit pulse accumulator control register +# define HAL_MCFxxxx_GPTx_PACTL 0x0018 +// 8-bit pulse accumulator flag register +# define HAL_MCFxxxx_GPTx_PAFLG 0x0019 +// 16-bit pulse accumulator counter register +# define HAL_MCFxxxx_GPTx_PACNT 0x001A +// 8-bit port data registers +# define HAL_MCFxxxx_GPTx_PORT 0x001D +// 8-bit port data direction register +# define HAL_MCFxxxx_GPTx_DDR 0x001E + +# define HAL_MCFxxxx_GPTx_SCR1_GPTEN (0x01 << 7) +# define HAL_MCFxxxx_GPTx_SCR1_TFFCA (0x01 << 4) + +# define HAL_MCFxxxx_GPTx_SCR2_TOI (0x01 << 7) +# define HAL_MCFxxxx_GPTx_SCR2_PUPT (0x01 << 5) +# define HAL_MCFxxxx_GPTx_SCR2_RDPT (0x01 << 4) +# define HAL_MCFxxxx_GPTx_SCR2_TCRE (0x01 << 3) +# define HAL_MCFxxxx_GPTx_SCR2_PR_MASK (0x07 << 0) +# define HAL_MCFxxxx_GPTx_SCR2_PR_SHIFT 0 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV1 0x00 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV2 0x01 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV4 0x02 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV8 0x03 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV16 0x04 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV32 0x05 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV64 0x06 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV128 0x07 + +# define HAL_MCFxxxx_GPTx_FLG2_TOF (0x01 << 7) + +# define HAL_MCFxxxx_GPTx_PACTL_PAE (0x01 << 6) +# define HAL_MCFxxxx_GPTx_PACTL_PAMOD (0x01 << 5) +# define HAL_MCFxxxx_GPTx_PACTL_PEDGE (0x01 << 4) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_MASK (0x03 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_SHIFT 2 +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PRESCALER (0x00 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK (0x01 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_256 (0x02 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_65536 (0x03 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_PAOVI (0x01 << 1) +# define HAL_MCFxxxx_GPTx_PACTL_PAI (0x01 << 0) + +# define HAL_MCFxxxx_GPTx_PAFLG_PAOVF (0x01 << 1) +# define HAL_MCFxxxx_GPTx_PAFLG_PAIF (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_GPT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_DTMR + +// DMA timers +// 16-bit timer mode registers +# define HAL_MCFxxxx_DTMRx 0x0000 +// 8-bit extended mode registers +# define HAL_MCFxxxx_DTXMRx 0x0002 +// 8-bit event registers +# define HAL_MCFxxxx_DTERx 0x00003 +// 32-bit reference, capture and counter registers +# define HAL_MCFxxxx_DTRRx 0x0004 +# define HAL_MCFxxxx_DTCRx 0x0008 +# define HAL_MCFxxxx_DTCNx 0x000C + +# define HAL_MCFxxxx_DTMRx_PS_MASK (0x0FF << 8) +# define HAL_MCFxxxx_DTMRx_PS_SHIFT 8 +# define HAL_MCFxxxx_DTMRx_CE_MASK (0x03 << 6) +# define HAL_MCFxxxx_DTMRx_CE_SHIFT 6 +# define HAL_MCFxxxx_DTMRx_CE_DISABLE (0x00 << 6) +# define HAL_MCFxxxx_DTMRx_CE_RISING (0x01 << 6) +# define HAL_MCFxxxx_DTMRx_CE_FALLING (0x02 << 6) +# define HAL_MCFxxxx_DTMRx_CE_ANY (0x03 << 6) +# define HAL_MCFxxxx_DTMRx_OM (0x01 << 5) +# define HAL_MCFxxxx_DTMRx_ORRI (0x01 << 4) +# define HAL_MCFxxxx_DTMRx_FRR (0x01 << 3) +# define HAL_MCFxxxx_DTMRx_CLK_MASK (0x03 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_SHIFT 1 +# define HAL_MCFxxxx_DTMRx_CLK_STOP (0x00 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DIV_1 (0x01 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DIV_16 (0x02 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DTINn (0x03 << 1) +# define HAL_MCFxxxx_DTMRx_RST (0x01 << 0) + +# define HAL_MCFxxxx_DTXMRx_DMAEN (0x01 << 7) +# define HAL_MCFxxxx_DTXMRx_MODE16 (0x01 << 1) + +# define HAL_MCFxxxx_DTERx_REF (0x01 << 1) +# define HAL_MCFxxxx_DTERx_CAP (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_DTMR + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_ETH +// Ethernet. Allow for multiple devices. + +# define HAL_MCFxxxx_ETHx_EIR 0x0004 +# define HAL_MCFxxxx_ETHx_EIMR 0x0008 +# define HAL_MCFxxxx_ETHx_RDAR 0x0010 +# define HAL_MCFxxxx_ETHx_TDAR 0x0014 +# define HAL_MCFxxxx_ETHx_ECR 0x0024 +# define HAL_MCFxxxx_ETHx_MDATA 0x0040 +# define HAL_MCFxxxx_ETHx_MMFR 0x0040 +# define HAL_MCFxxxx_ETHx_MSCR 0x0044 +# define HAL_MCFxxxx_ETHx_MIBC 0x0064 +# define HAL_MCFxxxx_ETHx_RCR 0x0084 +# define HAL_MCFxxxx_ETHx_TCR 0x00C4 +# define HAL_MCFxxxx_ETHx_PALR 0x00E4 +# define HAL_MCFxxxx_ETHx_PAUR 0x00E8 +# define HAL_MCFxxxx_ETHx_OPD 0x00EC +# define HAL_MCFxxxx_ETHx_IAUR 0x0118 +# define HAL_MCFxxxx_ETHx_IALR 0x011C +# define HAL_MCFxxxx_ETHx_GAUR 0x0120 +# define HAL_MCFxxxx_ETHx_GALR 0x0124 +# define HAL_MCFxxxx_ETHx_TFWR 0x0144 +# define HAL_MCFxxxx_ETHx_FRBR 0x014C +# define HAL_MCFxxxx_ETHx_FRSR 0x0150 +# define HAL_MCFxxxx_ETHx_ERDSR 0x0180 +# define HAL_MCFxxxx_ETHx_ETDSR 0x0184 +# define HAL_MCFxxxx_ETHx_EMRBR 0x0188 + +# define HAL_MCFxxxx_ETHx_RMON_T_DROP 0x0200 +# define HAL_MCFxxxx_ETHx_RMON_T_PACKETS 0x0204 +# define HAL_MCFxxxx_ETHx_RMON_T_BC_PKT 0x0208 +# define HAL_MCFxxxx_ETHx_RMON_T_MC_PKT 0x020C +# define HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN 0x0210 +# define HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE 0x0214 +# define HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE 0x0218 +# define HAL_MCFxxxx_ETHx_RMON_T_FRAG 0x021C +# define HAL_MCFxxxx_ETHx_RMON_T_JAB 0x0220 +# define HAL_MCFxxxx_ETHx_RMON_T_COL 0x0224 +# define HAL_MCFxxxx_ETHx_RMON_T_P64 0x0228 +# define HAL_MCFxxxx_ETHx_RMON_T_P65TO127 0x022C +# define HAL_MCFxxxx_ETHx_RMON_T_P128TO255 0x0230 +# define HAL_MCFxxxx_ETHx_RMON_T_P256TO511 0x0234 +# define HAL_MCFxxxx_ETHx_RMON_T_P512TO1023 0x0238 +# define HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047 0x023C +# define HAL_MCFxxxx_ETHx_RMON_T_PGTE2048 0x0240 +# define HAL_MCFxxxx_ETHx_RMON_T_OCTETS 0x0244 +# define HAL_MCFxxxx_ETHx_IEEE_T_DROP 0x0248 +# define HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK 0x024C +# define HAL_MCFxxxx_ETHx_IEEE_T_1COL 0x0250 +# define HAL_MCFxxxx_ETHx_IEEE_T_MCOL 0x0254 +# define HAL_MCFxxxx_ETHx_IEEE_T_DEF 0x0258 +# define HAL_MCFxxxx_ETHx_IEEE_T_LCOL 0x025C +# define HAL_MCFxxxx_ETHx_IEEE_T_EXCOL 0x0260 +# define HAL_MCFxxxx_ETHx_IEEE_T_MACERR 0x0264 +# define HAL_MCFxxxx_ETHx_IEEE_T_CSERR 0x0268 +# define HAL_MCFxxxx_ETHx_IEEE_T_SQE 0x026C +# define HAL_MCFxxxx_ETHx_IEEE_T_FDXFC 0x0270 +# define HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK 0x0274 +# define HAL_MCFxxxx_ETHx_RMON_R_PACKETS 0x0284 +# define HAL_MCFxxxx_ETHx_RMON_R_BC_PKT 0x0288 +# define HAL_MCFxxxx_ETHx_RMON_R_MC_PKT 0x028C +# define HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN 0x0290 +# define HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE 0x0294 +# define HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE 0x0298 +# define HAL_MCFxxxx_ETHx_RMON_R_FRAG 0x029C +# define HAL_MCFxxxx_ETHx_RMON_R_JAB 0x02A0 +# define HAL_MCFxxxx_ETHx_RMON_R_RESVD_0 0x02A4 +# define HAL_MCFxxxx_ETHx_RMON_R_P64 0x02A8 +# define HAL_MCFxxxx_ETHx_RMON_R_P65TO127 0x02AC +# define HAL_MCFxxxx_ETHx_RMON_R_P128TO255 0x02B0 +# define HAL_MCFxxxx_ETHx_RMON_R_P256TO511 0x02B4 +# define HAL_MCFxxxx_ETHx_RMON_R_P512TO1023 0x02B8 +# define HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047 0x02BC +# define HAL_MCFxxxx_ETHx_RMON_R_GTE2048 0x02C0 +# define HAL_MCFxxxx_ETHx_RMON_R_OCTETS 0x02C4 +# define HAL_MCFxxxx_ETHx_IEEE_R_DROP 0x02C8 +# define HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK 0x02CC +# define HAL_MCFxxxx_ETHx_IEEE_R_CRC 0x02D0 +# define HAL_MCFxxxx_ETHx_IEEE_R_ALIGN 0x02D4 +# define HAL_MCFxxxx_ETHx_IEEE_R_MACERR 0x02D8 +# define HAL_MCFxxxx_ETHx_IEEE_R_FDXFC 0x02DC +# define HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK 0x02E0 + +# define HAL_MCFxxxx_ETHx_EIR_HBERR (0x01 << 31) +# define HAL_MCFxxxx_ETHx_EIR_BABR (0x01 << 30) +# define HAL_MCFxxxx_ETHx_EIR_BABT (0x01 << 29) +# define HAL_MCFxxxx_ETHx_EIR_GRA (0x01 << 28) +# define HAL_MCFxxxx_ETHx_EIR_TXF (0x01 << 27) +# define HAL_MCFxxxx_ETHx_EIR_TXB (0x01 << 26) +# define HAL_MCFxxxx_ETHx_EIR_RXF (0x01 << 25) +# define HAL_MCFxxxx_ETHx_EIR_RXB (0x01 << 24) +# define HAL_MCFxxxx_ETHx_EIR_MII (0x01 << 23) +# define HAL_MCFxxxx_ETHx_EIR_EBERR (0x01 << 22) +# define HAL_MCFxxxx_ETHx_EIR_LC (0x01 << 21) +# define HAL_MCFxxxx_ETHx_EIR_RL (0x01 << 20) +# define HAL_MCFxxxx_ETHx_EIR_UN (0x01 << 19) + +# define HAL_MCFxxxx_ETHx_EIMR_HBERR HAL_MCFxxxx_ETHx_EIR_HBERR +# define HAL_MCFxxxx_ETHx_EIMR_BABR HAL_MCFxxxx_ETHx_EIR_BABR +# define HAL_MCFxxxx_ETHx_EIMR_BABT HAL_MCFxxxx_ETHx_EIR_BABT +# define HAL_MCFxxxx_ETHx_EIMR_GRA HAL_MCFxxxx_ETHx_EIR_GRA +# define HAL_MCFxxxx_ETHx_EIMR_TXF HAL_MCFxxxx_ETHx_EIR_TXF +# define HAL_MCFxxxx_ETHx_EIMR_TXB HAL_MCFxxxx_ETHx_EIR_TXB +# define HAL_MCFxxxx_ETHx_EIMR_RXF HAL_MCFxxxx_ETHx_EIR_RXF +# define HAL_MCFxxxx_ETHx_EIMR_RXB HAL_MCFxxxx_ETHx_EIR_RXB +# define HAL_MCFxxxx_ETHx_EIMR_MII HAL_MCFxxxx_ETHx_EIR_MII +# define HAL_MCFxxxx_ETHx_EIMR_EBERR HAL_MCFxxxx_ETHx_EIR_EBERR +# define HAL_MCFxxxx_ETHx_EIMR_LC HAL_MCFxxxx_ETHx_EIR_LC +# define HAL_MCFxxxx_ETHx_EIMR_RL HAL_MCFxxxx_ETHx_EIR_RL +# define HAL_MCFxxxx_ETHx_EIMR_UN HAL_MCFxxxx_ETHx_EIR_UN + +# define HAL_MCFxxxx_ETHx_RDAR_R_DES_ACTIVE (0x01 << 24) +# define HAL_MCFxxxx_ETHx_TDAR_X_DES_ACTIVE (0x01 << 24) + +# define HAL_MCFxxxx_ETHx_ECR_ETHER_EN (0x01 << 1) +# define HAL_MCFxxxx_ETHx_ECR_RESET (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_MMFR_ST_MASK (0x03 << 30) +# define HAL_MCFxxxx_ETHx_MMFR_ST_SHIFT 30 +# define HAL_MCFxxxx_ETHx_MMFR_ST_VALUE (0x01 << 30) +# define HAL_MCFxxxx_ETHx_MMFR_OP_MASK (0x03 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_OP_READ (0x02 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_OP_WRITE (0x01 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_PA_MASK (0x1F << 23) +# define HAL_MCFxxxx_ETHx_MMFR_PA_SHIFT 23 +# define HAL_MCFxxxx_ETHx_MMFR_RA_MASK (0x1F << 18) +# define HAL_MCFxxxx_ETHx_MMFR_RA_SHIFT 18 +# define HAL_MCFxxxx_ETHx_MMFR_TA_MASK (0x03 << 16) +# define HAL_MCFxxxx_ETHx_MMFR_TA_SHIFT 16 +# define HAL_MCFxxxx_ETHx_MMFR_TA_VALUE (0x02 << 16) +# define HAL_MCFxxxx_ETHx_MMFR_DATA_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_ETHx_MMFR_DATA_SHIFT 0 + +# define HAL_MCFxxxx_ETHx_MSCR_DIS_PREAMBLE (0x01 << 7) +# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_MASK (0x3F << 1) +# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_SHIFT 1 + +# define HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE (0x01 << 31) +# define HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE (0x01 << 30) + +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK (0x03FFF << 16) +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT 16 +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE (1518 << 16) +# define HAL_MCFxxxx_ETHx_RCR_FCE (0x01 << 5) +# define HAL_MCFxxxx_ETHx_RCR_BC_REJ (0x01 << 4) +# define HAL_MCFxxxx_ETHx_RCR_PROM (0x01 << 3) +# define HAL_MCFxxxx_ETHx_RCR_MII_MODE (0x01 << 2) +# define HAL_MCFxxxx_ETHx_RCR_DRT (0x01 << 1) +# define HAL_MCFxxxx_ETHx_RCR_LOOP (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE (0x01 << 4) +# define HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE (0x01 << 3) +# define HAL_MCFxxxx_ETHx_TCR_FDEN (0x01 << 2) +# define HAL_MCFxxxx_ETHx_TCR_HBC (0x01 << 1) +# define HAL_MCFxxxx_ETHx_TCR_GTS (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK (0x0FFFF << 16) +# define HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT 16 +# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT 0 + +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_MASK (0x03 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_SHIFT 0 +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_64 (0x00 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_128 (0x02 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_192 (0x03 << 0) + +// This is the data structure for a buffer descriptor. +# if !defined( __ASSEMBLER__) && !defined(__LDI__) +typedef struct hal_mcfxxxx_eth_buffer_descriptor { + cyg_uint16 ethbd_flags; + cyg_uint16 ethbd_length; + cyg_uint8* ethbd_buffer; +} hal_mcfxxxx_eth_buffer_descriptor; +# endif + +# define HAL_MCFxxxx_ETHx_RXBD_E (0x01 << 15) +# define HAL_MCFxxxx_ETHx_RXBD_RO1 (0x01 << 14) +# define HAL_MCFxxxx_ETHx_RXBD_W (0x01 << 13) +# define HAL_MCFxxxx_ETHx_RXBD_RO2 (0x01 << 12) +# define HAL_MCFxxxx_ETHx_RXBD_L (0x01 << 11) +# define HAL_MCFxxxx_ETHx_RXBD_M (0x01 << 8) +# define HAL_MCFxxxx_ETHx_RXBD_BC (0x01 << 7) +# define HAL_MCFxxxx_ETHx_RXBD_MC (0x01 << 6) +# define HAL_MCFxxxx_ETHx_RXBD_LG (0x01 << 5) +# define HAL_MCFxxxx_ETHx_RXBD_NO (0x01 << 4) +# define HAL_MCFxxxx_ETHx_RXBD_CR (0x01 << 2) +# define HAL_MCFxxxx_ETHx_RXBD_OV (0x01 << 1) +# define HAL_MCFxxxx_ETHx_RXBD_TR (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_TXBD_R (0x01 << 15) +# define HAL_MCFxxxx_ETHx_TXBD_TO1 (0x01 << 14) +# define HAL_MCFxxxx_ETHx_TXBD_W (0x01 << 13) +# define HAL_MCFxxxx_ETHx_TXBD_TO2 (0x01 << 12) +# define HAL_MCFxxxx_ETHx_TXBD_L (0x01 << 11) +# define HAL_MCFxxxx_ETHx_TXBD_TC (0x01 << 10) +# define HAL_MCFxxxx_ETHx_TXBD_ABC (0x01 << 9) + +#endif // HAL_MCFxxxx_HAS_MCF5282_ETH + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_QSPI + +// QSPI +// Six 16-bit registers: mode, delay, wrap, interrupt, address and data +# define HAL_MCFxxxx_QSPIx_QMR 0x0000 +# define HAL_MCFxxxx_QSPIx_QDLYR 0x0004 +# define HAL_MCFxxxx_QSPIx_QWR 0x0008 +# define HAL_MCFxxxx_QSPIx_QIR 0x000C +# define HAL_MCFxxxx_QSPIx_QAR 0x0010 +# define HAL_MCFxxxx_QSPIx_QDR 0x0014 + +# define HAL_MCFxxxx_QSPIx_QMR_MSTR (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QMR_DOHIE (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_MASK (0x0F << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_SHIFT 10 +# define HAL_MCFxxxx_QSPIx_QMR_BITS_16 (0x00 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_8 (0x08 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_9 (0x09 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_10 (0x0A << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_11 (0x0B << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_12 (0x0C << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_13 (0x0D << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_14 (0x0E << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_15 (0x0F << 10) +# define HAL_MCFxxxx_QSPIx_QMR_CPOL (0x01 << 9) +# define HAL_MCFxxxx_QSPIx_QMR_CPHA (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QMR_BAUD_MASK (0x0FF << 0) +# define HAL_MCFxxxx_QSPIx_QMR_BAUD_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QDLYR_SPE (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_MASK (0x07F << 8) +# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_MASK (0x0FF << 0) +# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QWR_HALT (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QWR_WREN (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QWR_WRTO (0x01 << 13) +# define HAL_MCFxxxx_QSPIx_QWR_CSIV (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_MASK (0x0F << 8) +# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_MASK (0x0F << 4) +# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_SHIFT 4 +# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_MASK (0x0F << 0) +# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QIR_WCEFB (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTB (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTL (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QIR_WCEFE (0x01 << 11) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTE (0x01 << 10) +# define HAL_MCFxxxx_QSPIx_QIR_SPIFE (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QIR_WCEF (0x01 << 3) +# define HAL_MCFxxxx_QSPIx_QIR_ABRT (0x01 << 2) +# define HAL_MCFxxxx_QSPIx_QIR_SPIF (0x01 << 0) + +# define HAL_MCFxxxx_QSPIx_QCRn_CONT (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QCRn_BITSE (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QCRn_DT (0x01 << 13) +# define HAL_MCFxxxx_QSPIx_QCRn_DSCK (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_MASK (0x0F << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS0 (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS1 (0x02 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS2 (0x04 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS3 (0x08 << 8) +# define HAL_MCFxxxx_QSPI_QCRn_QSPI_CS_CSn(__n) ((__n) << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CSn(__n) ((__n) << 8) + +# define HAL_MCFxxxx_QSPIx_QAR_TX_BASE 0x0000 +# define HAL_MCFxxxx_QSPIx_QAR_RX_BASE 0x0010 +# define HAL_MCFxxxx_QSPIx_QAR_COMMAND_BASE 0x0020 + +# define HAL_MCFxxxx_QSPIx_DEV_TO_BAUD(_dev_setting_arg_, _baud_) \ + CYG_MACRO_START \ + cyg_uint32 _dev_setting_ = (cyg_uint32) (_dev_setting_arg_); \ + cyg_uint32 _result_; \ + if (0 == _dev_setting_) { \ + _result_ = 0; \ + } else { \ + _result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _dev_setting_); \ + } \ + _baud_ = _result_; \ + CYG_MACRO_END + +// When calculating a device setting, if the baud rate cannot be supported exactly +// then switch to the next slowest setting. +# define HAL_MCFxxxx_QSPIx_BAUD_TO_DEV(_baud_arg_, _dev_setting_) \ + CYG_MACRO_START \ + cyg_uint32 _baud_ = (cyg_uint32) (_baud_arg_); \ + cyg_uint32 _result_; \ + if (0 == _baud_) { \ + _result_ = 0; \ + } else { \ + _result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _baud_); \ + if (_baud_ != (CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _result_))) { \ + _result_++; \ + } \ + if (_result_ < 2) { \ + _result_ = 2; \ + } else if (_result_ > 255) { \ + _result_ = 255; \ + } \ + } \ + _dev_setting_ = _result_; \ + CYG_MACRO_END + +#endif // HAL_MCFxxxx_HAS_MCF5282_QSPI + +// ---------------------------------------------------------------------------- + +#ifdef HAL_MCFxxxx_HAS_MCF5282_UART +// All registers are a single byte. +# define HAL_MCFxxxx_UARTx_UMR 0x00 +# define HAL_MCFxxxx_UARTx_USR 0x04 +# define HAL_MCFxxxx_UARTx_UCSR 0x04 +# define HAL_MCFxxxx_UARTx_UCR 0x08 +# define HAL_MCFxxxx_UARTx_URB 0x0C +# define HAL_MCFxxxx_UARTx_UTB 0x0C +# define HAL_MCFxxxx_UARTx_UIPCR 0x10 +# define HAL_MCFxxxx_UARTx_UACR 0x10 +# define HAL_MCFxxxx_UARTx_UISR 0x14 +# define HAL_MCFxxxx_UARTx_UIMR 0x14 +# define HAL_MCFxxxx_UARTx_UBG1 0x18 +# define HAL_MCFxxxx_UARTx_UBG2 0x1C + +# define HAL_MCFxxxx_UARTx_UIP 0x34 +# define HAL_MCFxxxx_UARTx_UOP1 0x38 +# define HAL_MCFxxxx_UARTx_UOP0 0x3C + +# define HAL_MCFxxxx_UARTx_UMR1_RXRTS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UMR1_FFULL (0x01 << 6) +# define HAL_MCFxxxx_UARTx_UMR1_ERR (0x01 << 5) +# define HAL_MCFxxxx_UARTx_UMR1_PM_MASK (0x03 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_SHIFT 3 +# define HAL_MCFxxxx_UARTx_UMR1_PM_WITH (0x00 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_FORCE (0x01 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_NO (0x02 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_MULTIDROP (0x03 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PT (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UMR1_BC_MASK (0x03 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_SHIFT 0 +# define HAL_MCFxxxx_UARTx_UMR1_BC_5 (0x00 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_6 (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_7 (0x02 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_8 (0x03 << 0) + +# define HAL_MCFxxxx_UARTx_UMR2_CM_MASK (0x03 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_SHIFT 6 +# define HAL_MCFxxxx_UARTx_UMR2_CM_NORMAL (0x00 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_AUTO (0x01 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_LOCAL (0x02 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_REMOTE (0x03 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_TXRTS (0x01 << 5) +# define HAL_MCFxxxx_UARTx_UMR2_TXCTS (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UMR2_SB_MASK (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UMR2_SB_SHIFT 0 +// These two constants are only valid for 6-8 bits. 5 bit needs +// to be treated specially. +# define HAL_MCFxxxx_UARTx_UMR2_SB_1 (0x07 << 0) +# define HAL_MCFxxxx_UARTx_UMR2_SB_2 (0x0f << 0) + +# define HAL_MCFxxxx_UARTx_USR_RB (0x01 << 7) +# define HAL_MCFxxxx_UARTx_USR_FE (0x01 << 6) +# define HAL_MCFxxxx_UARTx_USR_PE (0x01 << 5) +# define HAL_MCFxxxx_UARTx_USR_OE (0x01 << 4) +# define HAL_MCFxxxx_UARTx_USR_TXEMP (0x01 << 3) +# define HAL_MCFxxxx_UARTx_USR_TXRDY (0x01 << 2) +# define HAL_MCFxxxx_UARTx_USR_FFULL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_USR_RXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UCSR_RCS_MASK (0x0f << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_SHIFT 4 +# define HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN (0x0D << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTINDIV16 (0x0E << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTIN (0x0F << 4) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_MASK (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_SHIFT (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN (0x0D << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTINDIV16 (0x0E << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTIN (0x0F << 0) + +# define HAL_MCFxxxx_UARTx_UCR_MISC_MASK (0x07 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_SHIFT 4 +# define HAL_MCFxxxx_UARTx_UCR_MISC_NOP (0x00 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RMRP (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RR (0x02 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RT (0x03 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RES (0x04 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RBCI (0x05 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_STARTB (0x06 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_STOPB (0x07 << 4) +# define HAL_MCFxxxx_UARTx_UCR_TC_MASK (0x03 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_SHIFT 2 +# define HAL_MCFxxxx_UARTx_UCR_TC_NOP (0x00 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_TE (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_TD (0x02 << 2) +# define HAL_MCFxxxx_UARTx_UCR_RC_MASK (0x03 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_SHIFT 0 +# define HAL_MCFxxxx_UARTx_UCR_RC_NOP (0x00 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_RE (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_RD (0x02 << 0) + +# define HAL_MCFxxxx_UARTx_UIPCR_COS (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UIPCR_CTS (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UACR_IEC (0x01 << 0) + +// ABC, RXFIFO, TXFIFO and RXFTO are not always available +# define HAL_MCFxxxx_UARTx_UISR_COS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UISR_DB (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UISR_FFUL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UISR_RXRDY (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UISR_TXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UIMR_COS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UIMR_DB (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UIMR_FFUL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UIMR_RXRDY (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UIMR_TXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UIP_CTS (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UOP_RTS (0x01 << 0) + +// The baud rate depends on the system clock. There is no fractional +// precision register. +# define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \ + CYG_MACRO_START \ + cyg_uint8 _udu_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) >> 8)); \ + cyg_uint8 _udl_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) & 0x00FF)); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \ + CYG_MACRO_END + +#endif // HAL_MCFxxxx_HAS_MCF5282_UART + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_I2C +// I2C +// Five 8-bit registers: address, frequency divider, control, status, data +# define HAL_MCFxxxx_I2Cx_ADR 0x0000 +# define HAL_MCFxxxx_I2Cx_FDR 0x0004 +# define HAL_MCFxxxx_I2Cx_CR 0x0008 +# define HAL_MCFxxxx_I2Cx_SR 0x000C +# define HAL_MCFxxxx_I2Cx_DR 0x0010 + +# define HAL_MCFxxxx_I2Cx_CR_IEN (0x01 << 7) +# define HAL_MCFxxxx_I2Cx_CR_IIEN (0x01 << 6) +# define HAL_MCFxxxx_I2Cx_CR_MSTA (0x01 << 5) +# define HAL_MCFxxxx_I2Cx_CR_MTX (0x01 << 4) +# define HAL_MCFxxxx_I2Cx_CR_TXAK (0x01 << 3) +# define HAL_MCFxxxx_I2Cx_CR_RSTA (0x01 << 2) + +# define HAL_MCFxxxx_I2Cx_SR_ICF (0x01 << 7) +# define HAL_MCFxxxx_I2Cx_SR_IAAS (0x01 << 6) +# define HAL_MCFxxxx_I2Cx_SR_IBB (0x01 << 5) +# define HAL_MCFxxxx_I2Cx_SR_IAL (0x01 << 4) +# define HAL_MCFxxxx_I2Cx_SR_SRW (0x01 << 2) +# define HAL_MCFxxxx_I2Cx_SR_IIF (0x01 << 1) +# define HAL_MCFxxxx_I2Cx_SR_RXAK (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_I2C + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CAN +// FLEXCAN +// 16-bit module configuration register +# define HAL_MCFxxxx_CANx_MCR 0x0000 +// Three 8-bit control registers and an 8-bit prescaler +# define HAL_MCFxxxx_CANx_CTRL0 0x0006 +# define HAL_MCFxxxx_CANx_CTRL1 0x0007 +# define HAL_MCFxxxx_CANx_PRESDIV 0x0008 +# define HAL_MCFxxxx_CANx_CTRL2 0x0009 +// 16-bit free runxxng timer +# define HAL_MCFxxxx_CANx_TIMER 0x000A +// 32-bit global and buffer mask registers +# define HAL_MCFxxxx_CANx_RXGMASK 0x0010 +# define HAL_MCFxxxx_CANx_RX14MASK 0x0014 +# define HAL_MCFxxxx_CANx_RX15MASK 0x0018 +// 16-bit error and status +# define HAL_MCFxxxx_CANx_ESTAT 0x0020 +// 16-bit interrup mask and flags +# define HAL_MCFxxxx_CANx_IMASK 0x0022 +# define HAL_MCFxxxx_CANx_IFLAG 0x0024 +// Two 8-bit error counters +# define HAL_MCFxxxx_CANx_RXECTR 0x0026 +# define HAL_MCFxxxx_CANx_TXECTR 0x0027 +// 16 32-bit message buffers start here +# define HAL_MCFxxxx_CANx_BUF 0x0080 + +# define HAL_MCFxxxx_CANx_MCR_STOP (0x01 << 15) +# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 14) +# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 12) +# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 11) +# define HAL_MCFxxxx_CANx_MCR_WAKEMSK (0x01 << 10) +# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 9) +# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 8) +# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 7) +# define HAL_MCFxxxx_CANx_MCR_SELFWAKE (0x01 << 6) +# define HAL_MCFxxxx_CANx_MCR_APS (0x01 << 5) +# define HAL_MCFxxxx_CANx_MCR_STOPACK (0x01 << 4) + +# define HAL_MCFxxxx_CANx_CTRL0_BOFFMSK (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL0_ERRMASK (0x01 << 6) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE (0x01 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_0_DOMINANT (0x00 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_1_DOMINANT (0x01 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_MASK (0x03 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_SHIFT 0 +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_0_DOMINANT (0x00 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_1_DOMINANT (0x01 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_OPEN_0_DOMINANT (0x02 << 0) + +# define HAL_MCFxxxx_CANx_CTRL1_SAMP (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL1_TSYNC (0x01 << 5) +# define HAL_MCFxxxx_CANx_CTRL1_LBUF (0x01 << 4) +# define HAL_MCFxxxx_CANx_CTRL1_LOM (0x01 << 3) +# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_SHIFT 0 + +# define HAL_MCFxxxx_CANx_CTRL2_RJW_MASK (0x03 << 6) +# define HAL_MCFxxxx_CANx_CTRL2_RJW_SHIFT 6 +# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_MASK (0x07 << 3) +# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_SHIFT 3 +# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_MASK (0x03 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_SHIFT 14 +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_NONE (0x00 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_DOMINANT_RECESSIVE (0x01 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_RECESSIVE_DOMINANT (0x02 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_ACKERR (0x01 << 13) +# define HAL_MCFxxxx_CANx_ESTAT_CRCERR (0x01 << 12) +# define HAL_MCFxxxx_CANx_ESTAT_FORMERR (0x01 << 11) +# define HAL_MCFxxxx_CANx_ESTAT_STUFFERR (0x01 << 10) +# define HAL_MCFxxxx_CANx_ESTAT_TXWARN (0x01 << 9) +# define HAL_MCFxxxx_CANx_ESTAT_RXWARN (0x01 << 8) +# define HAL_MCFxxxx_CANx_ESTAT_IDLE (0x01 << 7) +# define HAL_MCFxxxx_CANx_ESTAT_TX_RX (0x01 << 6) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_MASK (0x03 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_SHIFT 4 +# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_ACTIVE (0x00 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_PASSIVE (0x01 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_BOFFINT (0x01 << 2) +# define HAL_MCFxxxx_CANx_ESTAT_ERRINT (0x01 << 1) +# define HAL_MCFxxxx_CANx_ESTAT_WAKEINT (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_CAN + +// Some ColdFire processors have a variation of the CAN device where all +// the registers are 32-bit. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_CAN_32BIT_REGS +# define HAL_MCFxxxx_CANx_MCR 0x0000 +# define HAL_MCFxxxx_CANx_CTRL 0x0004 +# define HAL_MCFxxxx_CANx_TIMER 0x0008 +# define HAL_MCFxxxx_CANx_RXGMASK 0x0010 +# define HAL_MCFxxxx_CANx_RX14MASK 0x0014 +# define HAL_MCFxxxx_CANx_RX15MASK 0x0018 +# define HAL_MCFxxxx_CANx_ERRCNT 0x001C +# define HAL_MCFxxxx_CANx_ERRSTAT 0x0020 +# define HAL_MCFxxxx_CANx_IMASK 0x0028 +# define HAL_MCFxxxx_CANx_IFLAG 0x0030 +# define HAL_MCFxxxx_CANx_BUF 0x0080 + +# define HAL_MCFxxxx_CANx_MCR_MDIS (0x01 << 31) +# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 30) +# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 28) +# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 27) +# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 25) +# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 24) +# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 23) +# define HAL_MCFxxxx_CANx_MCR_LPMACK (0x01 << 20) +# define HAL_MCFxxxx_CANx_MCR_MAXMB_MASK (0x0F << 0) +# define HAL_MCFxxxx_CANx_MCR_MAXMB_SHIFT 0 + +# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_MASK (0x00FF << 24) +# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_SHIFT 24 +# define HAL_MCFxxxx_CANx_CTRL_RJW_MASK (0x03 << 22) +# define HAL_MCFxxxx_CANx_CTRL_RJW_SHIFT 22 +# define HAL_MCFxxxx_CANx_CTRL_PSEG1_MASK (0x07 << 19) +# define HAL_MCFxxxx_CANx_CTRL_PSEG1_SHIFT 19 +# define HAL_MCFxxxx_CANx_CTRL_PSEG2_MASK (0x07 << 16) +# define HAL_MCFxxxx_CANx_CTRL_PSEG2_SHIFT 16 +# define HAL_MCFxxxx_CANx_CTRL_BOFFMSK (0x01 << 15) +# define HAL_MCFxxxx_CANx_CTRL_ERRMSK (0x01 << 14) +# define HAL_MCFxxxx_CANx_CTRL_CLKSRC (0x01 << 13) +# define HAL_MCFxxxx_CANx_CTRL_LPB (0x01 << 12) +# define HAL_MCFxxxx_CANx_CTRL_SMP (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL_BOFFREC (0x01 << 6) +# define HAL_MCFxxxx_CANx_CTRL_TSYN (0x01 << 5) +# define HAL_MCFxxxx_CANx_CTRL_LBUF (0x01 << 4) +# define HAL_MCFxxxx_CANx_CTRL_LOM (0x01 << 3) +# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_MASK (0x00FF << 8) +# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_SHIFT 8 +# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_MASK (0x00FF << 0) +# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ERRSTAT_BIT1ERR (0x01 << 15) +# define HAL_MCFxxxx_CANx_ERRSTAT_BIT0ERR (0x01 << 14) +# define HAL_MCFxxxx_CANx_ERRSTAT_ACKERR (0x01 << 13) +# define HAL_MCFxxxx_CANx_ERRSTAT_CRCERR (0x01 << 12) +# define HAL_MCFxxxx_CANx_ERRSTAT_FRMERR (0x01 << 11) +# define HAL_MCFxxxx_CANx_ERRSTAT_STFERR (0x01 << 10) +# define HAL_MCFxxxx_CANx_ERRSTAT_TXWRN (0x01 << 9) +# define HAL_MCFxxxx_CANx_ERRSTAT_RXWRN (0x01 << 8) +# define HAL_MCFxxxx_CANx_ERRSTAT_IDLE (0x01 << 7) +# define HAL_MCFxxxx_CANx_ERRSTAT_TXRX (0x01 << 6) +# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_MASK (0x03 << 4) +# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_SHIFT 4 +# define HAL_MCFxxxx_CANx_ERRSTAT_BOFFINT (0x01 << 2) +# define HAL_MCFxxxx_CANx_ERRSTAT_ERRINT (0x01 << 1) +#endif + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_QADC +// Queued analog-to-digital converter + +// Configuration register, 16 bits +# define HAL_MCFxxxx_QADC_QADCMCR 0x0000 +// Test register, 16 bits. This is only usable in factory test mode +# define HAL_MCFxxxx_QADC_QADCTEST 0x0002 +// Two port data registers, 8 bits each +# define HAL_MCFxxxx_QADC_PORTQA 0x0006 +# define HAL_MCFxxxx_QADC_PORTQB 0x0007 +// Two port direction registers, 8 bits each +# define HAL_MCFxxxx_QADC_DDRQA 0x0008 +# define HAL_MCFxxxx_QADC_DDRQB 0x0009 +// Three control registers, 16 bits each +# define HAL_MCFxxxx_QADC_QACR0 0x000A +# define HAL_MCFxxxx_QADC_QACR1 0x000C +# define HAL_MCFxxxx_QADC_QACR2 0x000E +// Two status registers, 16 bits each +# define HAL_MCFxxxx_QADC_QASR0 0x0010 +# define HAL_MCFxxxx_QADC_QASR1 0x0012 +// Command word table, 64 entries * 16 bits each +# define HAL_MCFxxxx_QADC_CCW 0x0200 +// Right-justified unsigned results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_RJURR 0x0280 +// Left-justified signed results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_LJSRR 0x0300 +// Left-justified unsigned results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_LJURR 0x0380 + +# define HAL_MCFxxxx_QADC_QADCMCR_QSTOP (0x01 << 15) +# define HAL_MCFxxxx_QADC_QADCMCR_QDBG (0x01 << 14) +# define HAL_MCFxxxx_QADC_QADCMCR_QSUPV (0x01 << 7) + +// The port data and direction registers just provide control +// over four signals apiece. + +# define HAL_MCFxxxx_QADC_QACR0_MUX (0x01 << 15) +# define HAL_MCFxxxx_QADC_QACR0_TRG (0x01 << 14) +# define HAL_MCFxxxx_QADC_QACR0_QPR_MASK (0x7F << 0) +# define HAL_MCFxxxx_QADC_QACR0_QPR_SHIFT 0 +// The actual prescaler is (2 * (QPR+1)), except for a QPR value +// of 0 which gives a prescaler of 4. + +// QACR1 and QACR2 control queues 1 and 2 respectively +# define HAL_MCFxxxx_QADC_QACRn_CIE (0x01 << 15) +# define HAL_MCFxxxx_QADC_QACRn_PIE (0x01 << 14) +# define HAL_MCFxxxx_QADC_QACRn_SSE (0x01 << 13) +# define HAL_MCFxxxx_QADC_QACRn_MQ_MASK (0x1F << 8) +# define HAL_MCFxxxx_QADC_QACRn_MQ_SHIFT 8 +// There are 32 different modes, see the manual for details. + +// QACR2 has some additional bits to support resume operations +# define HAL_MCFxxxx_QADC_QACR2_RESUME (0x01 << 7) +# define HAL_MCFxxxx_QADC_QACR2_BQ_MASK (0x7F << 0) +# define HAL_MCFxxxx_QADC_QACR2_BQ_SHIFT 0 + +# define HAL_MCFxxxx_QADC_QASR0_CF1 (0x01 << 15) +# define HAL_MCFxxxx_QADC_QASR0_PF1 (0x01 << 14) +# define HAL_MCFxxxx_QADC_QASR0_CF2 (0x01 << 13) +# define HAL_MCFxxxx_QADC_QASR0_PF2 (0x01 << 12) +# define HAL_MCFxxxx_QADC_QASR0_TOR1 (0x01 << 11) +# define HAL_MCFxxxx_QADC_QASR0_TOR2 (0x01 << 10) +# define HAL_MCFxxxx_QADC_QASR0_QS_MASK (0x0F << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_SHIFT 6 +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_IDLE (0x00 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PAUSED (0x01 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_ACTIVE (0x02 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PENDING (0x03 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_IDLE (0x04 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PAUSED (0x05 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_ACTIVE (0x06 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PENDING (0x07 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_IDLE (0x08 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PAUSED (0x09 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_SUSPENDED (0x0A << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PENDING (0x0B << 6) +# define HAL_MCFxxxx_QADC_QASR0_CWP_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_QASR0_CWP_SHIFT 0 + +# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_MASK (0x3F << 8) +# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_SHIFT 8 +# define HAL_MCFxxxx_QADC_QASR1_CWPQ_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_QASR1_CWPQ_SHIFT 0 + +# define HAL_MCFxxxx_QADC_CCW_PAUSE (0x01 << 9) +# define HAL_MCFxxxx_QADC_CCW_BYP (0x01 << 8) +# define HAL_MCFxxxx_QADC_CCW_IST_MASK (0x03 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_SHIFT 6 +# define HAL_MCFxxxx_QADC_CCW_IST_2 (0x00 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_4 (0x01 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_8 (0x02 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_16 (0x03 << 6) +# define HAL_MCFxxxx_QADC_CCW_CHAN_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_CCW_CHAN_SHIFT 0 + +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN0 0 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN1 1 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN2 2 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN3 3 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN52 52 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN53 53 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN55 55 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN56 56 +# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG1 55 +# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG2 56 +# define HAL_MCFxxxx_QADC_CCW_CHAN_LOWREF 60 +# define HAL_MCFxxxx_QADC_CCW_CHAN_HIGHREF 61 +# define HAL_MCFxxxx_QADC_CCW_CHAN_MIDREF 62 +# define HAL_MCFxxxx_QADC_CCW_CHAN_EOQ 63 + +#endif // HAL_MCFxxxx_HAS_MCF5282_QADC + +// ---------------------------------------------------------------------------- +// Pulse width modulation unit. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_PWM +# define HAL_MCFxxxx_PWMx_PWME 0x0000 +# define HAL_MCFxxxx_PWMx_PWMPOL 0x0001 +# define HAL_MCFxxxx_PWMx_PWMCLK 0x0002 +# define HAL_MCFxxxx_PWMx_PWMPRCLK 0x0003 +# define HAL_MCFxxxx_PWMx_PWMCAE 0x0004 +# define HAL_MCFxxxx_PWMx_PWMCTL 0x0005 +# define HAL_MCFxxxx_PWMx_PWMSCLA 0x0008 +# define HAL_MCFxxxx_PWMx_PWMSCLB 0x0009 +# define HAL_MCFxxxx_PWMx_PWMCNT0 0x000C +# define HAL_MCFxxxx_PWMx_PWMCNT1 0x000D +# define HAL_MCFxxxx_PWMx_PWMCNT2 0x000E +# define HAL_MCFxxxx_PWMx_PWMCNT3 0x000F +# define HAL_MCFxxxx_PWMx_PWMCNT4 0x0010 +# define HAL_MCFxxxx_PWMx_PWMCNT5 0x0011 +# define HAL_MCFxxxx_PWMx_PWMCNT6 0x0012 +# define HAL_MCFxxxx_PWMx_PWMCNT7 0x0013 +# define HAL_MCFxxxx_PWMx_PWMPER0 0x0014 +# define HAL_MCFxxxx_PWMx_PWMPER1 0x0015 +# define HAL_MCFxxxx_PWMx_PWMPER2 0x0016 +# define HAL_MCFxxxx_PWMx_PWMPER3 0x0017 +# define HAL_MCFxxxx_PWMx_PWMPER4 0x0018 +# define HAL_MCFxxxx_PWMx_PWMPER5 0x0019 +# define HAL_MCFxxxx_PWMx_PWMPER6 0x001A +# define HAL_MCFxxxx_PWMx_PWMPER7 0x001B +# define HAL_MCFxxxx_PWMx_PWMDTY0 0x001C +# define HAL_MCFxxxx_PWMx_PWMDTY1 0x001D +# define HAL_MCFxxxx_PWMx_PWMDTY2 0x001E +# define HAL_MCFxxxx_PWMx_PWMDTY3 0x001F +# define HAL_MCFxxxx_PWMx_PWMDTY4 0x0020 +# define HAL_MCFxxxx_PWMx_PWMDTY5 0x0021 +# define HAL_MCFxxxx_PWMx_PWMDTY6 0x0022 +# define HAL_MCFxxxx_PWMx_PWMDTY7 0x0023 +# define HAL_MCFxxxx_PWMx_PWMSDN 0x0024 + +# define HAL_MCFxxxx_PWMx_PWME_PWME7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWME_PWME5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWME_PWME3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWME_PWME1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_MASK (0x07 << 4) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_SHIFT 4 +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_MASK (0x07 << 0) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_SHIFT 0 +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON67 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON45 (0x01 << 6) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON23 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON01 (0x01 << 4) +# define HAL_MCFxxxx_PWMx_PWMCTL_PSWAI (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCTL_PFRZ (0x01 << 2) +# define HAL_MCFxxxx_PWMx_PWMSDN_IF (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMSDN_IE (0x01 << 6) +# define HAL_MCFxxxx_PWMx_PWMSDN_RESTART (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMSDN_LVL (0x01 << 4) +# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IN (0x01 << 2) +# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IL (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMSDN_SDNEN (0x01 << 0) +#endif // HAS_MCFxxxx_PWM + +// ---------------------------------------------------------------------------- +// Real-time clock. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RTC +# define HAL_MCFxxxx_RTC_HOURMIN 0x00 +# define HAL_MCFxxxx_RTC_SECONDS 0x04 +# define HAL_MCFxxxx_RTC_ALRM_HM 0x08 +# define HAL_MCFxxxx_RTC_ALRM_SEC 0x0C +# define HAL_MCFxxxx_RTC_CR 0x10 +# define HAL_MCFxxxx_RTC_ISR 0x14 +# define HAL_MCFxxxx_RTC_IER 0x18 +# define HAL_MCFxxxx_RTC_STPWCH 0x1C +# define HAL_MCFxxxx_RTC_DAYS 0x20 +# define HAL_MCFxxxx_RTC_ALRM_DAY 0x24 + +# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_MASK (0x1F << 8) +# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_SHIFT 8 +# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_SHIFT 0 +# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_MASK (0x1F << 8) +# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_SHIFT 8 +# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_SEC_SECONDS_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_ALARM_SEC_SECONDS_SHIFT 0 +# define HAL_MCFxxxx_RTC_CR_EN (0x01 << 7) +# define HAL_MCFxxxx_RTC_CR_XTL_MASK (0x03 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_SHIFT 5 +# define HAL_MCFxxxx_RTC_CR_XTL_32768 (0x00 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_32000 (0x01 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_38400 (0x02 << 5) +# define HAL_MCFxxxx_RTC_CR_SWR (0x01 << 0) +# define HAL_MCFxxxx_RTC_ISR_SAM7 (0x01 << 15) +# define HAL_MCFxxxx_RTC_ISR_SAM6 (0x01 << 14) +# define HAL_MCFxxxx_RTC_ISR_SAM5 (0x01 << 13) +# define HAL_MCFxxxx_RTC_ISR_SAM4 (0x01 << 12) +# define HAL_MCFxxxx_RTC_ISR_SAM3 (0x01 << 11) +# define HAL_MCFxxxx_RTC_ISR_SAM2 (0x01 << 10) +# define HAL_MCFxxxx_RTC_ISR_SAM1 (0x01 << 9) +# define HAL_MCFxxxx_RTC_ISR_SAM0 (0x01 << 8) +# define HAL_MCFxxxx_RTC_ISR_2HZ (0x01 << 7) +# define HAL_MCFxxxx_RTC_ISR_HR (0x01 << 5) +# define HAL_MCFxxxx_RTC_ISR_1HZ (0x01 << 4) +# define HAL_MCFxxxx_RTC_ISR_DAY (0x01 << 3) +# define HAL_MCFxxxx_RTC_ISR_ALM (0x01 << 2) +# define HAL_MCFxxxx_RTC_ISR_MIN (0x01 << 1) +# define HAL_MCFxxxx_RTC_ISR_SW (0x01 << 0) +# define HAL_MCFxxxx_RTC_IER_SAM7 (0x01 << 15) +# define HAL_MCFxxxx_RTC_IER_SAM6 (0x01 << 14) +# define HAL_MCFxxxx_RTC_IER_SAM5 (0x01 << 13) +# define HAL_MCFxxxx_RTC_IER_SAM4 (0x01 << 12) +# define HAL_MCFxxxx_RTC_IER_SAM3 (0x01 << 11) +# define HAL_MCFxxxx_RTC_IER_SAM2 (0x01 << 10) +# define HAL_MCFxxxx_RTC_IER_SAM1 (0x01 << 9) +# define HAL_MCFxxxx_RTC_IER_SAM0 (0x01 << 8) +# define HAL_MCFxxxx_RTC_IER_2HZ (0x01 << 7) +# define HAL_MCFxxxx_RTC_IER_HR (0x01 << 5) +# define HAL_MCFxxxx_RTC_IER_1HZ (0x01 << 4) +# define HAL_MCFxxxx_RTC_IER_DAY (0x01 << 3) +# define HAL_MCFxxxx_RTC_IER_ALM (0x01 << 2) +# define HAL_MCFxxxx_RTC_IER_MIN (0x01 << 1) +# define HAL_MCFxxxx_RTC_IER_SW (0x01 << 0) +# define HAL_MCFxxxx_RTC_STPWCH_CNT_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_STPWCH_CNT_SHIFT 0 +# define HAL_MCFxxxx_RTC_DAYS_DAYS_MASK (0x00FFFF << 0) +# define HAL_MCFxxxx_RTC_DAYS_DAYS_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_MASK (0x00FFFF << 0) +# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_SHIFT 0 +#endif // HAS_MCFxxxx_RTC + +// ---------------------------------------------------------------------------- +// Message digest hardware +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_MDHA +# define HAL_MCFxxxx_MDHA_MR 0x0000 +# define HAL_MCFxxxx_MDHA_CR 0x0004 +# define HAL_MCFxxxx_MDHA_CMR 0x0008 +# define HAL_MCFxxxx_MDHA_SR 0x000C +# define HAL_MCFxxxx_MDHA_ISR 0x0010 +# define HAL_MCFxxxx_MDHA_IMR 0x0014 +# define HAL_MCFxxxx_MDHA_DSR 0x001C +# define HAL_MCFxxxx_MDHA_MIN 0x0020 +# define HAL_MCFxxxx_MDHA_A0 0x0030 +# define HAL_MCFxxxx_MDHA_B0 0x0034 +# define HAL_MCFxxxx_MDHA_C0 0x0038 +# define HAL_MCFxxxx_MDHA_D0 0x003C +# define HAL_MCFxxxx_MDHA_E0 0x0040 +# define HAL_MCFxxxx_MDHA_MDS 0x0044 +# define HAL_MCFxxxx_MDHA_A1 0x0070 +# define HAL_MCFxxxx_MDHA_B1 0x0074 +# define HAL_MCFxxxx_MDHA_C1 0x0078 +# define HAL_MCFxxxx_MDHA_D1 0x007C +# define HAL_MCFxxxx_MDHA_E1 0x0080 + +# define HAL_MCFxxxx_MDHA_MR_SSL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_MR_MACFULL (0x01 << 9) +# define HAL_MCFxxxx_MDHA_MR_SWAP (0x01 << 8) +# define HAL_MCFxxxx_MDHA_MR_OPAD (0x01 << 7) +# define HAL_MCFxxxx_MDHA_MR_IPAD (0x01 << 6) +# define HAL_MCFxxxx_MDHA_MR_INIT (0x01 << 5) +# define HAL_MCFxxxx_MDHA_MR_MAC_MASK (0x03 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_SHIFT 3 +# define HAL_MCFxxxx_MDHA_MR_MAC_NONE (0x00 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_HMAC (0x01 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_EHMAC (0x02 << 3) +# define HAL_MCFxxxx_MDHA_MR_PDATA (0x01 << 2) +# define HAL_MCFxxxx_MDHA_MR_ALG (0x01 << 0) +# define HAL_MCFxxxx_MDHA_CR_DMAL_MASK (0x1F << 16) +# define HAL_MCFxxxx_MDHA_CR_DMAL_SHIFT 16 +# define HAL_MCFxxxx_MDHA_CR_END (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CR_DMA (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CR_IE (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CMR_GO (0x01 << 3) +# define HAL_MCFxxxx_MDHA_CMR_CI (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CMR_RI (0x01 << 1) +# define HAL_MCFxxxx_MDHA_CMR_SWR (0x01 << 0) +# define HAL_MCFxxxx_MDHA_SR_IFL_MASK (0x00FF << 16) +# define HAL_MCFxxxx_MDHA_SR_IFL_SHIFT 16 +# define HAL_MCFxxxx_MDHA_SR_APD_MASK (0x07 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_SHIFT 13 +# define HAL_MCFxxxx_MDHA_SR_APD_STANDARD (0x00 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_PAD_LAST_WORD (0x01 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_ADD_A_WORD (0x02 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_LAST_HASH (0x03 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_STALL_STATE (0x04 << 13) +# define HAL_MCFxxxx_MDHA_SR_FS_MASK (0x07 << 8) +# define HAL_MCFxxxx_MDHA_SR_FS_SHIFT 8 +# define HAL_MCFxxxx_MDHA_SR_GNW (0x01 << 7) +# define HAL_MCFxxxx_MDHA_SR_HSH (0x01 << 6) +# define HAL_MCFxxxx_MDHA_SR_BUSY (0x01 << 4) +# define HAL_MCFxxxx_MDHA_SR_RD (0x01 << 3) +# define HAL_MCFxxxx_MDHA_SR_ERR (0x01 << 2) +# define HAL_MCFxxxx_MDHA_SR_DONE (0x01 << 1) +# define HAL_MCFxxxx_MDHA_SR_INT (0x01 << 0) +# define HAL_MCFxxxx_MDHA_ISR_DRL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_ISR_GTDS (0x01 << 9) +# define HAL_MCFxxxx_MDHA_ISR_ERE (0x01 << 8) +# define HAL_MCFxxxx_MDHA_ISR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_MDHA_ISR_DSE (0x01 << 5) +# define HAL_MCFxxxx_MDHA_ISR_IME (0x01 << 4) +# define HAL_MCFxxxx_MDHA_ISR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_MDHA_ISR_IFO (0x01 << 0) +# define HAL_MCFxxxx_MDHA_IMR_DRL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_IMR_GTDS (0x01 << 9) +# define HAL_MCFxxxx_MDHA_IMR_ERE (0x01 << 8) +# define HAL_MCFxxxx_MDHA_IMR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_MDHA_IMR_DSE (0x01 << 5) +# define HAL_MCFxxxx_MDHA_IMR_IME (0x01 << 4) +# define HAL_MCFxxxx_MDHA_IMR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_MDHA_IMR_IFO (0x01 << 0) +#endif // HAS_MCFxxxx_MDHA + +// ---------------------------------------------------------------------------- +// Random number generation +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RNG +# define HAL_MCFxxxx_RNG_CR 0x00000000 +# define HAL_MCFxxxx_RNG_SR 0x00000004 +# define HAL_MCFxxxx_RNG_ER 0x00000008 +# define HAL_MCFxxxx_RNG_OUT 0x0000000C + +# define HAL_MCFxxxx_RNG_CR_CI (0x01 << 3) +# define HAL_MCFxxxx_RNG_CR_IM (0x01 << 2) +# define HAL_MCFxxxx_RNG_CR_HA (0x01 << 1) +# define HAL_MCFxxxx_RNG_CR_GO (0x01 << 0) +# define HAL_MCFxxxx_RNG_SR_OFS_MASK (0x00FF << 16) +# define HAL_MCFxxxx_RNG_SR_OFS_SHIFT 16 +# define HAL_MCFxxxx_RNG_SR_OFL_MASK (0x00FF << 8) +# define HAL_MCFxxxx_RNG_SR_OFL_SHIFT 8 +# define HAL_MCFxxxx_RNG_SR_EI (0x01 << 3) +# define HAL_MCFxxxx_RNG_SR_FUF (0x01 << 2) +# define HAL_MCFxxxx_RNG_SR_LRS (0x01 << 1) +# define HAL_MCFxxxx_RNG_SR_SR (0x01 << 0) +#endif // HAS_MCFxxxx_RNG + +// ---------------------------------------------------------------------------- +// Symmetric key hardware +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_SKHA + +# define HAL_MCFxxxx_SKHA_MR 0x00000000 +# define HAL_MCFxxxx_SKHA_CR 0x00000004 +# define HAL_MCFxxxx_SKHA_CMR 0x00000008 +# define HAL_MCFxxxx_SKHA_SR 0x0000000C +# define HAL_MCFxxxx_SKHA_ESR 0x00000010 +# define HAL_MCFxxxx_SKHA_EMR 0x00000014 +# define HAL_MCFxxxx_SKHA_KSR 0x00000018 +# define HAL_MCFxxxx_SKHA_DSR 0x0000001C +# define HAL_MCFxxxx_SKHA_IN 0x00000020 +# define HAL_MCFxxxx_SKHA_OUT 0x00000024 +# define HAL_MCFxxxx_SKHA_KDR1 0x00000030 +# define HAL_MCFxxxx_SKHA_KDR2 0x00000034 +# define HAL_MCFxxxx_SKHA_KDR3 0x00000038 +# define HAL_MCFxxxx_SKHA_KDR4 0x0000003C +# define HAL_MCFxxxx_SKHA_KDR5 0x00000040 +# define HAL_MCFxxxx_SKHA_KDR6 0x00000044 +# define HAL_MCFxxxx_SKHA_C1 0x00000070 +# define HAL_MCFxxxx_SKHA_C2 0x00000074 +# define HAL_MCFxxxx_SKHA_C3 0x00000078 +# define HAL_MCFxxxx_SKHA_C4 0x0000007C +# define HAL_MCFxxxx_SKHA_C5 0x00000080 +# define HAL_MCFxxxx_SKHA_C6 0x00000084 +# define HAL_MCFxxxx_SKHA_C7 0x00000088 +# define HAL_MCFxxxx_SKHA_C8 0x0000008C +# define HAL_MCFxxxx_SKHA_C9 0x00000090 +# define HAL_MCFxxxx_SKHA_C10 0x00000094 +# define HAL_MCFxxxx_SKHA_C11 0x00000098 + +# define HAL_MCFxxxx_SKHA_MR_CTRM_MASK (0x0F << 9) +# define HAL_MCFxxxx_SKHA_MR_CTRM_SHIFT 9 +# define HAL_MCFxxxx_SKHA_MR_DKP (0x01 << 8) +# define HAL_MCFxxxx_SKHA_MR_CM_MASK (0x03 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_SHIFT 3 +# define HAL_MCFxxxx_SKHA_MR_CM_ECB (0x00 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_CBC (0x01 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_CTR (0x03 << 3) +# define HAL_MCFxxxx_SKHA_MR_DIR (0x01 << 2) +# define HAL_MCFxxxx_SKHA_MR_ALG_MASK (0x03 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_SHIFT 0 +# define HAL_MCFxxxx_SKHA_MR_ALG_AES (0x00 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_DES (0x01 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_3DES (0x02 << 0) +# define HAL_MCFxxxx_SKHA_CR_ODMAL_MASK (0x3F << 24) +# define HAL_MCFxxxx_SKHA_CR_ODMAL_SHIFT 24 +# define HAL_MCFxxxx_SKHA_CR_IDMAL_MASK (0x3F << 16) +# define HAL_MCFxxxx_SKHA_CR_IDMAL_SHIFT 16 +# define HAL_MCFxxxx_SKHA_CR_END (0x01 << 3) +# define HAL_MCFxxxx_SKHA_CR_ODMA (0x01 << 2) +# define HAL_MCFxxxx_SKHA_CR_IDMA (0x01 << 1) +# define HAL_MCFxxxx_SKHA_CR_IE (0x01 << 0) +# define HAL_MCFxxxx_SKHA_CMR_GO (0x01 << 3) +# define HAL_MCFxxxx_SKHA_CMR_CI (0x01 << 2) +# define HAL_MCFxxxx_SKHA_CMR_RI (0x01 << 1) +# define HAL_MCFxxxx_SKHA_CMR_SWR (0x01 << 0) +# define HAL_MCFxxxx_SKHA_SR_OFL_MASK (0x00FF << 24) +# define HAL_MCFxxxx_SKHA_SR_OFL_SHIFT 24 +# define HAL_MCFxxxx_SKHA_SR_IFL_MASK (0x00FF << 16) +# define HAL_MCFxxxx_SKHA_SR_IFL_SHIFT 16 +# define HAL_MCFxxxx_SKHA_SR_BUSY (0x01 << 4) +# define HAL_MCFxxxx_SKHA_SR_RD (0x01 << 3) +# define HAL_MCFxxxx_SKHA_SR_ERR (0x01 << 2) +# define HAL_MCFxxxx_SKHA_SR_DONE (0x01 << 1) +# define HAL_MCFxxxx_SKHA_SR_INT (0x01 << 0) +# define HAL_MCFxxxx_SKHA_ESR_DRL (0x01 << 11) +# define HAL_MCFxxxx_SKHA_ESR_KRE (0x01 << 10) +# define HAL_MCFxxxx_SKHA_ESR_KPE (0x01 << 9) +# define HAL_MCFxxxx_SKHA_ESR_ERE (0x01 << 8) +# define HAL_MCFxxxx_SKHA_ESR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_SKHA_ESR_KSE (0x01 << 6) +# define HAL_MCFxxxx_SKHA_ESR_DSE (0x01 << 5) +# define HAL_MCFxxxx_SKHA_ESR_IME (0x01 << 4) +# define HAL_MCFxxxx_SKHA_ESR_NEOF (0x01 << 3) +# define HAL_MCFxxxx_SKHA_ESR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_SKHA_ESR_OFU (0x01 << 1) +# define HAL_MCFxxxx_SKHA_ESR_IFO (0x01 << 0) +# define HAL_MCFxxxx_SKHA_EMR_DRL (0x01 << 11) +# define HAL_MCFxxxx_SKHA_EMR_KRE (0x01 << 10) +# define HAL_MCFxxxx_SKHA_EMR_KPE (0x01 << 9) +# define HAL_MCFxxxx_SKHA_EMR_ERE (0x01 << 8) +# define HAL_MCFxxxx_SKHA_EMR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_SKHA_EMR_KSE (0x01 << 6) +# define HAL_MCFxxxx_SKHA_EMR_DSE (0x01 << 5) +# define HAL_MCFxxxx_SKHA_EMR_IME (0x01 << 4) +# define HAL_MCFxxxx_SKHA_EMR_NEOF (0x01 << 3) +# define HAL_MCFxxxx_SKHA_EMR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_SKHA_EMR_OFU (0x01 << 1) +# define HAL_MCFxxxx_SKHA_EMR_IFO (0x01 << 0) +#endif // HAS_MCFxxxx_SKHA + +// ---------------------------------------------------------------------------- +// Allow the processor-specific header to override some of the above, if +// necessary, or to extend the definitions. +#include <cyg/hal/proc_io.h> + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_IO_H
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/include/var_startup.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef _VAR_STARTUP_H -#define _VAR_STARTUP_H -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== - -#include <cyg/infra/cyg_type.h> - -// Include the processor-specific startup header. - -#include <cyg/hal/proc_startup.h> - -// Variant-specific reset vector initialization routine - -externC void var_reset(void); - -#endif // _VAR_STARTUP_H -
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/src/context.S +++ /dev/null @@ -1,105 +0,0 @@ -##============================================================================= -## -## context.S -## -## mcf52xx context switch code -## -##============================================================================= -#####ECOSGPLCOPYRIGHTBEGIN#### -## ------------------------------------------- -## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## -## eCos is free software; you can redistribute it and/or modify it under -## the terms of the GNU General Public License as published by the Free -## Software Foundation; either version 2 or (at your option) any later version. -## -## eCos is distributed in the hope that it will be useful, but WITHOUT ANY -## WARRANTY; without even the implied warranty of MERCHANTABILITY or -## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -## for more details. -## -## You should have received a copy of the GNU General Public License along -## with eCos; if not, write to the Free Software Foundation, Inc., -## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -## -## As a special exception, if other files instantiate templates or use macros -## or inline functions from this file, or you compile this file and link it -## with other works to produce a work based on this file, this file does not -## by itself cause the resulting work to be covered by the GNU General Public -## License. However the source code for this file must still be made available -## in accordance with section (3) of the GNU General Public License. -## -## This exception does not invalidate any other reasons why a work based on -## this file might be covered by the GNU General Public License. -## -## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -## at http://sources.redhat.com/ecos/ecos-license/ -## ------------------------------------------- -#####ECOSGPLCOPYRIGHTEND#### -##============================================================================= - -#include <pkgconf/hal.h> - -#------------------------------------------------------------------------------ -# function declaration macro - -#define FUNC_START(name) \ - .text; \ - .even; \ - .globl name; \ -name: - -#------------------------------------------------------------------------------ -# hal_thread_switch_context -# Switch thread contexts -# : 0(%sp) : return address -# : 4(%sp) : to - address of sp of next thread to execute -# : 8(%sp) : from - address of sp save location of current thread -# -# d0, d1, a0, a1 are ours to abuse. -# -# externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); - -FUNC_START(hal_thread_switch_context) - - move.l 4(%sp),%a0 /* Read the to and from from */ - move.l 8(%sp),%a1 /* parameters from the stack. */ - - lea -(6+5)*4(%sp),%sp /* Save all of the registers */ - movem.l %d2-%d7/%a2-%a6,(%sp) /* that the C calling */ - /* convention expects us to */ - /* preserve. */ - - move.l %sp,(%a1) /* Store this threads current */ - /* stack pointer to *from. */ - - move.l (%a0),%sp /* Load the stack pointer for */ - /* the next thread from *to. */ - - movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */ - lea (6+5)*4(%sp),%sp /* registers from the stack. */ - - rts /* Restore the PC. */ - -#------------------------------------------------------------------------------ -# hal_thread_load_context -# Load thread context -# : 4(%sp) : to - address of sp of next thread to execute -# -# d0, d1, a0, a1 are ours to abuse. - -FUNC_START(hal_thread_load_context) - - move.l 4(%sp),%a0 /* Read the to parameter from */ - move.l (%a0),%sp /* the stack and switch to that */ - /* stack pointer. */ - - movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */ - lea (6+5)*4(%sp),%sp /* registers from the stack. */ - - rts /* Restore the PC. */ - -##============================================================================= -##============================================================================= -
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/hal_diag.c @@ -0,0 +1,286 @@ +/*============================================================================= +// +// hal_diag.c +// +// ColdFire MCFxxxx HAL diagnostics support +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2004,2006,2007,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#ifdef CYGPKG_REDBOOT +# include <pkgconf/redboot.h> +#endif +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> + +// There are two main possibilities: +// 1) the platform uses the standard MCFxxxx diagnostics support, by +// enabling CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT, and +// the user has selected an available uart. +// 2) or the platform may provide its own diagnostics facilities. + +#if defined(CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT) + +// Output goes via one of the UARTs. hal_diag.h will have provided +// _HAL_MCFxxxx_DIAG_UART_BASE_ and _HAL_MCFxxxx_DIAG_UART_ISRVEC_. +// Optionally the platform HAL can provide an extra INIT macro. + +void +hal_mcfxxxx_diag_uart_init(cyg_uint8* base, cyg_uint32 baud) +{ +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS) || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + static int initialized; + if (initialized) { + return; + } + initialized = 1; +#endif + +#ifdef HAL_MCFxxxx_UART_DIAG_PLATFORM_INIT + HAL_MCFxxxx_UART_DIAG_PLATFORM_INIT(); +#endif + + // Various resets to get the UART in a known good state + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RMRP); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RR); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RT); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RES); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RBCI); + + // Assume that this code will only run during system startup and with + // interrupts disabled, so that imr1 and imr2 can be poked in succession. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UMR, HAL_MCFxxxx_UARTx_UMR1_PM_NO | HAL_MCFxxxx_UARTx_UMR1_BC_8); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UMR, HAL_MCFxxxx_UARTx_UMR2_CM_NORMAL | HAL_MCFxxxx_UARTx_UMR2_SB_1); + + // Assert RTS, just in case the other side is interested + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UOP1, HAL_MCFxxxx_UARTx_UOP_RTS); + + // No hardware flow control based on fifo contents, no interrupts for change-of-state + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UACR, 0); + + // The IMR is write-only, so it is going to be difficult to set or clear just the + // rxrdy bit. Instead leave the serial interrupt enabled here but mask/unmask it + // inside the interrupt controller. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UIMR, HAL_MCFxxxx_UARTx_UIMR_RXRDY); + + // Baud rate. Always use the internal prescaled CLKIN. The baud rate is + // determined by the platform. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCSR, HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN | HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN); + HAL_MCFxxxx_UARTx_SET_BAUD(base, baud); + + // Enable both RX and TX + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_TC_TE | HAL_MCFxxxx_UARTx_UCR_RC_RE); +} + +void +hal_mcfxxxx_diag_uart_putc(void* channel_data, char c) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + + do { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + } while (!(usr & HAL_MCFxxxx_UARTx_USR_TXRDY) ); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UTB, c); +} + +cyg_uint8 +hal_mcfxxxx_diag_uart_getc(void* channel_data) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr, data; + do { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + } while (!(usr & HAL_MCFxxxx_UARTx_USR_RXRDY)); + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + return data; +} + +// Additional routines needed in virtual vector configurations. +# if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +// State manipulated by the _control() function. Support for dynamic +// baud rates is optional. Some platforms may choose to provide this +// by implementing CYGSEM_REDBOOT_VARIABLE_BAUD_RATE +static int msec_timeout = 1; +static int irq_enabled = 0; +# ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE +static cyg_uint32 baud_rate = _HAL_MCFxxxx_DIAG_UART_BAUD_; +# endif + +static void +hal_mcfxxxx_diag_uart_write(void* channel_data, const cyg_uint8* buf, cyg_uint32 len) +{ + while (len-- > 0) { + hal_mcfxxxx_diag_uart_putc(channel_data, *buf++); + } +} + +static void +hal_mcfxxxx_diag_uart_read(void* channel_data, cyg_uint8* buf, cyg_uint32 len) +{ + while (len-- > 0) { + *buf++ = hal_mcfxxxx_diag_uart_getc(channel_data); + } +} + +static cyg_bool +hal_mcfxxxx_diag_uart_getc_timeout(void* channel_data, cyg_uint8* ch) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + cyg_uint8 data; + int delay_count = msec_timeout * 10; + + while (delay_count-- > 0) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + if (usr & HAL_MCFxxxx_UARTx_USR_RXRDY) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + *ch = data; + return 1; + } + HAL_DELAY_US(100); + } + return 0; +} + +static int +hal_mcfxxxx_diag_uart_isr(void* channel_data, int* ctrl_c, CYG_ADDRWORD isr_vector, CYG_ADDRWORD isr_data) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + cyg_uint8 data; + + *ctrl_c = 0; + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + if (usr & HAL_MCFxxxx_UARTx_USR_RXRDY) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + if (cyg_hal_is_break((char*)&data, 1)) { + *ctrl_c = 1; + } + } + return CYG_ISR_HANDLED; +} + +static int +hal_mcfxxxx_diag_uart_control(void* channel_data, __comm_control_cmd_t func, ...) +{ + int result = -1; + va_list args; + + va_start(args, func); + switch(func) { + case __COMMCTL_IRQ_ENABLE: + result = 0; + irq_enabled = 1; + HAL_INTERRUPT_UNMASK(_HAL_MCFxxxx_DIAG_UART_ISRVEC_); + break; + case __COMMCTL_IRQ_DISABLE: + result = irq_enabled; + irq_enabled = 0; + HAL_INTERRUPT_MASK(_HAL_MCFxxxx_DIAG_UART_ISRVEC_); + break; + case __COMMCTL_DBG_ISR_VECTOR: + result = _HAL_MCFxxxx_DIAG_UART_ISRVEC_; + break; + case __COMMCTL_SET_TIMEOUT: + result = msec_timeout; + msec_timeout = va_arg(args,cyg_uint32); + break; +#ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE + case __COMMCTL_GETBAUD: + result = baud_rate; + break; + case __COMMCTL_SETBAUD: + baud_rate = va_arg(args, cyg_uint32); + HAL_MCFxxxx_UARTx_SET_BAUD(_HAL_MCFxxxx_DIAG_UART_BASE_, baud_rate); + result = 0; + break; +#endif + default: + break; + } + + CYG_UNUSED_PARAM(void*, channel_data); + return result; +} + +void +cyg_hal_plf_comms_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + + hal_mcfxxxx_diag_uart_init((cyg_uint8*)_HAL_MCFxxxx_DIAG_UART_BASE_, CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD); + // For the diag channel we may want interrupts without explicitly installing + // an interrupt handler, so the priority has to be set manually. + HAL_INTERRUPT_SET_LEVEL(_HAL_MCFxxxx_DIAG_UART_ISRVEC_, CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI); + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, (void*)(_HAL_MCFxxxx_DIAG_UART_BASE_)); + CYGACC_COMM_IF_WRITE_SET(*comm, hal_mcfxxxx_diag_uart_write); + CYGACC_COMM_IF_READ_SET(*comm, hal_mcfxxxx_diag_uart_read); + CYGACC_COMM_IF_PUTC_SET(*comm, hal_mcfxxxx_diag_uart_putc); + CYGACC_COMM_IF_GETC_SET(*comm, hal_mcfxxxx_diag_uart_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, hal_mcfxxxx_diag_uart_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_mcfxxxx_diag_uart_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_mcfxxxx_diag_uart_getc_timeout); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} +# endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +#else +// The platform HAL must provide its own diagnostics routines. +#endif + +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx.c @@ -0,0 +1,121 @@ +/*============================================================================= +// +// mcfxxxx.c +// +// ColdFire MCFxxxx miscellaneous support +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2008-01-14 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> + +#ifdef CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER +// ---------------------------------------------------------------------------- +// Profiling support. This requires a hardware timer set to interrupt +// at a rate determined by application code. The interrupt handler +// should call __profile_hit() with a single argument, the interrupted +// PC. One of the PIT timers, determined by the processor or platform +// HAL is used to implement the profiling timer. +// +// Usually this would involve installing an ISR. However there is no +// easy way for an ISR to get hold of the interrupted PC. In some +// configurations the save state will be stored in hal_saved_interrupt_state, +// but not always. It might be possible to extract the PC from the stack, +// but that gets messy if a separate interrupt stack is used and would be +// vulnerable to changes in the architectural VSR. Instead a custom VSR +// is installed. + +extern void hal_mcfxxxx_profile_vsr(void); + +# include <cyg/profile/profile.h> + +int +hal_enable_profile_timer(int resolution) +{ + cyg_uint16 ticks; + + // Make sure the clock is not running but is otherwise initialized. + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR, + HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW | + HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF | + HAL_MCFxxxx_PITx_PCSR_RLD); + + // The resolution is a time interval in microseconds. The actual + // cpu clock frequency is determined by the platform. This is divided + // by 64, which means it may not be possible to get the exact resolution. + ticks = ((resolution * CYGHWR_HAL_SYSTEM_CLOCK_MHZ) / 64) - 1; + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PMR, ticks); + + // Convert back to microseconds. This may actually increase rounding + // errors for some arguments and platforms, but the result should + // still be accurate enough for practical purposes. + resolution = ((ticks + 1) * 64) / CYGHWR_HAL_SYSTEM_CLOCK_MHZ; + + // Set up the interrupt handler. This is usually a high-priority + // interrupt so that we can get profiling information for other + // interrupt sources. +#ifdef HAL_VSR_SET + HAL_VSR_SET(HAL_MCFxxxx_PROFILE_TIMER_VECTOR, &hal_mcfxxxx_profile_vsr, (cyg_uint32)0); +#endif + HAL_INTERRUPT_SET_LEVEL(HAL_MCFxxxx_PROFILE_TIMER_ISR, CYGNUM_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER_ISR_PRIORITY); + HAL_INTERRUPT_UNMASK(HAL_MCFxxxx_PROFILE_TIMER_ISR); + + // Now start the timer running. + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR, + HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW | + HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF | + HAL_MCFxxxx_PITx_PCSR_RLD | HAL_MCFxxxx_PITx_PCSR_EN); + + // Return the actual resolution. + return resolution; +} + +#endif // Profiling timer + +/* End of mcfxxxx.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx_asm.S @@ -0,0 +1,85 @@ +// #======================================================================== +// # +// # mcfxxxx_asm.S +// # +// # Miscellaneous assembler support functions for an mcfxxxx +// # +// #======================================================================== +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================ +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2008-01-14 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <cyg/hal/arch.inc> +#include <cyg/hal/var_io.h> + + .file "mcfxxxx_asm.S" + +#ifdef CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER + // See also hal_enable_profile_timer() in mcfxxxx.c + + // This VSR should call __profile_hit() with a single argument, + // the interrupted PC. The VSR has been installed as a + // high-priority interrupt source, so there is no need to worry + // about nested interrupts or an interrupt stack. + .extern __profile_hit + + FUNC_START(hal_mcfxxxx_profile_vsr) + // On entry sp[0] holds sr and sp[1] holds the pc. + // Save the caller-save integer registers. There are no floating + // point registers to worry about. Make space for the argument + // to __profile_hit() while we are at it. + sub.l #20, %sp + movem.l %d0-%d1/%a0-%a1, 4(%sp) + + // Now pick up the interrupted PC from its new offset and push it + // on the stack for __profile_hit(). + move.l 24(%sp),(%sp) + jbsr __profile_hit + + // The timer runs in restart mode, but the interrupt bit has to be reset. + move.l # (HAL_MCFxxxx_PITx_PCSR_PRE_64 + HAL_MCFxxxx_PITx_PCSR_OVW + \ + HAL_MCFxxxx_PITx_PCSR_PIE + HAL_MCFxxxx_PITx_PCSR_PIF + \ + HAL_MCFxxxx_PITx_PCSR_RLD + HAL_MCFxxxx_PITx_PCSR_EN), %d0 + move.w %d0, HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR + + movem.l 4(%sp), %d0-%d1/%a0-%a1 + add.l #20, %sp + rte +#endif + + .end
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/src/var_arch.S +++ /dev/null @@ -1,87 +0,0 @@ -##============================================================================= -#####ECOSGPLCOPYRIGHTBEGIN#### -## ------------------------------------------- -## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## -## eCos is free software; you can redistribute it and/or modify it under -## the terms of the GNU General Public License as published by the Free -## Software Foundation; either version 2 or (at your option) any later version. -## -## eCos is distributed in the hope that it will be useful, but WITHOUT ANY -## WARRANTY; without even the implied warranty of MERCHANTABILITY or -## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -## for more details. -## -## You should have received a copy of the GNU General Public License along -## with eCos; if not, write to the Free Software Foundation, Inc., -## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -## -## As a special exception, if other files instantiate templates or use macros -## or inline functions from this file, or you compile this file and link it -## with other works to produce a work based on this file, this file does not -## by itself cause the resulting work to be covered by the GNU General Public -## License. However the source code for this file must still be made available -## in accordance with section (3) of the GNU General Public License. -## -## This exception does not invalidate any other reasons why a work based on -## this file might be covered by the GNU General Public License. -## -## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -## at http://sources.redhat.com/ecos/ecos-license/ -## ------------------------------------------- -#####ECOSGPLCOPYRIGHTEND#### -##============================================================================= -/***************************************************************************** -var_arch.S -- mcf52xx variant code -*****************************************************************************/ - -#include <pkgconf/hal.h> - -/***************************************************************************** -FUNC_START -- Function declaration macro -*****************************************************************************/ -#define FUNC_START(name) \ - .text; \ - .even; \ - .globl name; \ -name: - -/* ************************************************************************ */ -/* These routines write to the special purpose registers in the ColdFire */ -/* core. Since these registers are write-only in the supervisor model, no */ -/* corresponding read routines exist. */ - -FUNC_START(mcf52xx_wr_vbr) - move.l 4(%sp),%d0 - andi.l #0xFFF00000,%d0 /* align to 1M boundary */ - movec %d0,%vbr - nop - rts - -FUNC_START(mcf52xx_wr_cacr) - move.l 4(%sp),%d0 - movec %d0,%cacr - nop - rts - -FUNC_START(mcf52xx_wr_acr0) - move.l 4(%sp),%d0 - movec %d0,%acr0 - nop - rts - -FUNC_START(mcf52xx_wr_acr1) - move.l 4(%sp),%d0 - movec %d0,%acr1 - nop - rts - -FUNC_START(mcf52xx_wr_rambar) - move.l 4(%sp),%d0 - .equ rambar,0xc04 /* Rc for movec */ - movec %d0,#rambar - nop - rts - -
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/src/var_misc.c +++ /dev/null @@ -1,69 +0,0 @@ -//========================================================================== -// -// var_misc.c -// -// HAL implementation miscellaneous functions -// -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> - -#include <cyg/hal/hal_intr.h> -#include <cyg/hal/hal_arch.h> - -//-------------------------------------------------------------------------- -// VSR table - -// For the mcf52xx, we can point the VBR directly to the VSR table. -// However, the table must be on a 1 MB boundary. Locate the VSR table where -// the linker tells us to. - -volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT] - __attribute__ ((section (".ramvec"))); - -//-------------------------------------------------------------------------- -void hal_variant_init(void) -{ - - // Don't need to do anything yet. - -} - -//-------------------------------------------------------------------------- -// End of var_misc.c -
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/src/var_startup.c +++ /dev/null @@ -1,100 +0,0 @@ -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== - -#include <cyg/infra/cyg_type.h> -#include <pkgconf/hal.h> -#include <cyg/hal/hal_startup.h> -#include <cyg/hal/hal_memmap.h> -#include <cyg/hal/hal_arch.h> - -/***************************************************************************** -var_init_cache_acr -- Initialize the cache and access control registers - -INPUT: - -OUTPUT: - -RETURN VALUE: - - None - -*****************************************************************************/ -static void var_init_cache_acr(void) -{ - - // Invalidate and disable the cache and ACRs. - - mcf52xx_wr_cacr((CYG_WORD32)0x01000000); - mcf52xx_wr_acr0((CYG_WORD32)0); - mcf52xx_wr_acr1((CYG_WORD32)0); - - // Call a routine to set up the cache and ACRs for this specific - // platform. - - plf_init_cache_acr(); - -} - -/***************************************************************************** -var_reset -- Variant-specific reset vector initialization routine - - This routine must be called with interrupts disabled. - -INPUT: - -OUTPUT: - -RETURN VALUE: - - None - -*****************************************************************************/ -void var_reset(void) -{ - - // Initialize the processor's vector base register. - - mcf52xx_wr_vbr((CYG_WORD32)__ramvec_start); - - // Initialize the cache and access control registers. - - var_init_cache_acr(); - - // Do any processor-specific reset initialization. - - proc_reset(); -} - -
deleted file mode 100644 --- a/packages/hal/m68k/mcf52xx/var/current/src/vectors.S +++ /dev/null @@ -1,489 +0,0 @@ -/***************************************************************************** -vectors.S -- mcf52xx exception vectors -*****************************************************************************/ -#####ECOSGPLCOPYRIGHTBEGIN#### -## ------------------------------------------- -## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## -## eCos is free software; you can redistribute it and/or modify it under -## the terms of the GNU General Public License as published by the Free -## Software Foundation; either version 2 or (at your option) any later version. -## -## eCos is distributed in the hope that it will be useful, but WITHOUT ANY -## WARRANTY; without even the implied warranty of MERCHANTABILITY or -## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -## for more details. -## -## You should have received a copy of the GNU General Public License along -## with eCos; if not, write to the Free Software Foundation, Inc., -## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -## -## As a special exception, if other files instantiate templates or use macros -## or inline functions from this file, or you compile this file and link it -## with other works to produce a work based on this file, this file does not -## by itself cause the resulting work to be covered by the GNU General Public -## License. However the source code for this file must still be made available -## in accordance with section (3) of the GNU General Public License. -## -## This exception does not invalidate any other reasons why a work based on -## this file might be covered by the GNU General Public License. -## -## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -## at http://sources.redhat.com/ecos/ecos-license/ -## ------------------------------------------- -#####ECOSGPLCOPYRIGHTEND#### -##============================================================================= - -#include <pkgconf/system.h> -#include <pkgconf/hal.h> - -#ifdef CYGPKG_KERNEL -#include <pkgconf/kernel.h> -#endif /* CYGPKG_KERNEL */ - -/****************************************************************************/ - - .file "vectors.S" - -/****************************************************************************/ - -/****************************************************************************/ - -/* The mcf52xx core allows us to move the VBR to our RAM vector table */ -/* at cyg_hal_vsr_table provided the table is at a 1MB boundary. */ - -/****************************************************************************/ -/* ROM vector table */ - -/* Create the ROM vector table. We use this table to initialize */ -/* cyg_hal_vsr_table which we point the VBR to. */ - - .macro hw_vsr name - .long hw_vsr_\name - .endm - - .section ".romvec","ax" - - .globl rom_vsr_table -rom_vsr_table: - - /* 0 - Initial SSP */ - hw_vsr stack - - /* 1 - Initial PC */ - hw_vsr reset - - /* 2-24 - Default exception handlers */ - .rept 24-2+1 - hw_vsr default - .endr - - /* 25-31 - Autovector interrupts 1-7 */ - .rept 31-25+1 - hw_vsr autovec - .endr - - /* 32-63 - Default exception handlers */ - .rept 63-32+1 - hw_vsr default - .endr - - /* 64-255 - User interrupt vectors */ - .rept 255-64+1 - hw_vsr interrupt - .endr - - .equ rom_vsr_table_size, . - rom_vsr_table - -/****************************************************************************/ -/* The default excetpion vector handler */ - -/* The default handler for all machine exceptions. We save the */ -/* machine state and call the default C VSR handler. This routine passes a */ -/* pointer to the saved state to the C VSR handler. The stack pointer in */ -/* the saved state points to the byte following the PC on the exception */ -/* stack (the sp before the exception). The format/vector word in the */ -/* exception stack contains the vector number. */ - -/* -void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs); -*/ - - .text - .balign 4 -hw_vsr_default: - - lea.l -(16*4)(%sp),%sp /* Preserve the entire state. */ - movem.l %d0-%d7/%a0-%a6,(%sp) /* Allocate space for all */ - lea.l ((16+1+1)*4)(%sp),%a0 /* registers (including the */ - move.l %a0,(15*4)(%sp) /* stack pointer). Write all */ - /* registers to the stack */ - /* space. Write the original */ - /* stack pointer value to the */ - /* stack. The format/vector */ - /* word, sr, and pc are already */ - /* on the stack. */ - - move.w (16*4)(%sp),%d0 /* Calculate the vector */ - and.l #0x000003fc,%d0 /* number. The format/vector */ - lsr.l #2,%d0 /* word on the stack contains */ - /* the vector number. */ - - pea.l (%sp) /* Pass a pointer to the */ - /* saved state to the exception */ - /* handler. */ - - move.l %d0,-(%sp) /* Push the vector number */ - /* parameter. */ - - .extern hal_default_exception_handler /* Call the default */ - jbsr hal_default_exception_handler /* exception VSR. This */ - /* routine may (and */ - /* probably will) modify */ - /* the exception context. */ - - addq.l #2*4,%sp /* Remove the vector number */ - /* and the state pointer from */ - /* the stack. */ - - /* Restore the state. There */ - /* is a chance that a debugger */ - /* changed the state (including */ - /* the stack pointer, PC, */ - /* etc.). We must be very */ - /* careful to restore the new */ - /* state without first */ - /* overwriting the values on */ - /* the stack. We must copy the */ - /* format/vector word, SR, and */ - /* PC to the new stack, but we */ - /* must make sure that the new */ - /* stack is not in the middle */ - /* of our current stack */ - /* variables that we are using. */ - - movem.l (%sp),%d0-%d7/%a0-%a4 /* Restore all of the */ - /* registers that we do not */ - /* need in the following code. */ - /* We will copy all registers */ - /* that are not restored here */ - /* to the new stack before */ - /* restoring them. */ - - move.l (15*4)(%sp),%a6 /* Load the address of the */ - /* new SP. */ - - lea.l (18*4)(%sp),%a5 /* Get a pointer to the */ - /* location following the */ - /* exception context. */ - - cmp.l %a5,%a6 /* Compare the new stack */ - jcc 1f /*jcc=jhs*/ /* address to the end of the */ - /* exception context. This */ - /* will tell us the order that */ - /* we need to copy the */ - /* exception stack and the */ - /* remaining registers from the */ - /* exception context to the new */ - /* stack. The order is */ - /* important because the stack */ - /* frames might (and in many */ - /* cases do) overlap. */ - - /* The new SP is at a lower */ - /* address than the end of the */ - /* exception context. Copy */ - /* from the lowest address to */ - /* the highest address. */ - - lea.l -5*4(%a6),%a6 /* Copy A5, A6, FVW, SR, and */ - move.l -5*4(%a5),(%a6) /* PC from the old stack to the */ - move.l -4*4(%a5),1*4(%a6) /* new stack. Note that we do */ - move.l -2*4(%a5),3*4(%a6) /* not copy the SP location but */ - move.l -1*4(%a5),4*4(%a6) /* we leave a space for it on */ - /* the new stack. If we do not */ - /* leave space for the SP, */ - /* there is a possibility of */ - /* overwriting some of our */ - /* data. Note that we copy in */ - /* increasing order. */ - - move.l %a6,%sp /* A6 points to the top of */ - move.l (%sp)+,%a5 /* the new stack with our */ - move.l (%sp)+,%a6 /* registers on it. Restore */ - addq.l #1*4,%sp /* the remaining registers and */ - rte /* use the exception stack to */ - /* return. Note that we also */ - /* remove the unused space left */ - /* for the SP. */ - -1: - - move.l -(%a5),-(%a6) /* The new SP is at a higher */ - move.l -(%a5),-(%a6) /* or the same address as the */ - subq.l #4,%a5 /* end of the exception */ - move.l -(%a5),-(%a6) /* context. Copy from the */ - move.l -(%a5),-(%a6) /* highest address to the */ - /* lowest address. Note that */ - /* we do not copy the stack */ - /* pointer. When copying in */ - /* this direction, there is no */ - /* reason to leave space for */ - /* the stack pointer. */ - - move.l %a6,%sp /* A6 points to the top of */ - move.l (%sp)+,%a5 /* the new stack with our */ - move.l (%sp)+,%a6 /* registers on it. Restore */ - rte /* the remaining registers and */ - /* use the exception stack to */ - /* return. */ - -/****************************************************************************/ -/* User interrupt vector handler */ - -/* Control is transferred here from a user interrupt vector (#64-255). */ - -/* Before branching to common code, load a value to translate the */ -/* vector table offset to the ISR table offset. The ISR vector table */ -/* contains the autovectors (0-6) followed by the interrupt vectors */ -/* (7-198). */ - - .equ int_pres_regs_sz,((2+3)*4) - .macro int_pres_regs - lea.l -int_pres_regs_sz(%sp),%sp - movem.l %d0-%d2/%a0-%a1,(%sp) - .endm - .macro int_rest_regs - movem.l (%sp),%d0-%d2/%a0-%a1 - lea.l int_pres_regs_sz(%sp),%sp - .endm - - .text - .balign 4 -hw_vsr_interrupt: - - int_pres_regs /* Preserve all registers */ - /* that this ISR routine needs */ - /* to preserve. The C code */ - /* will preserve all other */ - /* registers. */ - - move.l #(-64+7)*4,%d0 /* Adding this value to the */ - /* vector table offset will */ - /* result in the corresponding */ - /* offset into the ISR table. */ - - /* Fall through to common code. */ - -hw_vsr_int_common: /* Common code. */ - - /* d0.l: Contains a value to translate the vector table offset to */ - /* the ISR table offset. */ - - move.w int_pres_regs_sz(%sp),%d1 /* Calculate the vector */ - and.l #0x000003fc,%d1 /* offset. The format/vector */ - /* word on the stack contains */ - /* the vector number. Mask off */ - /* all unused bits. The bit */ - /* position of the vector */ - /* number field makes it */ - /* automatically multiplied by */ - /* four. */ - - add.l %d1,%d0 /* Calculate the ISR table */ - /* offset. Add the vector */ - /* table offset to the */ - /* translation value. */ - - asr.l #2,%d1 /* Calculate the vector */ - /* number using the vector */ - /* table offset. */ - - /* d0.l: Contains the offset into the ISR table. */ - - /* d1.l: Contains the vector number. */ - -#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT - - .extern cyg_scheduler_sched_lock /* Lock the scheduler if */ - addq.l #1,cyg_scheduler_sched_lock /* we are using the kernel. */ - -#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ - -/* We need to call the following routines. The isr address, data, and */ -/* intr are all from the ISR table. interrupt_end is a C routine and is */ -/* only called if we are using the kernel. regs points to the saved */ -/* registers on the stack. isr_ret is the return address from isr. vector */ -/* is the vector number. */ - -/* -static cyg_uint32 isr(CYG_ADDRWORD vector, - CYG_ADDRWORD data) - -externC void interrupt_end(cyg_uint32 isr_ret, - Cyg_Interrupt *intr, - HAL_SavedRegisters *regs) -*/ - - pea (%sp) /* Push the regs pointer. */ - - .extern cyg_hal_interrupt_objects /* Push the intr object */ - lea cyg_hal_interrupt_objects,%a0 /* pointer from the table. */ - move.l (%a0,%d0.l),-(%sp) - - .extern cyg_hal_interrupt_data /* Push the data value */ - lea cyg_hal_interrupt_data,%a0 /* from the table. */ - move.l (%a0,%d0.l),-(%sp) - - .extern cyg_hal_interrupt_handlers /* Get the address of the */ - lea cyg_hal_interrupt_handlers,%a0 /* ISR from the table. */ - move.l (%a0,%d0.l),%a0 - - move.l %d1,-(%sp) /* Push the vector number */ - /* parameter. */ - - jbsr (%a0) /* Call the ISR. */ - - addq.l #4*1,%sp /* Remove the vector */ - /* parameter from the stack. */ - - move.l %d0,(%sp) /* d0.l contains the return */ - /* value from the ISR. */ - /* Overwrite the data parameter */ - /* with the ISR return value to */ - /* pass as a parameter */ - /* (isr_ret) to interrupt_end. */ - /* The intr object and regs */ - /* parameters are still on the */ - /* stack. */ - -#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT - - /* We only need to call interrupt_end() when there is a kernel */ - /* present to do any tidying up. */ - - /* The interrupt_end routine will call the DSRs and do */ - /* rescheduling when it decrements the scheduler lock from 1 to */ - /* zero. In this case, we do not want to have interrupts masked */ - /* while the DSRs run. Restore the interrupt mask to the value */ - /* prior to this interrupt. Do not completely unmask all */ - /* interrupts because this interrupt may be a nested interrupt. We */ - /* do not want to lower the interrupt mask on the lower priority */ - /* interrupt. */ - - move.w (4*3)+int_pres_regs_sz+2(%sp),%d2 - move.w %d2,%sr - - /* If the interrupt mask was not previously zero, we want to make */ - /* sure that the DSRs to not run and no preemption occurs. Add the */ - /* value of the previous interrupt mask to the scheduler lock. If */ - /* the previous mask was zero, the scheduler lock will remain at */ - /* one and the interrupt end function will decrement it to zero. */ - /* Otherwise, we want to prevent the interrupt end function from */ - /* unlocking the scheduler. We do this because there is a chance */ - /* that someone had interrupts masked with the scheduler lock at */ - /* zero. If a higher priority interrupt occurs, we could be */ - /* running DSRs and doing preemption with the interrupts masked! */ - - and.l #0x0700,%d2 - lsr.l #8,%d2 - add.l %d2,cyg_scheduler_sched_lock - - .extern interrupt_end /* Call the interrupt_end C */ - jbsr interrupt_end /* routine. This routine might */ - /* preempt the currently */ - /* running thread. */ - - /* Now that interrupt end is complete, subtract the previous */ - /* interrupt level back out of the scheduler lock. */ - - sub.l %d2,cyg_scheduler_sched_lock - -#endif - - lea (4*3)(%sp),%sp /* Remove the isr_ret, intr, */ - /* and regs parameters from the */ - /* stack. */ - - int_rest_regs /* Restore the preserved */ - /* registers for the current */ - /* thread. */ - - rte /* Restore the SR and PC. */ - -/****************************************************************************/ -/* Autovector interrupt vector handler. */ - -/* Control is transferred here from an interrupt autovector (#25-31). */ - -/* Before branching to common code, load a value to translate the */ -/* vector table offset to the ISR table offset. The ISR vector table */ -/* contains the autovectors (0-6) followed by the interrupt vectors */ -/* (7-198). */ - - .text - .balign 4 -hw_vsr_autovec: - - int_pres_regs /* Preserve all registers */ - /* that this ISR routine needs */ - /* to preserve. The C code */ - /* will preserve all other */ - /* registers. */ - - move.l #(-25+0)*4,%d0 /* Adding this value to the */ - /* vector table offset will */ - /* result in the corresponding */ - /* offset into the ISR table. */ - - jra hw_vsr_int_common /* Branch into common code. */ - -/****************************************************************************/ -/* hw_vsr_reset -- Hardware Reset Vector */ - -/* We assume that most of the chip selects are configured by the boot */ -/* loader. */ - - .text - .balign 4 - .globl hw_vsr_reset -hw_vsr_reset: - - .globl __exception_reset /* Define the entry point for */ -__exception_reset: /* the linker. */ - - move.w #0x2700,%sr /* Make sure that all */ - /* interrupts are masked. */ - - lea hw_vsr_stack,%sp /* Load the reset and */ - /* interrupt stack pointer. */ - - lea 0,%fp /* Set up the initial frame */ - link %fp,#0 /* pointer. */ - - .extern hal_reset /* Call the C routine to */ - jbsr hal_reset /* complete the reset process. */ - -9: stop #0x2000 /* If we return, stop. */ - jra 9b - -/****************************************************************************/ -/* Interrupt and reset stack */ - -/* WARNING: Do not put this in any memory section that gets */ -/* initialized. Doing so may cause the C code to initialize its own stack. */ - - .section ".uninvar","aw",@nobits - - .balign 16 - .global hw_vsr_stack_bottom -hw_vsr_stack_bottom: - .skip 0x2000 - .balign 16 - .global hw_vsr_stack -hw_vsr_stack: - .skip 0x10 - -/****************************************************************************/ -