Mercurial > ecos
changeset 2115:3e45f460a99e
* cdl/hal_arm_xscale_pxa2x0.cdl: New
CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT option to select support for
the PXA25x series or the PXA27x series. The default is PXA25x so
existing packages work as-is.
* include/hal_pxa2x0.h: Add some extra PXA27x specific registers.
* src/pxa2x0_misc.c, include/hal_var_ints.h: Add support for the
extra interrupts (including the extra GPIO ones) on the PXA27x.
* src/pxa2x0_misc.c (hal_delay_us): Use correct timer clock
frequency for PXA27x. Correctly handle the loop taking longer
than 1 timer tick.
| author | asl |
|---|---|
| date | Thu, 29 Dec 2005 10:36:01 +0000 |
| parents | e126375ffab7 |
| children | 8286f0e1f4c7 |
| files | packages/hal/arm/xscale/pxa2x0/current/ChangeLog packages/hal/arm/xscale/pxa2x0/current/cdl/hal_arm_xscale_pxa2x0.cdl packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h packages/hal/arm/xscale/pxa2x0/current/include/hal_var_ints.h packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c |
| diffstat | 5 files changed, 234 insertions(+), 151 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/hal/arm/xscale/pxa2x0/current/ChangeLog +++ b/packages/hal/arm/xscale/pxa2x0/current/ChangeLog @@ -1,3 +1,19 @@ +2005-12-06 David Vrabel <dvrabel@arcom.com> + + * cdl/hal_arm_xscale_pxa2x0.cdl: New + CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT option to select support for + the PXA25x series or the PXA27x series. The default is PXA25x so + existing packages work as-is. + + * include/hal_pxa2x0.h: Add some extra PXA27x specific registers. + + * src/pxa2x0_misc.c, include/hal_var_ints.h: Add support for the + extra interrupts (including the extra GPIO ones) on the PXA27x. + + * src/pxa2x0_misc.c (hal_delay_us): Use correct timer clock + frequency for PXA27x. Correctly handle the loop taking longer + than 1 timer tick. + 2005-09-19 David Vrabel <dvrabel@arcom.com> * cdl/hal_arm_xscale_pxa2x0.cdl: Fix the last patch, logical OR
--- a/packages/hal/arm/xscale/pxa2x0/current/cdl/hal_arm_xscale_pxa2x0.cdl +++ b/packages/hal/arm/xscale/pxa2x0/current/cdl/hal_arm_xscale_pxa2x0.cdl @@ -67,6 +67,16 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_PXA2X0 puts $::cdl_header "#define CYGBLD_HAL_VAR_H <cyg/hal/hal_pxa2x0.h>" puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" } + + cdl_option CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT { + display "PXA2XX processor model" + description " + This option selects the variant of the PXA2XX family (PXA25x + or PXA27x) to support." + flavor data + legal_values { "PXA25X" "PXA27X" } + default_value { "PXA25X" } + } compile pxa2x0_misc.c
--- a/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h +++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h @@ -404,6 +404,8 @@ #define PXA2X0_ICFP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x000c ) #define PXA2X0_ICPR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0010 ) #define PXA2X0_ICCR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0014 ) +#define PXA2X0_ICMR2 PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a0 ) +#define PXA2X0_ICLR2 PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a4 ) // GPIO #define PXA2X0_GPIO_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0e00000 ) @@ -434,6 +436,15 @@ #define PXA2X0_GAFR1_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 ) #define PXA2X0_GAFR2_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 ) #define PXA2X0_GAFR2_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 ) +#define PXA2X0_GAFR3_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x006c ) +#define PXA2X0_GAFR3_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0070 ) +#define PXA2X0_GPLR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0100 ) +#define PXA2X0_GPDR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x010c ) +#define PXA2X0_GPSR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0118 ) +#define PXA2X0_GPCR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0124 ) +#define PXA2X0_GRER3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0130 ) +#define PXA2X0_GFER3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x013c ) +#define PXA2X0_GEDR3 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0148 ) #define PXA2X0_GPIO_NORM 0x00 #define PXA2X0_GPIO_AF1 0x01 @@ -492,24 +503,46 @@ #define PXA2X0_CCCR PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0000 ) #define PXA2X0_CKEN PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0004 ) #define PXA2X0_OSCC PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0008 ) - // Memory Clock -#define PXA2X0_CCCR_L09 (0x1f) -#define PXA2X0_CCCR_L27 (0x01) -#define PXA2X0_CCCR_L32 (0x02) -#define PXA2X0_CCCR_L36 (0x03) -#define PXA2X0_CCCR_L40 (0x04) -#define PXA2X0_CCCR_L45 (0x05) - // Memory-to-Run-Mode multiplier -#define PXA2X0_CCCR_M1 (0x1 << 5) -#define PXA2X0_CCCR_M2 (0x2 << 5) -#define PXA2X0_CCCR_M4 (0x3 << 5) - // Run-Mode-to-Turbo-Mode multiplier -#define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0 -#define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5 -#define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0 -#define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5 -#define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0 +// PXA25x CCCR bits +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X +// Crystal Frequency to Memory Frequency multiplier +# define PXA2X0_CCCR_L09 (0x1f) +# define PXA2X0_CCCR_L27 (0x01) +# define PXA2X0_CCCR_L32 (0x02) +# define PXA2X0_CCCR_L36 (0x03) +# define PXA2X0_CCCR_L40 (0x04) +# define PXA2X0_CCCR_L45 (0x05) +// Memory frequency to to run mode frequency multiplier +# define PXA2X0_CCCR_M1 (0x1 << 5) +# define PXA2X0_CCCR_M2 (0x2 << 5) +# define PXA2X0_CCCR_M4 (0x3 << 5) +// Run mode frequency to turbo mode frequency multiplier +# define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0 +# define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5 +# define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0 +# define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5 +# define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0 +#endif + +// PXA27x CCCR bits +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X +// Run-mode-to-oscillator ratio +# define PXA27X_CCCR_L8 (0x08) +# define PXA27X_CCCR_L16 (0x10) +// Turbo-mode-to-run-mode ratio +# define PXA27X_CCCR_N1 (0x02 << 7) +# define PXA27X_CCCR_N1_5 (0x03 << 7) +# define PXA27X_CCCR_N2 (0x04 << 7) +# define PXA27X_CCCR_N2_5 (0x05 << 7) +# define PXA27X_CCCR_N3 (0x06 << 7) + +# define PXA27X_CCCR_A (0x02000000) +# define PXA27X_CCCR_PLL_EARLY_EN (0x04000000) +# define PXA27X_CCCR_LCD_26 (0x08000000) +# define PXA27X_CCCR_PPDIS (0x40000000) +# define PXA27X_CCCR_CPDIS (0x80000000) +#endif // LCD Controller #define PXA2X0_LCCR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0000 )
--- a/packages/hal/arm/xscale/pxa2x0/current/include/hal_var_ints.h +++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_var_ints.h @@ -52,15 +52,24 @@ #include <cyg/hal/hal_pxa2x0.h> // 1st level -// 0-7 Reserved +#define CYGNUM_HAL_INTERRUPT_SSP3 0 +#define CYGNUM_HAL_INTERRUPT_MSL 1 +#define CYGNUM_HAL_INTERRUPT_USBH2 2 +#define CYGNUM_HAL_INTERRUPT_USBH1 3 +#define CYGNUM_HAL_INTERRUPT_KEYPAD 4 +#define CYGNUM_HAL_INTERRUPT_MEMSTK 5 +#define CYGNUM_HAL_INTERRUPT_PWRI2C 6 +#define CYGNUM_HAL_INTERRUPT_OST_4_11 7 #define CYGNUM_HAL_INTERRUPT_GPIO0 8 #define CYGNUM_HAL_INTERRUPT_GPIO1 9 -#define CYGNUM_HAL_INTERRUPT_GPIO 10 +#define CYGNUM_HAL_INTERRUPT_GPIOX 10 #define CYGNUM_HAL_INTERRUPT_USB 11 #define CYGNUM_HAL_INTERRUPT_PMU 12 #define CYGNUM_HAL_INTERRUPT_I2S 13 #define CYGNUM_HAL_INTERRUPT_AC97 14 -// 15,16 Reserved +#define CYGNUM_HAL_INTERRUPT_ASSP 15 /* PXA25x */ +#define CYGNUM_HAL_INTERRUPT_USIM 15 /* PXA27x */ +#define CYGNUM_HAL_INTERRUT_NSSP 16 #define CYGNUM_HAL_INTERRUPT_LCD 17 #define CYGNUM_HAL_INTERRUPT_I2C 18 #define CYGNUM_HAL_INTERRUPT_ICP 19 @@ -77,6 +86,16 @@ #define CYGNUM_HAL_INTERRUPT_HZ 30 #define CYGNUM_HAL_INTERRUPT_ALARM 31 +#if defined (CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X) + +#define CYGNUM_HAL_INTERRUPT_TPM 32 +#define CYGNUM_HAL_INTERRUPT_CAMERA 33 + +#define CYGNUM_HAL_INTERNAL_IRQS 34 + +#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X) + +#define CYGNUM_HAL_INTERNAL_IRQS 32 // 2nd level #define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2) @@ -166,13 +185,21 @@ #define CYGNUM_HAL_INTERRUPT_GPIO84 (96+20) #define CYGNUM_HAL_INTERRUPT_GPIO85 (96+21) +#endif + +#define CYGNUM_HAL_INTERRUPT_GPIO(i) \ + (((i) < 2) ? (CYGNUM_HAL_INTERRUPT_GPIO0 + (i)) : (CYGNUM_HAL_INTERNAL_IRQS + (i))) #define CYGNUM_HAL_INTERRUPT_NONE -1 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 #define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX (96+21) +#if defined CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X +# define CYGNUM_HAL_ISR_MAX (96+21) +#elif defined CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X +# define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERNAL_IRQS + 121) +#endif #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1) #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
--- a/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c +++ b/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c @@ -85,9 +85,22 @@ void hal_hardware_init(void) *PXA2X0_GFER1 = 0; *PXA2X0_GFER2 = 0; +#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X) *PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status *PXA2X0_GEDR1 = 0xffffffff; *PXA2X0_GEDR2 = 0x0001ffff; +#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X) + *PXA2X0_ICMR2 = 0; + *PXA2X0_ICLR2 = 0; + + *PXA2X0_GRER3 = 0; + *PXA2X0_GFER3 = 0; + + *PXA2X0_GEDR0 = 0xfffff71b; + *PXA2X0_GEDR1 = 0xffffffff; + *PXA2X0_GEDR2 = 0xffffffff; + *PXA2X0_GEDR3 = 0x1fffffff; +#endif plf_hardware_init(); // Perform any platform specific initializations @@ -165,15 +178,21 @@ void hal_clock_read(cyg_uint32 *pvalue) // Delay for some number of micro-seconds void hal_delay_us(cyg_int32 usecs) { +#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X) +# define NSECS_PER_TICK 271267 /* 3.6865 MHz clock */ +#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X) +# define NSECS_PER_TICK 307692 /* 3.25 MHz clock */ +#endif + cyg_uint32 val = 0; - cyg_uint32 ctr = *PXA2X0_OSCR; + cyg_uint32 prev = *PXA2X0_OSCR; while (usecs-- > 0) { - do { - if (ctr != *PXA2X0_OSCR) { - val += 271267; // 271267ps (3.6865Mhz -> 271.267ns) - ++ctr; - } - } while (val < 1000000); + while (val < 1000000) { + cyg_uint32 now = *PXA2X0_OSCR; + cyg_uint32 diff = now - prev; + val += NSECS_PER_TICK * diff; + prev = now; + } val -= 1000000; } } @@ -208,13 +227,13 @@ int hal_IRQ_handler(void) do { if ( (1 << index) & sources ) { - if (index == CYGNUM_HAL_INTERRUPT_GPIO) { + if (index == CYGNUM_HAL_INTERRUPT_GPIOX) { // Special case of GPIO cascade. Search for lowest set bit sources = *PXA2X0_GEDR0; index = 0; do { if (sources & (1 << index)) { - return index+32; + return CYGNUM_HAL_INTERNAL_IRQS + index; } index++; } while (index < 32); @@ -222,7 +241,7 @@ int hal_IRQ_handler(void) index = 0; do { if (sources & (1 << index)) { - return index+64; + return CYGNUM_HAL_INTERNAL_IRQS + 32 + index; } index++; } while (index < 32); @@ -230,11 +249,20 @@ int hal_IRQ_handler(void) index = 0; do { if (sources & (1 << index)) { - return index+96; + return CYGNUM_HAL_INTERNAL_IRQS + 64 + index; } index++; - } while (index < 21); - + } while (index < 32); +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X + sources = *PXA2X0_GEDR3; + index = 0; + do { + if (sources & (1 << index)) { + return CYGNUM_HAL_INTERNAL_IRQS + 96 + index; + } + index++; + } while (index < 32); +#endif } return index; } @@ -253,9 +281,14 @@ void hal_interrupt_mask(int vector) // Normal vectors are handled by code subsequent to the macro call. HAL_EXTENDED_INTERRUPT_MASK(vector); #endif - - if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { - vector = CYGNUM_HAL_INTERRUPT_GPIO; +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X + if (vector >= 32 && vector < CYGNUM_HAL_INTERNAL_IRQS) { + *PXA2X0_ICMR2 &= ~(1 << (vector - 32)); + return; + } +#endif + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) { + vector = CYGNUM_HAL_INTERRUPT_GPIOX; } *PXA2X0_ICMR &= ~(1 << vector); } @@ -269,9 +302,14 @@ void hal_interrupt_unmask(int vector) // Normal vectors are handled by code subsequent to the macro call. HAL_EXTENDED_INTERRUPT_UNMASK(vector); #endif - - if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { - vector = CYGNUM_HAL_INTERRUPT_GPIO; +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X + if (vector >= 32 && vector < CYGNUM_HAL_INTERNAL_IRQS) { + *PXA2X0_ICMR2 |= (1 << (vector - 32)); + return; + } +#endif + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) { + vector = CYGNUM_HAL_INTERRUPT_GPIOX; } *PXA2X0_ICMR |= (1 << vector); } @@ -285,25 +323,31 @@ void hal_interrupt_acknowledge(int vecto // Normal vectors are handled by code subsequent to the macro call. HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector); #endif - if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) - { - *PXA2X0_GEDR0 = (1 << (vector - 8)); - }else{ - if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) { - *PXA2X0_GEDR2 = (1 << (vector - 96)); - } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) { - *PXA2X0_GEDR1 = (1 << (vector - 64)); - } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { - *PXA2X0_GEDR0 = (1 << (vector - 32)); - } else { - // Not a GPIO interrupt - return; - } - } + if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) { + *PXA2X0_GEDR0 = (1 << (vector - 8)); + } else { +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(96)) { + *PXA2X0_GEDR3 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96)); + } else +#endif + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(64)) { + *PXA2X0_GEDR2 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(32)) { + *PXA2X0_GEDR1 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) { + *PXA2X0_GEDR0 = (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS)); + } else { + // Not a GPIO interrupt + return; + } + } } void hal_interrupt_configure(int vector, int level, int up) { + cyg_bool falling = level || !up; + cyg_bool rising = level || up; #ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE // Use platform specific handling, if defined @@ -311,102 +355,55 @@ void hal_interrupt_configure(int vector, // Normal vectors are handled by code subsequent to the macro call. HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up); #endif - if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) { - if (level) { - if (up) { - // Enable both edges - *PXA2X0_GRER2 |= (1 << (vector - 96)); - *PXA2X0_GFER2 |= (1 << (vector - 96)); - } else { - // Disable both edges - *PXA2X0_GRER2 &= ~(1 << (vector - 96)); - *PXA2X0_GFER2 &= ~(1 << (vector - 96)); - } - } else { - // Only interested in one edge - if (up) { - // Set rising edge detect and clear falling edge detect. - *PXA2X0_GRER2 |= (1 << (vector - 96)); - *PXA2X0_GFER2 &= ~(1 << (vector - 96)); - } else { - // Set falling edge detect and clear rising edge detect. - *PXA2X0_GFER2 |= (1 << (vector - 96)); - *PXA2X0_GRER2 &= ~(1 << (vector - 96)); - } - } - } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) { - if (level) { - if (up) { - // Enable both edges - *PXA2X0_GRER1 |= (1 << (vector - 64)); - *PXA2X0_GFER1 |= (1 << (vector - 64)); - } else { - // Disable both edges - *PXA2X0_GRER1 &= ~(1 << (vector - 64)); - *PXA2X0_GFER1 &= ~(1 << (vector - 64)); - } - } else { - // Only interested in one edge - if (up) { - // Set rising edge detect and clear falling edge detect. - *PXA2X0_GRER1 |= (1 << (vector - 64)); - *PXA2X0_GFER1 &= ~(1 << (vector - 64)); - } else { - // Set falling edge detect and clear rising edge detect. - *PXA2X0_GFER1 |= (1 << (vector - 64)); - *PXA2X0_GRER1 &= ~(1 << (vector - 64)); - } - } - } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { - if (level) { - if (up) { - // Enable both edges - *PXA2X0_GRER0 |= (1 << (vector - 32)); - *PXA2X0_GFER0 |= (1 << (vector - 32)); - } else { - // Disable both edges - *PXA2X0_GRER0 &= ~(1 << (vector - 32)); - *PXA2X0_GFER0 &= ~(1 << (vector - 32)); - } - } else { - // Only interested in one edge - if (up) { - // Set rising edge detect and clear falling edge detect. - *PXA2X0_GRER0 |= (1 << (vector - 32)); - *PXA2X0_GFER0 &= ~(1 << (vector - 32)); - } else { - // Set falling edge detect and clear rising edge detect. - *PXA2X0_GFER0 |= (1 << (vector - 32)); - *PXA2X0_GRER0 &= ~(1 << (vector - 32)); - } - } - } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) - { - if (level) { - if (up) { - // Enable both edges - *PXA2X0_GRER0 |= (1 << (vector - 8)); - *PXA2X0_GFER0 |= (1 << (vector - 8)); - } else { - // Disable both edges - *PXA2X0_GRER0 &= ~(1 << (vector - 8)); - *PXA2X0_GFER0 &= ~(1 << (vector - 8)); - } - } else { - // Only interested in one edge - if (up) { - // Set rising edge detect and clear falling edge detect. - *PXA2X0_GRER0 |= (1 << (vector - 8)); - *PXA2X0_GFER0 &= ~(1 << (vector - 8)); - } else { - // Set falling edge detect and clear rising edge detect. - *PXA2X0_GFER0 |= (1 << (vector - 8)); - *PXA2X0_GRER0 &= ~(1 << (vector - 8)); - } - } - } - - +#ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(96)) { + if (falling) + *PXA2X0_GFER3 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96)); + else + *PXA2X0_GFER3 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96)); + if (rising) + *PXA2X0_GRER3 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96)); + else + *PXA2X0_GRER3 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 96)); + } else +#endif + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(64)) { + if (falling) + *PXA2X0_GFER2 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64)); + else + *PXA2X0_GFER2 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64)); + if (rising) + *PXA2X0_GRER2 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64)); + else + *PXA2X0_GRER2 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 64)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(32)) { + if (falling) + *PXA2X0_GFER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32)); + else + *PXA2X0_GFER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32)); + if (rising) + *PXA2X0_GRER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32)); + else + *PXA2X0_GRER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS - 32)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO(2)) { + if (falling) + *PXA2X0_GFER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS)); + else + *PXA2X0_GFER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS)); + if (rising) + *PXA2X0_GRER1 |= (1 << (vector - CYGNUM_HAL_INTERNAL_IRQS)); + else + *PXA2X0_GRER1 &= ~(1 << (vector - CYGNUM_HAL_INTERNAL_IRQS)); + } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) { + if (falling) + *PXA2X0_GFER0 |= (1 << (vector - 8)); + else + *PXA2X0_GFER0 &= ~(1 << (vector - 8)); + if (rising) + *PXA2X0_GRER0 |= (1 << (vector - 8)); + else + *PXA2X0_GRER0 &= ~(1 << (vector - 8)); + } } void hal_interrupt_set_level(int vector, int level)