Mercurial > ecos
changeset 2461:6ac315df1958
Port to the FR30 architecture, the mb91301 variant and the skmb91302 board.
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new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/ChangeLog @@ -0,0 +1,51 @@ +2007-07-09 Lars Poeschel <larsi@wh2.tu-dresden.de> + + * src/context.S: + * src/fr30_stub.c: + * src/hal_misc.c: + * src/vectors.S: + * include/arch.inc: + * include/basetype.h: + * include/fr30.inc: + * include/fr30_stub.h: + * include/hal_arch.h: + * include/hal_cache.h: + * include/hal_intr.h: + * include/hal_io.h: + * cdl/hal_fr30.cdl: Initial fr30 ecos port + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/cdl/hal_fr30.cdl @@ -0,0 +1,80 @@ +# ==================================================================== +# +# hal_fr30.cdl +# +# fr30 architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): larsi +# Original data: +# Contributors: +# Date: 2006-05-28 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_FR30 { + display "fr30 architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + define_header hal_fr30.h + description " + The fr30 architecture HAL package provides generic + support for Fujitsu's fr30/fr50/fr60 processor architecture. + It is also necessary to select a specific target platform HAL + package. If you have a fr50 device, choose the MB91360 variant." + + cdl_interface CYGINT_HAL_FR30_VARIANT { + display "Number of variant implementations in this configuration" + requires 1 == CYGINT_HAL_FR30_VARIANT + } + + compile hal_misc.c context.S vectors.S fr30_stub.c + + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/arch.inc @@ -0,0 +1,190 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +##============================================================================= +## +## arch.inc +## +## fr30 assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors: larsi +## Date: 2006-06-20 +## Purpose: Architecture definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the fr30 CPU family. +## Usage: +## #include <cyg/hal/arch.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/fr30.inc> + +#include <cyg/hal/variant.inc> + +##----------------------------------------------------------------------------- +## define some .equ's to access c-code #define's from assembler code +.equ CYGNUM_ASM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE + +##----------------------------------------------------------------------------- +## CPU specific macros. These provide a common assembler interface to +## operations that may have CPU specific implementations on different +## variants of the architecture + +#ifndef CYGPKG_HAL_FR30_CPU_INIT_DEFINED + # Initialize CPU + .macro hal_cpu_init + .endm +#endif /* !CYGPKG_HAL_FR30_CPU_INIT_DEFINED */ + +.macro hal_cpu_int_enable + orccr #0x10 +.endm + +.macro hal_cpu_int_disable + andccr #0xef +.endm + + +# Merge the interrupt enable state of the status register in +# \sr with the current sr. + +.macro hal_cpu_int_merge sr + FIXME hal_cpu_int_merge not implemented yet +.endm + +##----------------------------------------------------------------------------- +# Default FR30 interrupt controller macros. Every FR30 has an integrated +# interrupt controller, which we use here. This should be enough if there is +# no special external interrupt controller (which I did not see yet). + +#ifndef CYGPKG_HAL_FR30_INTC_DEFINED + +#ifndef CYGPKG_HAL_FR30_INTC_INIT_DEFINED +# initialize all interrupts to disabled. This is done automatically during +# CPU reset and the macro is not used during ECOS startup. It is not +# supplied here but would be setting all ICRs to 31 (to disable the particular +# interrupt and maybe setting ILM in PS to 0. + .macro hal_intc_init + .endm +#endif + + +# Normally interrupts are decoded by hardware and can not be software decoded, +# so this is empty here. + + .macro hal_intc_decode vnum + .endm + +# Also translation interrupt number <--> vector number is done automatically +# in hardware, so the macros are not supplied here. + +#endif + +#------------------------------------------------------------------------------ +# These defines are for the ISR and VSR tables which are defined in assembler +# code. (currently in variant.S / vectors.S) and have to be the same like in +# hal_intr.h + +#define CYGNUM_HAL_VECTOR_INTRFIRST 15 +#define CYGNUM_HAL_VECTOR_INTRLAST 63 +#define CYGNUM_HAL_VECTOR_NUMINTRS (CYGNUM_HAL_VECTOR_INTRLAST-CYGNUM_HAL_VECTOR_INTRFIRST+1) + +// Common interrupt vectors +#ifndef CYGNUM_HAL_ISR_MIN +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_INTRFIRST +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_INTRLAST +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_VECTOR_NUMINTRS) +#endif + +// The default size of the VSR table is 256 entries. +#ifndef CYGNUM_HAL_VSR_MIN +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 255 +#define CYGNUM_HAL_VSR_COUNT 256 +#endif + +#------------------------------------------------------------------------------ +# Register save and restore macros. These expect a pointer to a CPU save state +# area in the register \ptr. The GPR indicated by \reg will be saved into its +# slot in that structure. + +# TODO do this macros if needed, look at MIPS arch.inc for inspiration + + +#------------------------------------------------------------------------------ +# Stack switching macros + + + +#------------------------------------------------------------------------------ +# MEMC macros. + + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_FR30_CACHE_DEFINED + + .macro hal_cache_init + + .endm + +#endif + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_FR30_TIMER_DEFINED + + .macro hal_timer_init + .endm + +#endif + + +#endif // ifndef CYGONCE_HAL_ARCH_INC +# end of arch.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/basetype.h @@ -0,0 +1,76 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors:larsi +// Date: 2006-06-15 +// Purpose: Define architecture base types. +// Usage: Included by "cyg_type.h", do not use directly +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // BIG endian + +// --------------------------------------------------------------------------- +// Override the alignment definitions from cyg_type.h + +#ifndef CYGARC_ALIGNMENT +#define CYGARC_ALIGNMENT 4 +#endif + +// The corresponding power of two alignment +#ifndef CYGARC_P2ALIGNMENT +#define CYGARC_P2ALIGNMENT 2 +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H +// End of basetype.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/fr30.inc @@ -0,0 +1,65 @@ +##============================================================================= +## +## fr30.inc +## +## fr30 assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors:larsi +## Date: 2006-06-15 +## Purpose: fr30 definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the fr30 +## Usage: +## #include <cyg/hal/fr30.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#------------------------------------------------------------------------------ +# Exception, interrupt and thread context save area layout +# The layout of this structure is also defined in "hal_arch.h", for C +# code. Do not change this without changing that (or vice versa). + +#------------------------------------------------------------------------------ +# end of fr30.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/fr30_stub.h @@ -0,0 +1,160 @@ +//======================================================================== +// +// fr30_stub.h +// +// FR30-specific definitions for remote debugging via gdb +// +//======================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: Fujitsu FR30-specific definitions for gdb stubs support +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_FR30_STUB_H +#define CYGONCE_HAL_FR30_STUB_H + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_IO_SERIAL +#include <pkgconf/io_serial.h> +#endif + +#include <cyg/hal/hal_diag.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#define HAL_STUB_PLATFORM_INIT_SERIAL() HAL_DIAG_INIT() + +#define HAL_STUB_PLATFORM_GET_CHAR() \ +((cyg_int8)({ \ + cyg_int8 _ch_; \ + HAL_DIAG_READ_CHAR(_ch_); \ + _ch_; \ +})) + +#define HAL_STUB_PLATFORM_PUT_CHAR(c) HAL_DIAG_WRITE_CHAR((c)) + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int,(baud)) + +#define HAL_STUB_PLATFORM_RESET() HAL_DIAG_INIT() + +#define HAL_STUB_PLATFORM_INIT() HAL_DIAG_INIT() + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#define FR30_GENREGS 16 +#define FR30_DEDICATEDREGS 8 +#define FR30_REGSIZE 4 /* bytes */ + +// only NUMREGS and REGSIZE are the really needed macros + +#define NUMREGS (FR30_GENREGS + FR30_DEDICATEDREGS) +#define REGSIZE( _x_ ) FR30_REGSIZE + + +typedef unsigned long target_register_t; + +enum regnames { + R0, R1, R2, R3, R4, R5, R6, R7, + R8, R9, R10, R11, R12, R13, R14, SP, + PC, PS, TBR, RP, SSP, USP, MDH, MDL +}; + +typedef enum regnames regnames_t; + +// Override generic stubs get_register() and use arch-specific version +#define CYGARC_STUB_REGISTER_ACCESS_DEFINED + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) +#define HAL_GET_PROFILE_INFO( _thepc_, _thesp_ ) \ + CYG_MACRO_START \ + extern HAL_SavedRegisters *hal_saved_interrupt_state; \ + if ( hal_saved_interrupt_state ) { \ + (_thepc_) = (char *)(hal_saved_interrupt_state->pc); \ + (_thesp_) = (char *)(hal_saved_interrupt_state->sp); \ + } \ + CYG_MACRO_END +#endif + +/* Given a trap value TRAP, return the corresponding signal. */ +externC int __computeSignal (unsigned int trap_number); + +/* Return the trap number corresponding to the last-taken trap. */ +externC int __get_trap_number (void); + +/* Return the currently-saved value corresponding to register REG. */ +externC target_register_t get_register (regnames_t reg); + +/* Store VALUE in the register corresponding to WHICH. */ +externC void put_register (regnames_t which, target_register_t value); + +/* Set the currently-saved pc register value to PC. This also updates NPC + as needed. */ +externC void set_pc (target_register_t pc); + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ +externC void __single_step (void); + +/* Clear the single-step state. */ +externC void __clear_single_step (void); + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ +externC int __is_breakpoint_function (void); + +/* Skip the current instruction. */ +externC void __skipinst (void); + +externC void __install_breakpoints (void); + +externC void __clear_breakpoints (void); + +#endif // ifndef CYGONCE_HAL_FR30_STUB_H + +// EOF fr30_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/hal_arch.h @@ -0,0 +1,363 @@ +#ifndef CYGONCE_HAL_HAL_ARCH_H +#define CYGONCE_HAL_HAL_ARCH_H + +//============================================================================= +// +// hal_arch.h +// +// Architecture specific abstractions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2006-05-28 +// Purpose: Define architecture abstractions +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_arch.h> + +#define CYG_HAL_FR30_REG CYG_ADDRWORD + +//----------------------------------------------------------------------------- +// Processor saved states. This structure is also defined in fr30.inc for +// assembly code. Do not change this without changing that (or vice versa). + +typedef struct HAL_SavedRegisters +{ + cyg_uint32 r[16]; // general purpose registers with + // r[13]: virtual accumulator (AC) + // r[14]: frame pointer (FP) + // r[15]: stack pointer (SP) r15 is not saved here! + cyg_uint32 pc; // program counter + cyg_uint32 ps; // program status (with ILM, SCR, CCR) + cyg_uint32 tbr; // table base register (not neccessary, + // as it is used system-wide not per thread) + cyg_uint32 rp; // return pointer + // ssp is used system-wide for EIT processing and does not need to be saved here + // and therefore we don't store usp, because we have it already in r15 + cyg_uint32 ssp; // system stack pointer + cyg_uint32 usp; // user stack pointer + cyg_uint32 mdh; // multiplication and division regs / + cyg_uint32 mdl; // with high and low words + + cyg_uint32 last_trap; // the last taken trap (for GDB stubs) + +} HAL_SavedRegisters; + + +//----------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. FIXME +// declared in src/hal_misc.c +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +//----------------------------------------------------------------------------- +// Bit manipulation routines +// declared in src/hal_misc.c + +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); + +#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); + +#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); + +//----------------------------------------------------------------------------- +// Context Initialization +// Initialize the context of a thread. +// Arguments: +// _sparg_ name of variable containing current sp, will be written with new sp +// _thread_ thread object address, passed as argument to entry point +// _entry_ entry point address. +// _id_ bit pattern used in initializing registers, for debugging. + +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ + CYG_MACRO_START \ + register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ + register HAL_SavedRegisters *_regs_; \ + int _i_; \ + _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT - 1)); \ + for( _i_ = 0; _i_ <= 14; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \ + (_regs_)->r[15] = (CYG_HAL_FR30_REG)(_regs_); /* r15 = USP = top of stack*/ \ + (_regs_)->r[04] = (CYG_HAL_FR30_REG)(_thread_); /* R4 = arg1 = thread ptr */ \ + (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \ + (_regs_)->ps = (CYG_HAL_FR30_REG)0x1f0030; /* 0x000F0030; set flags */ \ + (_regs_)->tbr = (CYG_HAL_FR30_REG)0xffc00; /*system standard tbr value*/ \ + (_regs_)->rp = (CYG_HAL_FR30_REG)0x0; /* return pointer = 0x0 */ \ + (_regs_)->ssp = (CYG_HAL_FR30_REG)0x0; /* R4 = arg1 = thread ptr */ \ + (_regs_)->usp = (CYG_HAL_FR30_REG)(_regs_); /* r15 = USP = top of stack*/ \ + (_regs_)->mdh = (CYG_HAL_FR30_REG)0; /* mdh = 0 */ \ + (_regs_)->mdl = (CYG_HAL_FR30_REG)0; /* mdl = 0 */ \ + (_sparg_) = (CYG_ADDRESS)_regs_; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Context switch macros. +// The arguments are pointers to locations where the stack pointer +// of the current thread is to be stored, and from where the sp of the +// next thread is to be fetched. +// declared in src/hal_misc.c + +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +externC void hal_thread_load_context( CYG_ADDRESS to ) + __attribute__ ((noreturn)); + +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ + hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_); + +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ + hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); + +//----------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//----------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define HAL_BREAKPOINT(_label_) \ +CYG_MACRO_START \ + asm volatile (" .globl " #_label_ ";\n" \ + #_label_":\n" \ + "int #0x9\n" \ + ); \ +CYG_MACRO_END + +// 0x9F30 is the INTE instruction (vector no.9, TBR offset 0x3D8) +// 0x1f09 is the INT# 9 instruction (vector no.9, TBR offset 0x3D8) +#define HAL_BREAKINST 0x1f09 +#define HAL_BREAKINST_SIZE 2 +#define HAL_BREAKINST_TYPE unsigned short + +//----------------------------------------------------------------------------- +// Thread register state manipulation for GDB support. + +// Default to a 32 bit register size for GDB register dumps. +#ifndef CYG_HAL_GDB_REG +#define CYG_HAL_GDB_REG CYG_WORD32 +#endif + +// Register layout expected by GDB +typedef struct +{ + CYG_HAL_FR30_REG r[16]; // was: r[0] GPR regs + CYG_HAL_FR30_REG pc; + CYG_HAL_FR30_REG ps; + CYG_HAL_FR30_REG tbr; + CYG_HAL_FR30_REG rp; + CYG_HAL_FR30_REG ssp; + CYG_HAL_FR30_REG usp; + CYG_HAL_FR30_REG mdh; + CYG_HAL_FR30_REG mdl; +} GDB_Registers; + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure declared in src/fr30_stub.h + +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + +// Copy a set of registers from a HAL_SavedRegisters structure into a +// GDB ordered array. +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ + CYG_MACRO_START \ + GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 16; _i_++ ) { \ + _gdb_->r[_i_] = (_regs_)->r[_i_]; \ + } \ + \ + _gdb_->pc = (_regs_)->pc; \ + _gdb_->ps = (_regs_)->ps; \ + _gdb_->tbr = (_regs_)->tbr; \ + _gdb_->rp = (_regs_)->rp; \ + _gdb_->ssp = (_regs_)->ssp; \ + _gdb_->usp = (_regs_)->usp; \ + _gdb_->mdh = (_regs_)->mdh; \ + _gdb_->mdl = (_regs_)->mdl; \ + CYG_MACRO_END + +// Copy a set of registers from a GDB_Registers structure into a +// HAL_SavedRegisters structure. +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ + CYG_MACRO_START \ + GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 16; _i_++ ) \ + (_regs_)->r[_i_] = _gdb_->r[_i_]; \ + \ + (_regs_)->pc = _gdb_->pc; \ + (_regs_)->ps = _gdb_->ps; \ + (_regs_)->tbr = _gdb_->tbr; \ + (_regs_)->rp = _gdb_->rp; \ + (_regs_)->ssp = _gdb_->ssp; \ + (_regs_)->usp = _gdb_->usp; \ + (_regs_)->mdh = _gdb_->mdh; \ + (_regs_)->mdl = _gdb_->mdl; \ + CYG_MACRO_END + + +// ------------------------------------------------------------------------- +// hal_setjmp/hal_longjmp + + +// We must save all of the registers that are preserved across routine +// calls. The assembly code assumes that this structure is defined in the +// following format. Any changes to this structure will result in changes to +// the assembly code!! + +typedef struct { + // registers + cyg_uint32 r8; + cyg_uint32 r9; + cyg_uint32 r10; + cyg_uint32 r11; + cyg_uint32 r14; + + // SP and PC + cyg_uint32 r15; //USP + cyg_uint32 pc; +} hal_jmp_buf_t; + +// This type is used by normal routines to pass the address of the structure +// into our routines without having to explicitly take the address +// of the structure. + +typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)]; + +// Define the generic setjmp and longjmp routines +externC int hal_setjmp(hal_jmp_buf env); +externC void hal_longjmp(hal_jmp_buf env, int val); +//----------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. (contains an empty function call at the moment) +// declared in src/hal_misc.c + +externC void hal_idle_thread_action(cyg_uint32 loop_count); + +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) + +//----------------------------------------------------------------------------- +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. +// +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// Stack frame overhead per call. 13 registers (which is a maximum FIXME), +// frame pointer, and return address. We can't guess the local variables so +// just assume that using all of the registers averages out. + +#define CYGNUM_HAL_STACK_FRAME_SIZE ((13 + 1 + 1) * 4) + +// Stack needed for a context switch. +// it should be sizeof(HAL_SavedRegisters) +// All registers + PC + PS + RP + MDH + MDL + +#ifndef CYGNUM_HAL_STACK_CONTEXT_SIZE +#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((16+1+1+1+1+1)*4) +#endif // CYGNUM_HAL_STACK_CONTEXT_SIZE + +// Interrupt + call to ISR, interrupt_end() and the DSR + +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ +((CYGNUM_HAL_STACK_CONTEXT_SIZE) + (4*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// We define a minimum stack size as the minimum any thread could ever +// legitimately get away with. We can throw asserts if users ask for less +// than this. Allow enough for four interrupt sources - clock, serial, +// nic, and one other + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM \ +((4*CYGNUM_HAL_STACK_INTERRUPT_SIZE) \ + + (16*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// Now make a reasonable choice for a typical thread size. Pluck figures +// from thin air and say 30 call frames with an average of 16 words of +// automatic variables per call frame + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ +(CYGNUM_HAL_STACK_SIZE_MINIMUM + \ + (30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))) + +//-------------------------------------------------------------------------- +// Memory access macros + +#define CYGARC_CACHED_ADDRESS(x) (x) +#define CYGARC_UNCACHED_ADDRESS(x) (x) +#define CYGARC_PHYSICAL_ADDRESS(x) (x) +#define CYGARC_VIRTUAL_ADDRESS(x) (x) + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). + +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_HAL_ARCH_H +// End of hal_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/hal_cache.h @@ -0,0 +1,127 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ +CYG_MACRO_START \ +_state_ = 1; \ +CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ +CYG_MACRO_START \ +_state_ = 1; \ +CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +//----------------------------------------------------------------------------- +// Instruction cache line control + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/hal_intr.h @@ -0,0 +1,431 @@ +#ifndef CYGONCE_HAL_HAL_INTR_H +#define CYGONCE_HAL_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// FR30 HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: larsi +// Date: 2006-06-09 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_fr30.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_intr.h> + +//-------------------------------------------------------------------------- +// Exception vectors. +// Standard exception,interrupt and trap(EIT) vectors supported by FR30 CPUs +// These values are the ones to use for HAL_VSR_GET/SET +// The FR30 vector table lies in reversed in memory, therefore we do +// the 255-x thing here. + +#define CYGNUM_HAL_VECTOR_RESET 0 +// Values from 1 - 8 are system reserved +#define CYGNUM_HAL_VECTOR_MODE_VECTOR 1 +#define CYGNUM_HAL_VECTOR_COPR_NOT_FOUND 7 +#define CYGNUM_HAL_VECTOR_COPR_ERROR 8 +#define CYGNUM_HAL_VECTOR_BREAKPOINT 9 +#define CYGNUM_HAL_VECTOR_INTE CYGNUM_HAL_VECTOR_BREAKPOINT +// Values 10 and 11 are system reserved +#define CYGNUM_HAL_VECTOR_INSTR_BREAK_EXCEPTION 10 +#define CYGNUM_HAL_VECTOR_OPERAND_BREAK_TRAP 11 +#define CYGNUM_HAL_VECTOR_DEBUG 12 +#define CYGNUM_HAL_VECTOR_STEP_TRACE CYGNUM_HAL_VECTOR_DEBUG +// Value 13 is system reserved +#define CYGNUM_HAL_VECTOR_NMI_INTR_TOOL 13 +// Value 14 undefined instruction exception +#define CYGNUM_HAL_VECTOR_OPCODE 14 +// NMI (special non maskable interrupt) +#define CYGNUM_HAL_VECTOR_NMI 15 +// interrupts +// Note that these defines are for C code and have to be the same like those in +// arch.inc for assembler code ! +#define CYGNUM_HAL_VECTOR_INTRFIRST 15 +#define CYGNUM_HAL_VECTOR_INTRLAST 63 +#define CYGNUM_HAL_VECTOR_NUMINTRS (CYGNUM_HAL_VECTOR_INTRLAST-CYGNUM_HAL_VECTOR_INTRFIRST+1) +// Values 64 and 65 are reserved for system +// traps +#define CYGNUM_HAL_VECTOR_TRAPFIRST 80 +#define CYGNUM_HAL_VECTOR_SYSTEM_CALL CYGNUM_HAL_VECTOR_TRAPFIRST +#define CYGNUM_HAL_VECTOR_TRAPLAST 255 +#define CYGNUM_HAL_VECTOR_NUMTRAPS (CYGNUM_HAL_VECTOR_TRAPLAST-CYGNUM_HAL_VECTOR_TRAPFIRST+1) + +// The default size of the VSR table is 256 entries. +#ifndef CYGNUM_HAL_VSR_MIN +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 255 +#define CYGNUM_HAL_VSR_COUNT 256 +#endif + +// For ecos fr30 interrupts are interrupts and fr30 exceptions and +// fr30 traps are both exceptions + +// Common interrupt vectors +#ifndef CYGNUM_HAL_ISR_MIN +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_INTRFIRST +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_INTRLAST +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_VECTOR_NUMINTRS) +#endif +// Common exception vectors. (so these are fr30 exceptions and traps) +#define CYGNUM_HAL_EXCEPTION_RESET CYGNUM_HAL_VECTOR_RESET +#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_COPR_NOT_FOUND +#define CYGNUM_HAL_EXCEPTION_FPU CYGNUM_HAL_VECTOR_COPR_ERROR +#define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_INTE +// #define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_BREAKPOINT +// #define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_STEP_TRACE +#define CYGNUM_HAL_EXCEPTION_SINGLE_STEP CYGNUM_HAL_VECTOR_STEP_TRACE +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_OPCODE + +// common interrupt vectors +// I am sure more defines can be moved from variant to architecture HAL here +#define CYGNUM_HAL_INTERRUPT_NMI 15 + +// here we define exceptions and traps as the fr30 docs termini +#define CYGNUM_HAL_EXCEPTION_FR30_MIN 0 +#define CYGNUM_HAL_EXCEPTION_FR30_MAX 14 +#define CYGNUM_HAL_EXCEPTION_FR30_COUNT (CYGNUM_HAL_EXCEPTION_FR30_MAX - CYGNUM_HAL_EXCEPTION_FR30_MIN + 1) + +#define CYGNUM_HAL_TRAP_FR30_MIN 80 +#define CYGNUM_HAL_TRAP_FR30_MAX 255 +#define CYGNUM_HAL_TRAP_FR30_COUNT (CYGNUM_HAL_TRAP_FR30_MAX - CYGNUM_HAL_TRAP_FR30_MIN + 1) + +// here we define the ecos ones +// nicht mehr aktuell:(calculated from fr30 ones) FIXME maybe have to +// change to correspons to durchgaengig vector numbers. In this table +// exceptions are unterbrochen from interrupts +#define CYGNUM_HAL_EXCEPTION_MIN 0 +#define CYGNUM_HAL_EXCEPTION_MAX 255 +#define CYGNUM_HAL_EXCEPTION_COUNT \ + ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) + +//-------------------------------------------------------------------------- +// Interrupt levels +// Lower numbers mean stronger interrupt levels +// values 0 - 14 are system reserved and can not be set by a program +// (setting them would add 16 to the value automatically) +// value 15 is for NMI +// value 31 disables the interrupt + +#ifndef CYGHWR_HAL_INTERRUPT_LEVELS_DEFINED + +#define CYGNUM_HAL_INTERRUPT_LEVEL_0 16 +#define CYGNUM_HAL_INTERRUPT_LEVEL_1 17 +#define CYGNUM_HAL_INTERRUPT_LEVEL_2 18 +#define CYGNUM_HAL_INTERRUPT_LEVEL_3 19 +#define CYGNUM_HAL_INTERRUPT_LEVEL_4 20 +#define CYGNUM_HAL_INTERRUPT_LEVEL_5 21 +#define CYGNUM_HAL_INTERRUPT_LEVEL_6 22 +#define CYGNUM_HAL_INTERRUPT_LEVEL_7 23 +#define CYGNUM_HAL_INTERRUPT_LEVEL_8 24 +#define CYGNUM_HAL_INTERRUPT_LEVEL_9 25 +#define CYGNUM_HAL_INTERRUPT_LEVEL_10 26 +#define CYGNUM_HAL_INTERRUPT_LEVEL_11 27 +#define CYGNUM_HAL_INTERRUPT_LEVEL_12 28 +#define CYGNUM_HAL_INTERRUPT_LEVEL_13 29 +#define CYGNUM_HAL_INTERRUPT_LEVEL_14 30 +#define CYGNUM_HAL_INTERRUPT_LEVEL_15 31 +#define CYGNUM_HAL_INTERRUPT_LEVEL_DISABLE \ + CYGNUM_HAL_INTERRUPT_LEVEL_15 + +#define CYGHWR_HAL_INTERRUPT_LEVELS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Static data used by HAL + +// ISR tables +externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// VSR table +externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +//-------------------------------------------------------------------------- +// Interrupt state storage + +typedef cyg_uint32 CYG_INTERRUPT_STATE; + +//--------------------------------------------------------------------------- +// Default ISR +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_DEFAULT_ISR hal_default_isr + +//-------------------------------------------------------------------------- +// CPU interrupt enable/disable macros + +#define HAL_ENABLE_INTERRUPTS() \ +CYG_MACRO_START \ + asm volatile ("orccr #0x10;\n") ; \ +CYG_MACRO_END + +#define HAL_DISABLE_INTERRUPTS(_old_) \ +CYG_MACRO_START \ + register int x ; \ + asm volatile ("st r1, @-r15 ;\n" \ + "MOV PS, r1 ;\n" \ + "LDI:8 #0x10,%0 ;\n" \ + "AND r1, %0 ;\n" \ + "LSR #1,%0 ;\n" \ + "ld @r15+, r1 ;\n" \ + "ANDCCR #0xEF \n" \ + : "=r" (x) \ + ); \ + (_old_) = (x); \ +CYG_MACRO_END + +#define HAL_RESTORE_INTERRUPTS(_old_) \ +CYG_MACRO_START \ + register int x = _old_; \ + asm volatile ( "CMP #8, %0 ;\n" \ + "BEQ 0f ;\n" \ + "ANDCCR #0xEF ;\n" \ + "BRA 1f;\n" \ + "0:\n" \ + "ORCCR #0x10 ;\n" \ + "1:\n" \ + : /* No outputs */ \ + : "r"(x) \ + ); \ +CYG_MACRO_END + +// 5th bit (0x10 / #10H) is interrupt flag +// it is shifted right to be able to work with 4 bit immediate in the other macros +#define HAL_QUERY_INTERRUPTS(_old_) \ +CYG_MACRO_START \ + register int x ; \ + asm volatile ("MOV PS,__tmp_reg__ ;\n" \ + "LDI:8 #10H,%0 ;\n" \ + "AND __tmp_reg__,%0 ;\n" \ + "LSR #1,%0 ;\n" \ + : "=r" (x) \ + ); \ + (_old_) = (x); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// Interrupt and VSR attachment macros + + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if (hal_interrupt_handlers[_index_] \ + ==(CYG_ADDRESS)HAL_DEFAULT_ISR) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ + CYG_MACRO_END + +#ifndef HAL_INTERRUPT_ATTACH +externC void __default_interrupt_vsr(void); +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + \ + HAL_VSR_SET( _vector_, &__default_interrupt_vsr , NULL); \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ + { \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)(_isr_); \ + hal_interrupt_data[_index_] = (CYG_ADDRWORD)(_data_); \ + hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_); \ + } \ + CYG_MACRO_END +#endif /* HAL_INTERRUPT_ATTACH */ + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + \ + if (hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS)(_isr_)) \ + { \ + hal_interrupt_handlers[_index_] = \ + (CYG_ADDRESS)HAL_DEFAULT_ISR; \ + hal_interrupt_data[_index_] = 0; \ + hal_interrupt_objects[_index_] = 0; \ + } \ + CYG_MACRO_END + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *((CYG_ADDRESS *)(_pvsr_)) = hal_vsr_table[(_vector_)]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ + CYG_MACRO_START \ + CYG_ADDRESS *__poldvsr = (CYG_ADDRESS *)(_poldvsr_); \ + if( __poldvsr != NULL ) \ + *__poldvsr = hal_vsr_table[(_vector_)]; \ + hal_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_); \ + CYG_MACRO_END + +// This is an ugly name, but what it means is: grab the VSR back to eCos +// internal handling, or if you like, the default handler. But if +// cooperating with GDB and CygMon, the default behaviour is to pass most +// exceptions to CygMon. This macro undoes that so that eCos handles the +// exception. So use it with care. + +externC void __default_exception_vsr(void); +externC void __default_interrupt_vsr(void); + +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \ +CYG_MACRO_START \ + HAL_VSR_SET( _vector_, _vector_ > CYGNUM_HAL_EXCEPTION_MAX \ + ? (CYG_ADDRESS)__default_interrupt_vsr \ + : (CYG_ADDRESS)__default_exception_vsr, \ + _poldvsr_ ); \ +CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Vector translation. +// For chained interrupts we only have a single vector though which all +// are passed. For unchained interrupts we have a vector per interrupt. + +#ifndef HAL_TRANSLATE_VECTOR + +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 + +#else + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) + +#endif + +#endif + +//-------------------------------------------------------------------------- +// Clock control. +// This code uses the 16 bit reload timer 1. The defines are used to specify +// the IO adress of the registers, that are different in FR30 variants. + +#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +extern CYG_WORD32 cyg_hal_clock_period; + +#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED + +#define HAL_CLOCK_INITIALIZE( _period_ ) \ +CYG_MACRO_START \ + HAL_WRITE_UINT16( CYG_HAL_FR30_RTC_TMRLR , _period_); \ + HAL_WRITE_UINT16( CYG_HAL_FR30_RTC_TMCSR , 0x081b); \ + cyg_hal_clock_period = _period_; \ +CYG_MACRO_END + +// This clears the interrupt request for reload timer 1 (RTC) +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ +CYG_MACRO_START \ +asm volatile("ldi:8 #0x57, r0;\n" \ + "bandl #0xb, @r0;\n" \ + : : :"r0"); \ +CYG_MACRO_END + +#define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ + CYG_FAIL("clock_read"); \ + register CYG_WORD32 result; \ + HAL_READ_UINT16( CYG_HAL_FR30_RTC_TMR, result); \ + *(_pvalue_) = cyg_hal_clock_period - result; \ +CYG_MACRO_END + +#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +#endif + + +#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ + !defined(HAL_CLOCK_LATENCY) +#define HAL_CLOCK_LATENCY( _pvalue_ ) \ +CYG_MACRO_START \ + register CYG_WORD32 _cval_; \ + HAL_CLOCK_READ(&_cval_); \ + *(_pvalue_) = _cval_ - cyg_hal_clock_period; \ +CYG_MACRO_END +#endif + +//---------------------------------------------------------------------------- +// Reset +// this clears BIT4 in STCR(0x481), which should issue a reset + +#define HAL_PLATFORM_RESET() \ + asm volatile ( \ + "ldi:20 #0x481, r0;\n" \ + "bandh #1, @r0;\n" \ + : : :"r0"); + +externC void _start(void); +#define HAL_PLATFORM_RESET_ENTRY (&_start) + +//-------------------------------------------------------------------------- +// Microsecond delay +// This uses reload timer 2, because timer 0 and 1 can cause DMA transfers. +// Timer 2 is only used for delay service. We maybe support it out of the +// scheduler clock in the future. + +externC void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(_millis_) hal_delay_us(_millis_); + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_INTR_H +// End of hal_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/include/hal_io.h @@ -0,0 +1,160 @@ +#ifndef CYGONCE_HAL_HAL_IO_H +#define CYGONCE_HAL_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: Define IO register support +// Description: The macros defined here provide the HAL APIs for handling +// device IO control registers. +// +// Usage: +// #include <cyg/hal/hal_io.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_io.h> + +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// HAL IO macros. +#ifndef HAL_IO_MACROS_DEFINED + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + asm volatile ("ldub @%1, %0": "=r" (_value_): "r" (_register_)); +// ((_value_) = *((volatile CYG_BYTE *)(_register_))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + asm volatile ("stb %0, @%1": : "r" (_value_), "r" (_register_)); +// (*((volatile CYG_BYTE *)(_register_)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + asm volatile ("lduh @%1, %0": "=r" (_value_): "r" (_register_)); + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + asm volatile ("sth %0, @%1": : "r" (_value_), "r" (_register_)); + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + asm volatile ("ld @%1, %0": "=r" (_value_): "r" (_register_)); + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + asm volatile ("st %0, @%1": : "r" (_value_), "r" (_register_)); + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +#define HAL_IO_MACROS_DEFINED + +#endif + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_IO_H +// End of hal_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/src/context.S @@ -0,0 +1,201 @@ +##============================================================================= +## +## context.S +## +## FR30 context switch and longjmp setjmp code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors:larsi +## Date: 2006-06-03 +## Purpose: fr30 context switch code +## Description: This file contains implementations of the thread context +## switch routines. It also contains the longjmp() and setjmp() +## routines. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/fr30.inc> + +#include <cyg/hal/arch.inc> + +#------------------------------------------------------------------------------ +# function declaration macro + +#define FUNC_START(name) \ + .globl name; \ +name: + +#------------------------------------------------------------------------------ +# hal_thread_switch_context +# Switch thread contexts +# +# a timer interrupt should have caused this function to be called +# so interrupts are forbidden and we are in SSP mode (S flag=1) +# +# R4 and R5 contain our arguments. +# R5 is _fspptr_ (old USP), R4 is _tspptr_ (new USP). +# @(SSP) has the return address of the call to this function. +# In @(SSP,4) the PS and in @(SSP,8) the PC are saved by hardware. +# Before we RETI, we have to switch S flag in CCR to 0 +# to use SSP for returning. Interrupts have to be +# reenabled before returning, but this is done by restoring PS. + + + .globl hal_thread_switch_context +hal_thread_switch_context: + +# at first switch to USP (set bit 5 in CCR in PS) + st r0, @-r15 ; push last_trap, cannot guarantee that it is + ; the right value, but that should not matter + ; as it is only for GDB + st mdl, @-r15 + st mdh, @-r15 + + st r0, @-r15 ; store usp + + st r0, @-r15 ; store ssp + st rp, @-r15 + st tbr, @-r15 + st ps, @-r15 + st rp, @-r15 ; rp is our new pc when load_context executes + + st r15, @-r15 ; store original r15 here + + stm1 (r8, r9, r10, r11, r12, r13, r14) + stm0 (r0, r1, r2, r3 , r4 , r5 , r6 , r7) + +# we should be finished saving context here + + st r15, @r5 ; store pointer to saved context + +#------------------------------------------------------------------------------ +# hal_thread_load_context +# Load thread context +.globl hal_thread_load_context +hal_thread_load_context: + + ld @r4, r15 + + ldm0 (r0, r1, r2, r3, r4, r5, r6, r7) + ldm1 (r8, r9, r10, r11, r12, r13, r14) + ld @r15+, mdl + ld @r15+, rp + ld @r15+, ps + ld @r15+, tbr +# TODO addsp to skip stack positions + ld @r15+, mdl + ld @r15+, mdl + ld @r15+, mdl + ld @r15+, mdh + ld @r15+, mdl + addsp 4 + ret + +#------------------------------------------------------------------------------ +# HAL longjmp, setjmp implementations +# hal_setjmp saves only to callee save registers r8, r9, r10, r11, r14, r15 +# into buffer supplied in r4 +# Note: These definitions are repeated in hal_arch.h. If changes are required +# remember to update both sets. +# setjmp/longjmp for FR30. The jmpbuf looks like this: +# +# Register jmpbuf offset +# r8 0x00 +# r9 0x04 +# r10 0x08 +# r11 0x0c +# r14 (FP) 0x10 +# r15 (SP) 0x14 +# pc (rp) 0x18 + + .macro save reg + st \reg, @r4 + addn #4, r4 + .endm + + .macro restore reg + ld @r4, \reg + addn #4, r4 + .endm + + + .text + .global hal_setjmp + .type hal_setjmp,@function +hal_setjmp: + save r8 + save r9 + save r10 + save r11 + save r14 + save r15 + mov rp, r5 + st r5, @r4 + +# Return 0 to caller. + ldi:8 #0, r4 + ret + + .global hal_longjmp +hal_longjmp: + restore r8 + restore r9 + restore r10 + restore r11 + restore r14 + restore r15 + ld @r4, r4 + mov r4, rp + +# If caller attempted to return 0, return 1 instead. + + mov r5, r4 + or r4, r4 + bne 1f + ldi:8 #1, r4 +1: + ret + +#----------------------------------------------------------------------------- +# End of context.S
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/src/fr30_stub.c @@ -0,0 +1,210 @@ +//======================================================================== +// +// fr30_stub.c +// +// Fujitsu FR30-specific code for remote debugging via gdb +// +//======================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: +// Description: Helper functions for gdb stub for FR30 processors +// Usage: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <stddef.h> + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/infra/cyg_ass.h> // assertion macros + +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT +#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id +#endif + +/* Given a trap value TRAP, return the corresponding signal. */ + +int __computeSignal (unsigned int trap_number) +{ + switch (trap_number) + { + + case CYGNUM_HAL_VECTOR_COPR_NOT_FOUND: + case CYGNUM_HAL_VECTOR_COPR_ERROR: + return SIGFPE; + + // step trace TRAP + case CYGNUM_HAL_VECTOR_DEBUG: + // INTE + case CYGNUM_HAL_VECTOR_BREAKPOINT: + return SIGTRAP; + /* System call instruction executed */ + case CYGNUM_HAL_VECTOR_SYSTEM_CALL ... CYGNUM_HAL_VECTOR_TRAPLAST: + return SIGSYS; + /* External interrupt */ + case CYGNUM_HAL_INTERRUPT_0 ... CYGNUM_HAL_INTERRUPT_DELAYED_IRQ: + return SIGINT; + // Illegal or reserved instruction + case CYGNUM_HAL_VECTOR_OPCODE: + return SIGILL; + + // Marks port does think to return SIGTRAP as default. + default: + return SIGTERM; + } +} + +/* Return the trap number corresponding to the last-taken trap. */ + +int __get_trap_number (void) +{ + // The vector is not not part of the GDB register set so get it + // directly from the save context. + return _hal_registers->last_trap; +} + +/* Set the currently-saved pc register value to PC. This also updates NPC + as needed. */ + +void set_pc (target_register_t pc) +{ + put_register (PC, pc); +} + +/*---------------------------------------------------------------------- + * Single-step support + */ + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ + +void __single_step (void) +{ + /* Trying to use processors single stepping. + This means to set T flag in PS register. */ + put_register (PS, get_register (PS) | 0x100); +} + +/* Clear the single-step state. */ +void __clear_single_step (void) +{ + put_register (PS, get_register (PS) & ~0x100); +} + +void __install_breakpoints () +{ + /* if (instrBuffer.targetAddr != NULL) + { + instrBuffer.savedInstr = *instrBuffer.targetAddr; + *instrBuffer.targetAddr = __break_opcode (); + } */ + + /* Install the breakpoints in the breakpoint list */ + __install_breakpoint_list(); + + // No need to flush caches here; Generic stub code will handle this. +} + +void __clear_breakpoints (void) +{ + __clear_breakpoint_list(); +} + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ + +int +__is_breakpoint_function () +{ + return get_register (PC) == (target_register_t)&_breakinst; +} + +/* Skip the current instruction. Since this is only called by the + stub when the PC points to a breakpoint or trap instruction, + we can safely just skip 2. */ + +void __skipinst (void) +{ + put_register (PC, get_register (PC) + 2); +} + +/* Get a register out of the GDB register structure */ +target_register_t +get_register (regnames_t reg) +{ + GDB_Registers* gdb_regs; + + gdb_regs = (GDB_Registers*)_registers; + + if (reg >= R0 && reg <= MDL) + return gdb_regs->r[reg]; + + return 0xdeadbeef; +} + +/* Put a register into the GDB register structure */ +void +put_register (regnames_t reg, target_register_t value) +{ + GDB_Registers* gdb_regs; + + gdb_regs = (GDB_Registers*)_registers; + + if (reg >= R0 && reg <= MDL) { + gdb_regs->r[reg] = value; + } else { + CYG_FAIL("Attempt to write to non-existent register "); + } +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +// EOF openrisc_stub.c
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/src/hal_misc.c @@ -0,0 +1,245 @@ +//========================================================================== +// +// hal_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // VSR/ISR defines +#include <cyg/hal/hal_misc.h> + +/*------------------------------------------------------------------------*/ +/* If required, define a variable to store the clock period. */ + +#ifdef CYGHWR_HAL_CLOCK_PERIOD_DEFINED + +CYG_WORD32 cyg_hal_clock_period; + +#endif + + +/***************************************************************************** +hal_default_exception_handler -- First level C exception handler + + The assembly default VSR handler calls this routine to handle the +exception. When this routine returns, the state is restored to the state +pointed to by regs. + + We declare this routine as weak so that other handlers can easily +become the default exception handler. + +INPUT: + + vector: The exception vector number. + + regs: A pointer to the saved state. + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ + +externC void +hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs) + __attribute__ ((weak)); + +void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs) +{ + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + externC void __handle_exception(void); + externC HAL_SavedRegisters * _hal_registers; + + // Set the pointer to the registers of the current exception + // context. At entry the GDB stub will expand the + // HAL_SavedRegisters structure into a (bigger) register array. + _hal_registers = regs; + + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + + // We should decode the vector and pass a more appropriate + // value as the second argument. For now we simply pass a + // pointer to the saved registers. We should also divert + // breakpoint and other debug vectors into the debug stubs. + + cyg_hal_deliver_exception(vector, (CYG_ADDRWORD)regs); + +#else + + CYG_FAIL("Exception!!!"); + +#endif + + return; +} + +//--------------------------------------------------------------------------- +// Default arch ISR + +externC cyg_uint32 +hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_FAIL("Spurious Interrupt!!!"); + return 0; +} + +//--------------------------------------------------------------------------- +// Idle thread action + +void +hal_idle_thread_action( cyg_uint32 count ) +{ +} + +//----------------------------------------------------------------------------- +// Monitor initialization. This means to init the vsr vector table. +// TODO maybe init hal_vsr_table through defining it in assembler code + +#ifndef CYGPKG_HAL_FR30_MON_DEFINED +void hal_mon_init(void){ + int i; + /* 0 - 14 exceptions */ + for(i = 0; i < CYGNUM_HAL_VECTOR_INTRFIRST; i++){ + hal_vsr_table[i] = (CYG_ADDRESS)__default_exception_vsr; + } + /* 15 - xx interrupts */ + for( ; i < CYGNUM_HAL_VECTOR_INTRLAST; i++){ + hal_vsr_table[i] = (CYG_ADDRESS)__default_interrupt_vsr; + } + /* xx+1 - 255 exceptions (fr30 traps) */ + for( ; i < CYGNUM_HAL_VSR_MAX; i++){ + hal_vsr_table[i] = (CYG_ADDRESS)__default_exception_vsr; + } +} +#endif + +//--------------------------------------------------------------------------- +// Determine the index of the ls bit of the supplied mask. + +cyg_uint32 +hal_lsbit_index(cyg_uint32 mask) +{ + cyg_uint32 n = mask; + + static const signed char tab[64] = + { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, + 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, + 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, + 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 + }; + + n &= ~(n-1UL); + n = (n<<16)-n; + n = (n<<6)+n; + n = (n<<4)+n; + + return tab[n>>26]; +} + +//--------------------------------------------------------------------------- +// Determine the index of the ms bit of the supplied mask. FIXME: since we +// have hardware support for it, use it! (bit search module) + +cyg_uint32 +hal_msbit_index(cyg_uint32 mask) +{ + cyg_uint32 x = mask; + cyg_uint32 w; + + // Phase 1: make word with all ones from that one to the right. + x |= x >> 16; + x |= x >> 8; + x |= x >> 4; + x |= x >> 2; + x |= x >> 1; + + // Phase 2: calculate number of "1" bits in the word. + w = (x & 0x55555555) + ((x >> 1) & 0x55555555); + w = (w & 0x33333333) + ((w >> 2) & 0x33333333); + w = w + (w >> 4); + w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); + return (cyg_uint32)((w + (w >> 16)) & 0xFF); + +} + +/*------------------------------------------------------------------------*/ +/* C++ support - run initial constructors */ + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +typedef void (*pfunc) (void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +void + cyg_hal_invoke_constructors (void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) { + (*p) (); + } +#endif +} + +//---------------------------------------------------------------------------
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/arch/current/src/vectors.S @@ -0,0 +1,564 @@ +##============================================================================= +## +## vectors.S +## +## fr30 startup code and exception and interrupt vectors +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors:larsi +## Date: 2006-06-26 +## Purpose: fr30 exception vectors +## Description: This file defines the code placed into the exception +## vectors. It also contains the startup code and first +## level default VSRs that save and restore state for +## both exceptions and interrupts. +## +######DESCRIPTIONEND#### +## +##============================================================================= + + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif /* CYGPKG_KERNEL */ + +#include <cyg/hal/arch.inc> + +#============================================================================== + + .file "vectors.S" + +#============================================================================== +# Real startup code. We jump here from the various reset vectors to set up the +# world. + + .text + .globl _start + +_start: + +# disable interrupts and set priority to lowest (=disable) + andccr #0xef + stilm #0x0 + + hal_diag_init_led +#ifdef CYGPKG_HAL_FR30_FLASH_INIT_DEFINED + hal_flash_init +#endif + hal_cpu_init + +#ifdef CYGPKG_HAL_FR30_MEMC_INIT_DEFINED + hal_memc_init +#endif + + hal_intc_init + + hal_cache_init + + hal_timer_init + +# Zero the BSS. If the BSS is not a whole number of words +# long we will write up to 3 extra bytes at the end. +# (This should not be a problem usually). + ldi:32 #__bss_end - 8, r12 + ldi:32 #__bss_start - 4, r13 + eor r0, r0 ; zero r0 +2: + add #0x4, r13 + cmp r12, r13 + ble:d 2b + st r0, @r13 + + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + +# In a ROM booted system, we also need to copy the data section +# out to the RAM. + ldi:32 #__rom_data_start - 4, r11 + ldi:32 #__ram_data_start - 4, r13 + ldi:32 #__ram_data_end - 8, r12 +3: + add #0x4, r11 + add #0x4, r13 + ld @r11, r0 + cmp r12, r13 + ble:d 3b + st r0, @r13 + +#endif + + # Set up the stacks + # Begin with interrupt (system) stack + + ldi:32 #__interrupt_stack, r11 + mov r11, ssp + + # and now continue with user stack + + orccr #0x20 + ldi:32 #__user_stack, r11 + mov r11, usp + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +# If we are here, initialize the hal_vsr_table. RAM startup +# configurations can assume that Redboot has already set it up. + + .extern hal_mon_init + ldi:32 #hal_mon_init, r11 + call @r11 + +#endif + + .extern hal_variant_init + ldi:32 #hal_variant_init, r11 + call @r11 + + .extern hal_platform_init + ldi:32 #hal_platform_init, r11 + call @r11 + + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + // This is here so we can debug the constructors. + .extern initialize_stub + ldi:32 #initialize_stub, r11 + call @r11 +#endif + + .extern cyg_hal_invoke_constructors + ldi:32 #cyg_hal_invoke_constructors, r11 + call @r11 + +# TODO integrate into hal_intr.h +# set irq 25 priority (for reload timer 1) + ldi:20 #0x449, r4 + ldi:8 #0x10, r5 + stb r5, @r4 + +#ifdef CYGDBG_HAL_DEBUG_GDB_INITIAL_BREAK + .extern breakpoint + call breakpoint +#endif + + .extern cyg_start + ldi:32 #cyg_start, r11 + call @r11 + +# Hmm. Not expecting to return from cyg_start, endless nop loop +1: nop + call 1b + +#============================================================================== +# Default exception VSR + + .align 2, 0xcc + .globl __default_exception_vsr +__default_exception_vsr: + + ## We enter here with the CPU state still in the registers and: + ## @(ssp,8) PS pushed by hardware + ## @(ssp,4) PC pushed by hardware + ## @(ssp) old register r0 content pushed by trampoline + ## r0 now contains the vector number + +# at first switch to USP (set bit 5 in CCR in PS) + orccr #0x20 + + st r0, @-r15 + st mdl, @-r15 + st mdh, @-r15 + + mov r0, mdh ; save exception/interrupt number + mov r15, r0 + addn #+12, r0 + mov r0, mdl ; save r15 also in mdl + + st r0, @-r15 ; store usp + mov ssp, r0 + st r0, @-r15 ; store ssp (TODO maybe have to sub 12 before) + st rp, @-r15 + st tbr, @-r15 + addsp #-8 ; skip 2 positions for PS and PC + mov r15, r0 ; save stack position to later store PS and PC + + st mdl, @-r15 ; store original r15 here + stm1 (r8, r9, r10, r11, r12, r13, r14) + stm0 (r1, r2, r3, r4, r5, r6, r7) + + mov ssp, r14 + ld @r14, r1 ; get original r0 content + st r1, @-r15 ; and store it + + ld @(r14,4), r2 ; get hardware pushed PC + st r2, @r0 ; and store it + ld @(r14,8), r3 ; get hardware pushed PS + addn #4, r0 ; and + st r3, @r0 ; store it + +# we should be finished saving context here + +# Call exception handler + .extern hal_default_exception_handler + + ldi:32 #hal_default_exception_handler, r11 + mov r15, r5 ; pointer to saved state as second argument + call:d @r11 + mov mdh, r4 ; exception number as first argument + +__default_exception_vsr_return: + + + ## At this point, the user stack (USP) contains: + ## @(usp,0x60) trap number + ## @(usp,0x5c) mdl + ## @(usp,0x58) mdh + ## @(usp,0x54) usp + ## @(usp,0x50) ssp + ## @(usp,0x4c) rp + ## @(usp,0x48) tbr + ## @(usp,0x44) ps + ## @(usp,0x40) pc + ## @(usp,0x3c) r15 + ## @(usp,0x38) r14 + ## @(usp,0x34) r13 + ## @(usp,0x30) r12 + ## @(usp,0x2c) r11 + ## @(usp,0x28) r10 + ## @(usp,0x24) r9 + ## @(usp,0x20) r8 + ## @(usp,0x1c) r7 + ## @(usp,0x18) r6 + ## @(usp,0x14) r5 + ## @(usp,0x10) r4 + ## @(usp,0xc) r3 + ## @(usp,8) r2 + ## @(usp,4) r1 + ## @(usp) r0 + ## + ## and system stack (SSP) contains: + ## @(ssp,8) PS + ## @(ssp,4) PC + ## @(ssp) old r0 content + +# we can reuse the code from __default_interrupt_vsr + ldi:32 #hal_exception_return, r0 + jmp @r0 + +#============================================================================== +# Default interrupt VSR +# +# + + .align 2, 0xcc + .globl __default_interrupt_vsr +__default_interrupt_vsr: + + ## We enter here with the CPU state still in the registers and: + ## r0 vector number + ## @(ssp) old register r0 content pushed by trampoline + ## @(ssp,4) PS pushed by hardware + ## @(ssp,8) PC pushed by hardware + + # begin to save registers (to USP) + orccr #0x20 + + st mdl, @-r15 + st mdh, @-r15 + st rp, @-r15 + + stm1 (r8, r9, r10, r11, r12, r13) + stm0 (r1, r2, r3 , r4 , r5 , r6, r7) + + andccr #0xdf + ld @r15+, r8 ; read old r0 content from SSP + ld @r15+, r9 ; read pc pushed by hardware + ld @r15+, r10 ; read ps pushed by hardware + orccr #0x20 + + st r8, @-r15 ; push old r0 content to USP + +# we should be finished saving irq context here + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) +# Increment scheduler lock + .extern cyg_scheduler_sched_lock + ldi:32 #cyg_scheduler_sched_lock, r1 + ld @r1, r2 + addn #1, r2 + st r2, @r1 +#endif + +# Call hal_interrupt_handlers[vector](vector, cyg_hal_interrupt_data[vector]) + mov r0, r8 ; copy the vector + lsl #2, r8 ; multiply vector by 4 + + ldi:32 #hal_interrupt_handlers, r13 ; load handlers table + ld @(r13, r8), r1 ; current handler + ldi:32 #hal_interrupt_data, r13 ; load data table + ld @(r13, r8), r5 ; current data, second argument + call:d @r1 + mov r0, r4 ; exception number as argument + +# At this point: +# r15 = stack pointer /*(should be usable as pointer to HAL_SavedRegisters)*/ +# r4 = ISR return code (returned by call) +# r8 = ISR table offset (saved across call) +# r0 = vector number (NOT saved across call, but we don't need it) + +/* + # If we are returning from the last nested interrupt, move back + # to the thread stack. interrupt_end() must be called on the + # thread stack since it potentially causes a context switch. + + hal_from_intstack +*/ + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + +# Call interrupt_end(return_value, hal_interrupt_objects[vector], regs) +# - r4 is the return value from the ISR +# - regs points to saved CPU context + + ldi:32 #hal_interrupt_objects, r13 ; load objects table + ld @(r13, r8), r5 ; current object, second argument + ldi:32 #interrupt_end, r12 + call:d @r12 + mov r15, r6 ; third argument TODO is not in + ; HAL_Saved_Registers format + +#endif + +##.globl hal_exception_return +hal_exception_return: + +# Now pull saved state from stack and return to +# what thread was originally doing. + +# at first store return values to SSP + andccr #0xdf + st r10, @-r15 ; store ps + st r9, @-r15 ; store pc + orccr #0x20 + +# and then restore normal registers from USP + ldm0 (r0, r1, r2 , r3 , r4 , r5, r6, r7) + ldm1 (r8, r9, r10, r11, r12, r13) + + ld @r15+, rp + ld @r15+, mdh + ld @r15+, mdl + + andccr #0xdf + reti + +#============================================================================== +# Exception trampolines +# TBR table points to these short code sequences here that push the vector +# number on to the stack and then indirect via the VSR table to a handler. +# (__default_interrupt_vsr) + + .text + +# macro to create exception handler (no error code) + +.macro hal_fr30_exception_noerr idx + .globl hal_fr30_exception_noerr_\idx +hal_fr30_exception_noerr_\idx: + st r0, @-r15 + ldi:32 #hal_vsr_table + \idx * 4, r0 + ld @r0, r0 + jmp:d @r0 + ldi:8 #\idx, r0 +.endm + + # Now generate all the default exception VSR trampolines. + +# hal_fr30_exception_noerr 1 no trampoline needed for reset and mode vector + hal_fr30_exception_noerr 2 + hal_fr30_exception_noerr 3 + hal_fr30_exception_noerr 4 + hal_fr30_exception_noerr 5 + hal_fr30_exception_noerr 6 + hal_fr30_exception_noerr 7 + hal_fr30_exception_noerr 8 + hal_fr30_exception_noerr 9 + hal_fr30_exception_noerr 10 + hal_fr30_exception_noerr 11 + hal_fr30_exception_noerr 12 + hal_fr30_exception_noerr 13 + hal_fr30_exception_noerr 14 + +#============================================================================== +# IRQ handler trampolines + +# macro to create exception handler (no error code) + +.macro hal_fr30_irq_handler idx + .globl hal_fr30_irq_\idx +hal_fr30_irq_\idx: + st r0, @-r15 + ldi:32 #hal_vsr_table + \idx * 4, r0 + ld @r0, r0 + jmp:d @r0 + ldi:8 #\idx, r0 +.endm + + hal_fr30_irq_handler 15 + hal_fr30_irq_handler 16 + hal_fr30_irq_handler 17 + hal_fr30_irq_handler 18 + hal_fr30_irq_handler 19 + hal_fr30_irq_handler 20 + hal_fr30_irq_handler 21 + hal_fr30_irq_handler 22 + hal_fr30_irq_handler 23 + hal_fr30_irq_handler 24 + hal_fr30_irq_handler 25 + hal_fr30_irq_handler 26 + hal_fr30_irq_handler 27 + hal_fr30_irq_handler 28 + hal_fr30_irq_handler 29 + hal_fr30_irq_handler 30 + hal_fr30_irq_handler 31 + hal_fr30_irq_handler 32 + hal_fr30_irq_handler 33 + hal_fr30_irq_handler 34 + hal_fr30_irq_handler 35 + hal_fr30_irq_handler 36 + hal_fr30_irq_handler 37 + hal_fr30_irq_handler 38 + hal_fr30_irq_handler 39 + hal_fr30_irq_handler 40 + hal_fr30_irq_handler 41 + hal_fr30_irq_handler 42 + hal_fr30_irq_handler 43 + hal_fr30_irq_handler 44 + hal_fr30_irq_handler 45 + hal_fr30_irq_handler 46 + hal_fr30_irq_handler 47 + hal_fr30_irq_handler 48 + hal_fr30_irq_handler 49 + hal_fr30_irq_handler 50 + hal_fr30_irq_handler 51 + hal_fr30_irq_handler 52 + hal_fr30_irq_handler 53 + hal_fr30_irq_handler 54 + hal_fr30_irq_handler 55 + hal_fr30_irq_handler 56 + hal_fr30_irq_handler 57 + hal_fr30_irq_handler 58 + hal_fr30_irq_handler 59 + hal_fr30_irq_handler 60 + hal_fr30_irq_handler 61 + hal_fr30_irq_handler 62 + hal_fr30_irq_handler 63 + + + .data +// +// "Vectors" - fixed location data items +// This section contains any data which might be shared between +// an eCos application and any other environment, e.g. the debug +// ROM. +// + .section ".fixed_vectors" +// Space for the virtual vectors + .balign 4 +// Vectors used to communicate between eCos and ROM environments + .globl hal_virtual_vector_table +hal_virtual_vector_table: + .rept 64 // CYGNUM_CALL_IF_TABLE_SIZE + .long 0 + .endr + + .globl hal_vsr_table +hal_vsr_table: + .rept CYGNUM_HAL_VSR_COUNT // exceptions & interrupts + .long 0 + .endr + +#============================================================================== +# Initial and interrupt stack + + .section ".bss" + + .balign 4 + .global cyg_interrupt_stack_base +cyg_interrupt_stack_base: +__interrupt_stack_base: + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 4 + .global cyg_interrupt_stack +cyg_interrupt_stack: +__interrupt_stack: + .long 0,0,0,0,0,0,0,0 + + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + .global __stub_stack_base +__stub_stack_base: + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 4 + .global __stub_stack +__stub_stack: + + .long 0,0,0,0,0,0,0,0 +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + .balign 4 +__user_stack_base: +// FIXME TODO import symbolic constant from C-code + .rept 4532 + .byte 0 + .endr + .balign 4 +__user_stack: + .long 0 + +#------------------------------------------------------------------------------ +# end of vectors.S
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/ChangeLog @@ -0,0 +1,45 @@ +2007-07-09 Lars Poeschel <larsi@wh2.tu-dresden.de> + + * src/fr30_md91301.ld: + * src/hal_diag.c: + * src/var_misc.c: + * include/hal_diag.h: + * include/var_arch.h: + * include/variant.inc: + * include/var_intr.h: + * cdl/hal_fr30_mb91301.cdl: Initial fr30 ecos port + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/cdl/hal_fr30_mb91301.cdl @@ -0,0 +1,192 @@ +# ==================================================================== +# +# hal_fr30_mb91301.cdl +# +# FR30/mb91301 variant architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): larsi +# Original data: bartv, nickg +# Contributors: +# Date: 2006-07-09 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_FR30_MB91301 { + display "MB91301 variant" + parent CYGPKG_HAL_FR30 + implements CYGINT_HAL_FR30_VARIANT + hardware + include_dir cyg/hal + define_header hal_fr30_mb91301.h + description " + The MB91301 architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_fr30.h>" + } + + cdl_component CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ { + display "System clock speed in MHz" + flavor data + calculated { (CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED * \ + CYGHWR_HAL_FR30_MB91301_CLKR) } + description "This is the resulting base clock speed for the board. + It is calculated + CLKR * CRYSTAL_SPEED. + This is NOT the CPU Frequency." + + cdl_option CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED { + display "Crystal speed in Mhz" + flavor data + description "You have to enter the speed of the mounted crystal here. + The resulting base clock is calculated: + CLKR * CRYSTAL_SPEED / CLKB_DIVIDER" + legal_values 1 to 17 + default_value 15 + } + + cdl_option CYGHWR_HAL_FR30_MB91301_CLKR { + display "Main PLL multiply-by rate" + flavor data + description "Using this value you can set the resulting base clock + speed. It is calculated: + CLKR * CRYSTAL_SPEED. + DO NOT DO A SETTING HIGHER THAN 4 UNLESS YOU EXACTLY + KNOW WHAT YOU A DOING! " + legal_values 1 to 8 + default_value 4 + } + + cdl_option CYGHWR_HAL_FR30_MB91301_CLKB_DIVIDER { + display "Base clock divider" + flavor data + description "Using this value you can limit the base clock speed. + You set the divider. The resulting base clock speed + is calculated: + CLKB = system clock / divider + CPU, internal memory and internal buses use this base clock! + A value other than 1 can cause problems when using the stop + mode of the CPU. + See Fujitsu MB91301 hardware manual Chapter 5 for + constraints on setting this value!" + legal_values 1 to 16 + default_value 1 + } + + cdl_option CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER { + display "Peripheral clock divider" + flavor data + description "Using this value you can set the peripheral clock + speed. You set the divider. The resulting peripheral clock + speed is calculated: + CLKP = system clock / divider + See Fujitsu MB91301 hardware manual Chapter 5 for constraints on setting + this value!" + legal_values 1 to 16 + default_value 4 + } + + cdl_option CYGHWR_HAL_FR30_MB91301_CLKT_DIVIDER { + display "External buses clock divider" + flavor data + description "Using this value you can set the external buses clock + speed. You set the divider. The resulting external buses + clock speed is calculated: + CLKT = system clock / divider + See Fujitsu MB91301 hardware manual Chapter 5 for constraints on setting + this value!" + legal_values 1 to 16 + default_value 1 + } + + } + + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value {(CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED * CYGHWR_HAL_FR30_MB91301_CLKR * 1000000) / (CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER * CYGNUM_HAL_RTC_DENOMINATOR * 32)} + description " + The tick timer facility is used + to drive the eCos kernel RTC. Reload Timer 1 is used. The count + register decrements at the CLKP clock speed. We use prescaler 32. + By default we want 100 Hz." + } + } + + + compile hal_diag.c var_misc.c variant.S + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/fr30_mb91301.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/fr30_mb91301.ld" } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/include/hal_diag.h @@ -0,0 +1,128 @@ +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + + +#else // old way of doing diagnostic I/O + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c (old way without virtual vectors) */ + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() hal_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif /* CYGSEM_HAL_VIRTUAL_VECTOR_DIAG */ + +/*---------------------------------------------------------------------------*/ +// serial port0 defines +#define CYG_HAL_FR30_MB91301_SMR0 0x63 +#define CYG_HAL_FR30_MB91301_SCR0 0x62 +#define CYG_HAL_FR30_MB91301_SIDR0 0x61 +#define CYG_HAL_FR30_MB91301_SODR0 0x61 +#define CYG_HAL_FR30_MB91301_SSR0 0x60 +#define CYG_HAL_FR30_MB91301_UTIM0 0x64 +#define CYG_HAL_FR30_MB91301_UTIMR0 0x64 +#define CYG_HAL_FR30_MB91301_DRCL0 0x66 +#define CYG_HAL_FR30_MB91301_UTIMC0 0x67 + +/*---------------------------------------------------------------------------*/ +// serial port1 defines +#define CYG_HAL_FR30_MB91301_SMR1 0x6b +#define CYG_HAL_FR30_MB91301_SCR1 0x6a +#define CYG_HAL_FR30_MB91301_SIDR1 0x69 +#define CYG_HAL_FR30_MB91301_SODR1 0x69 +#define CYG_HAL_FR30_MB91301_SSR1 0x68 +#define CYG_HAL_FR30_MB91301_UTIM1 0x6c +#define CYG_HAL_FR30_MB91301_UTIMR1 0x6c +#define CYG_HAL_FR30_MB91301_DRCL1 0x6e +#define CYG_HAL_FR30_MB91301_UTIMC1 0x6f + +#define CYG_HAL_FR30_MB91301_PDRJ 0x13 +#define CYG_HAL_FR30_MB91301_DDRJ 0x403 +#define CYG_HAL_FR30_MB91301_PFRJ 0x413 + +/*---------------------------------------------------------------------------*/ +// LED +#define CYG_HAL_FR30_MB91301_PDRG 0x10 +#define CYG_HAL_FR30_MB91301_DDRG 0x400 +#define CYG_HAL_FR30_MB91301_PFRG 0x410 +// our MB91302A does not have PCRG (pull up resistor register G) +// but it is here anyway +#define CYG_HAL_FR30_MB91301_PCRG 0x420 + +// externC void hal_diag_init_led(void); +externC void hal_diag_led(cyg_uint8); + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/include/var_arch.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//========================================================================== +// +// var_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: Define architecture abstractions +// Description: This file contains any extra or modified definitions for +// this variant of the architecture. +// Usage: #include <cyg/hal/var_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// End of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/include/var_intr.h @@ -0,0 +1,275 @@ +#ifndef CYGONCE_HAL_IMP_INTR_H +#define CYGONCE_HAL_IMP_INTR_H + +//========================================================================== +// +// var_intr.h +// +// MB91301 Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: larsi +// Date: 2006-07-14 +// Purpose: MB91301 Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for variants of the MB91301 +// architecture. +// +// Usage: +// #include <cyg/hal/imp_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_intr.h> + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#define CYGNUM_HAL_INTERRUPT_0 16 +#define CYGNUM_HAL_INTERRUPT_1 17 +#define CYGNUM_HAL_INTERRUPT_2 18 +#define CYGNUM_HAL_INTERRUPT_3 19 +#define CYGNUM_HAL_INTERRUPT_4 20 +#define CYGNUM_HAL_INTERRUPT_5 21 +#define CYGNUM_HAL_INTERRUPT_6 22 +#define CYGNUM_HAL_INTERRUPT_7 23 +#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER0 24 +#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1 25 +#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER2 26 +#define CYGNUM_HAL_INTERRUPT_UART0_RX 27 +#define CYGNUM_HAL_INTERRUPT_UART1_RX 28 +#define CYGNUM_HAL_INTERRUPT_UART2_RX 29 +#define CYGNUM_HAL_INTERRUPT_UART0_TX 30 +#define CYGNUM_HAL_INTERRUPT_UART1_TX 31 +#define CYGNUM_HAL_INTERRUPT_UART2_TX 32 +#define CYGNUM_HAL_INTERRUPT_DMAC0 33 +#define CYGNUM_HAL_INTERRUPT_DMAC1 34 +#define CYGNUM_HAL_INTERRUPT_DMAC2 35 +#define CYGNUM_HAL_INTERRUPT_DMAC3 36 +#define CYGNUM_HAL_INTERRUPT_DMAC4 37 +#define CYGNUM_HAL_INTERRUPT_AD 38 +#define CYGNUM_HAL_INTERRUPT_PPG0 39 +#define CYGNUM_HAL_INTERRUPT_PPG1 40 +#define CYGNUM_HAL_INTERRUPT_PPG2 41 +#define CYGNUM_HAL_INTERRUPT_PPG3 42 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 43 +#define CYGNUM_HAL_INTERRUPT_UTIMER0 44 +#define CYGNUM_HAL_INTERRUPT_UTIMER1 45 +#define CYGNUM_HAL_INTERRUPT_UTIMER2 46 +#define CYGNUM_HAL_INTERRUPT_TIMEBASE_OVERFLOW 47 +#define CYGNUM_HAL_INTERRUPT_I2C0 48 +#define CYGNUM_HAL_INTERRUPT_I2C1 49 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 50 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 51 +#define CYGNUM_HAL_INTERRUPT_FREERUN_TIMER 52 +#define CYGNUM_HAL_INTERRUPT_ICU0 53 +#define CYGNUM_HAL_INTERRUPT_ICU1 54 +#define CYGNUM_HAL_INTERRUPT_ICU2 55 +#define CYGNUM_HAL_INTERRUPT_ICU3 56 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 57 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 58 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 59 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 60 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 61 +// system reserved #define CYGNUM_HAL_INTERRUPT_ 62 +#define CYGNUM_HAL_INTERRUPT_DELAYED_IRQ 63 + +// The interrupt vector used by the RTC, aka tick timer +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1 + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Interrupt controller access. + +// currently only external interrupts are masked using the external +// interrupt controller. This means only vectors 16 to 23 are valid. +// Other interrupts may be masked in the future +// using the mask mechanism for interrupt levels, if needed. + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#define CYG_HAL_FR30_MB91301_ENIR 0x41 +#define CYG_HAL_FR30_MB91301_EIRR 0x40 +#define CYG_HAL_FR30_MB91301_ELVR 0x42 +#define CYG_HAL_FR30_MB91301_ICR00 0x440 + +// Array which stores the configured priority levels for the configured +// interrupts. +// this will be useful, if we implement masking of non external interrupts +// externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + + +#define HAL_INTERRUPT_MASK( _vector_ ) \ +{ \ + CYG_WORD32 _ilr_; \ + if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \ + (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \ + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \ + _ilr_ &= ~(1<<((_vector_)>>4)); \ + HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \ + } \ + /* Handle RTC masking special */ \ + if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \ + asm volatile("ldi:8 #0x57, r0;\n" \ + "bandl #0x7, @r0;\n" \ + : : :"r0"); \ +} + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ +{ \ + CYG_WORD32 _ilr_; \ + if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \ + (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \ + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \ + _ilr_ |= (1<<((_vector_)>>4)); \ + HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \ + } \ + /* Handle RTC unmasking special */ \ + if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \ + asm volatile("ldi:8 #0x57, r0;\n" \ + "borl #0x8, @r0;\n" \ + : : :"r0"); \ +} + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +{ \ + CYG_WORD32 _ilr_; \ + if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \ + (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \ + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ ); \ + _ilr_ &= ~(1<<((_vector_)>>4)); \ + HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ ); \ + } \ + /* Handle RTC acknowledging special */ \ + if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \ + asm volatile("ldi:8 #0x57, r0;\n" \ + "bandl #0xb, @r0;\n" \ + : : :"r0"); \ +} + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ +{ \ + /* subtract 15 from vector */ \ + cyg_uint32 _v_ = _vector_ >> 4; \ + cyg_uint16 _val_ = 0; \ + cyg_uint16 _reg_; \ + \ + if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \ + (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \ + \ + /* set bits according to requirements */ \ + if( _up_ ) _val_ |= 1; \ + if( !(_level_) ) _val_ |= 2; \ + \ + /* get old ELVR */ \ + HAL_READ_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ ); \ + \ + /* clear old value and set new */ \ + _reg_ &= ~(3 << _v_); \ + _reg_ |= _val_ << _v_; \ + HAL_WRITE_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ ); \ + } \ +} + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ +{ \ + /* subtract 15 from vector */ \ + cyg_uint32 _v_ = _vector_ >> 4; \ + CYG_WORD32 _ilr_; \ +/* HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ );*/ \ +/* reading before writing is only needed, if UINT8 writing is not */ \ +/* possible to IO 0x440 */ \ + _ilr_ = (_level_); \ + HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ ); \ +/* for later use: */ \ +/* hal_interrupt_level[_vector_] = _level_; */ \ +} + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Clock control registers + +// MB91301 series has 3 built-in timer channels. +// Timer 2 is used for delay and timer 1 for RTC/*delay*/. +// Timer 0 and 1 can activate DMA and this feature is propably needed by +// the application. Timer 0 is free to use by the application. + +#define CYG_HAL_FR30_DLY_TMCSR 0x5e +#define CYG_HAL_FR30_DLY_TMR 0x5a +#define CYG_HAL_FR30_DLY_TMRLR 0x58 +#define CYG_HAL_FR30_RTC_TMCSR 0x56 +#define CYG_HAL_FR30_RTC_TMR 0x52 +#define CYG_HAL_FR30_RTC_TMRLR 0x50 + + + +//-------------------------------------------------------------------------- +// Control-C support. + +#if defined(CYGDBG_HAL_FR30_DEBUG_GDB_CTRLC_SUPPORT) + +#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART + +externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_CTRLC_ISR hal_ctrlc_isr + +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_IMP_INTR_H +// End of imp_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/include/variant.inc @@ -0,0 +1,331 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## MB91301 family assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors:larsi +## Date: 2006-07-24 +## Purpose: MB91301 family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the TX39 CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/fr30.inc> + +#include <cyg/hal/platform.inc> + +##----------------------------------------------------------------------------- +## Define CPU variant for architecture HAL. + +#define CYG_HAL_FR30_MB91301 + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +#ifndef CYG_HAL_FR30_ISR_TABLES_DEFINED +#define CYG_HAL_FR30_ISR_TABLES_DEFINED +#endif + +##----------------------------------------------------------------------------- +## CPU initialisation, we set the clock to PLL 48 Mhz (12 * 4Mhz) here. +## PLL lock waiting time is implemented as a busy loop. + +#ifndef CYGPKG_HAL_FR30_CPU_INIT_DEFINED +#define CYGPKG_HAL_FR30_CPU_INIT_DEFINED +# +# busy wait loop +# pollutes r11, r12 +# +.macro wait_loop no=0x1 + ldi:20 #\no, r12 + ldi:8 #0x1, r11 +8: + sub r11, r12 + bne 8b +.endm + +##----------------------------------------------------------------------------- +## Clock Modulator control registers + + .equ FR30_MB91301_CMCR, 0x164 + .equ FR30_MB91301_CMCRH, 0x164 + .equ FR30_MB91301_CMCRL, 0x165 + .equ FR30_MB91301_CMPR, 0x166 + .equ FR30_MB91301_CMLS0, 0x168 + .equ FR30_MB91301_CMLS1, 0x16a + .equ FR30_MB91301_CMLS2, 0x16c + .equ FR30_MB91301_CMLT0, 0x170 + .equ FR30_MB91301_CMLT1, 0x172 + .equ FR30_MB91301_CMLT2, 0x174 + .equ FR30_MB91301_CMAC, 0x176 + .equ FR30_MB91301_CMACH, 0x178 + .equ FR30_MB91301_CMACL, 0x179 + .equ FR30_MB91301_CMTS, 0x17a + .equ FR30_MB91301_CMTSH, 0x17a + .equ FR30_MB91301_CMTSL, 0x17b + .equ FR30_MB91301_ICR31, 0x45f + +##----------------------------------------------------------------------------- +## Registers for Clock Generation and Reset + + .equ FR30_MB91301_RSRR, 0x480 + .equ FR30_MB91301_STCR, 0x481 + .equ FR30_MB91301_TBCR, 0x482 + .equ FR30_MB91301_CTBR, 0x483 + .equ FR30_MB91301_CLKR, 0x484 + .equ FR30_MB91301_WPR, 0x485 + .equ FR30_MB91301_DIVR0, 0x486 + .equ FR30_MB91301_DIVR1, 0x487 + +##----------------------------------------------------------------------------- +## ext bus interface registers + + .equ FR30_MB91301_ASR0, 0x640 + .equ FR30_MB91301_ACR0, 0x642 + .equ FR30_MB91301_AWR0, 0x660 + .equ FR30_MB91301_CSER, 0x680 + + .equ FR30_MB91301_PDR9, 0x9 + .equ FR30_MB91301_DDR9, 0x609 + .equ FR30_MB91301_PFR9, 0x619 + .equ FR30_MB91301_PCR9, 0x629 + + .equ FR30_MB91301_PDR8, 0x8 + .equ FR30_MB91301_DDR8, 0x608 + .equ FR30_MB91301_PFR8, 0x618 + .equ FR30_MB91301_PCR8, 0x628 + +##----------------------------------------------------------------------------- +## registers for serial0 and U-timer settings +## + .equ FR30_MB91301_PDRJ, 0x13 + .equ FR30_MB91301_DDRJ, 0x403 + .equ FR30_MB91301_PFRJ, 0x413 + .equ FR30_MB91301_UTIM0, 0x64 + .equ FR30_MB91301_UTIMR0, 0x64 + .equ FR30_MB91301_UTIMC0, 0x67 + .equ FR30_MB91301_DRCL, 0x66 + .equ FR30_MB91301_SMR0, 0x63 + .equ FR30_MB91301_SCR0, 0x62 + .equ FR30_MB91301_SIDR0, 0x61 + .equ FR30_MB91301_SODR0, 0x61 + .equ FR30_MB91301_SSR0, 0x60 + +##----------------------------------------------------------------------------- +## registers for clock settings +## + .equ FR30_MB91301_RTC_TMRLR, 0x50 + .equ FR30_MB91301_RTC_TMR, 0x52 + .equ FR30_MB91301_RTC_TMCSR, 0x56 + + + +##------------------------------------------------------------------------------ +## CPU initialisation macro +## This is mainly for setting clock speeds. +##------------------------------------------------------------------------------ +.macro hal_cpu_init + + ldi:8 #0x00, r0 + + ldi:20 #FR30_MB91301_CLKR, r10 ; PLLx4 and enable it, still use source + ldi:8 (CYGHWR_HAL_FR30_MB91301_CLKR - 1) * 16 + 4, r1 ; + stb r1, @r10 ; oscillation as clock source + + ldi:20 #FR30_MB91301_TBCR, r11 ; set time base counter to + ldi:8 #0x18, r1 ; about 60 ms and disable + stb r1, @r11 ; its interrupt (we poll below) + + ldi:20 #FR30_MB91301_CTBR, r12 ; and + ldi:8 #0xa5, r2 ; start + ldi:8 #0x5a, r3 ; the + stb r2, @r12 ; time base + stb r3, @r12 ; counter + + ldi:20 #FR30_MB91301_STCR, r13 ; set oscillation stabilisation time + ldi:8 #0x17, r1 ; to about 250 us + stb r1, @r13 ; + + ldi:20 #FR30_MB91301_DIVR0, r12 ; set CLKB divider + ldi:8 (CYGHWR_HAL_FR30_MB91301_CLKB_DIVIDER - 1) * 16 + (CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER - 1), r1 ; and + stb r1, @r12 ; CLKP divider + + ldi:20 #FR30_MB91301_DIVR1, r13 ; CLKT divider + ldi:8 (CYGHWR_HAL_FR30_MB91301_CLKT_DIVIDER - 1) * 16, r1 + stb r1, @r13 ; + + ldi:8 #0x80, r2 ; wait the rest +1: ; of the + ldub @r11, r3 ; time base counter time + and r2, r3 ; (we set it to + beq 1b ; 60 ms above) + + ldi:8 #0x36, r1 ; and now we are ready to + stb r1, @r10 ; switch clock to PLL + +.endm + +#endif /* !CYGPKG_HAL_FR30_CPU_INIT_DEFINED */ + +##----------------------------------------------------------------------------- +## FR30 interrupt handling. +## nothing is here because the intc is initialized correctly by hardware reset +## if something is needed it should be implemented in arch.inc with define'd +## adresses to the registers. It should be the same for all FR30s + + +##------------------------------------------------------------------------------ +## Diagnostics macros. +## Indicate that the diagnostic macros are defined in variant.S / hal_diag.c + +#ifndef CYGPKG_HAL_FR30_DIAG_DEFINED + +##----------------------------------------------------------------------------- +## registers for led settings +## + + .equ FR30_MB91301_PDRG, 0x10 + .equ FR30_MB91301_DDRG, 0x400 + .equ FR30_MB91301_PFRG, 0x410 +## our MB91301A does not have PCRG (pull up resistor register G) +## but it is here anyway + .equ FR30_MB91301_PCRG, 0x420 + + +.macro hal_diag_init_led + ldi:8 #0xff, r4 + ldi:20 #FR30_MB91301_DDRG, r5 + stb r4, @r5 + ldi:8 #0x00, r13 + ldi:20 #FR30_MB91301_PFRG, r5 + stb r13, @r5 + dmovb r13, @FR30_MB91301_PDRG +.endm + +## +## switch on led on "hardcoded" value supplied after this macro +## pollutes r13 +## +.macro hal_diag_led led=0x0 +##st r13, @-r15 + ldi:8 #\led , r13 + dmovb r13, @FR30_MB91301_PDRG +##ld @r15+, r13 +.endm + +##------------------------------------------------------------------------------ +## UARTa macros +## + +## output a value to UART a +## the value has to be in r4 +## register r1 will be polluted +.macro uarta_putc + ldi:8 #FR30_MB91301_SODR0, r1 + stb r4, @r1 +.endm + + +## wait for the data in UART a SODR0 register to be drained +## registers r1, r2, r3 will be polluted +.macro uarta_drain + ldi:8 #FR30_MB91301_SSR0, r3 ; + ldi:8 #0x08, r1 ; TDRE bit of SSR0 +1: ; + ldub @r3, r2 ; + and r1, r2 ; + beq 1b +.endm + +## receive a value from UART a +## value is returned in r4 +## register r1, r2 and r3 will be polluted +.macro uarta_getc + ldi:8 #FR30_MB91301_SSR0, r3 ; + ldi:8 #0x10, r1 ; RDRF bit of SSR0 +2: + ldub @r3, r2 ; + and r1, r2 ; + beq 2b ; wait until a byte is received + + ldi:8 #FR30_MB91301_SIDR0, r3 ; + ldub @r3, r4 ; and get the value +.endm + +#define CYGPKG_HAL_FR30_DIAG_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_FR30_TIMER_DEFINED + + .macro hal_timer_init + + # load reload value into reload register + ldi:8 #FR30_MB91301_RTC_TMRLR, r4 + ldi:20 #CYGNUM_HAL_RTC_PERIOD, r5 + sth r5, @r4 + # set parameters to TODO + ldi:8 #FR30_MB91301_RTC_TMCSR, r4 + ldi:20 #0x0813, r5 + sth r5, @r4 + .endm + +#define CYGPKG_HAL_FR30_TIMER_DEFINED + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/src/fr30_mb91301.ld @@ -0,0 +1,164 @@ +//============================================================================= +// +// MLT linker script for Fujitsu FR30 +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/system.h> + +STARTUP(vectors.o) +ENTRY(_start) +#ifdef EXTRAS +INPUT(extras.o) +#endif +#if (__GNUC__ >= 3) +// GROUP(libtarget.a libgcc.a libsupc++.a) +GROUP(libtarget.a libgcc.a) +#else +GROUP(libtarget.a libgcc.a) +#endif + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN \ + /* Debug information */ \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } + +#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \ + .fixed_vectors _vma_ : _lma_ \ + { FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \ + > _region_ + +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { FORCE_OUTPUT; KEEP (*(.rom_vectors)) } \ + > _region_ + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + PROVIDE (__stext = ABSOLUTE(.)); \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) \ + *(.glue_7) *(.glue_7t) \ + } > _region_ \ + _etext = .; PROVIDE (__etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) } \ + > _region_ + +/* #define SECTION_startup_trampoline(_region_, _vma_, _lma_) + .startup_trampoline _vma_ : _lma_ + { FORCE_OUTPUT; *(.startup_trampoline*) } + > _region_ */ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fixup) } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.gcc_except_table) } \ + > _region_ + +#define SECTION_mmu_tables(_region_, _vma_, _lma_) \ + .mmu_tables _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.mmu_tables) } \ + > _region_ + +#define SECTION_sram(_region_, _vma_, _lma_) \ + .sram _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.sram*) } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); *(.data*) *(.data1) \ + . = ALIGN (8); \ + KEEP(*( SORT (.ecos.table.*))) ; \ + . = ALIGN (8); \ + __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \ + __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \ + *(.sdata*) \ + *(.eh_frame) \ + . = ALIGN (8); *(.2ram.*) \ + /* Global pointer stuff */ \ + . = ALIGN(8); _gp = . + 2048; __global = _gp; \ + _GOT_START_ = ABSOLUTE (.); *(.got) _GOT_END_ = ABSOLUTE (.); \ + _GOT_PLT_START_ = ABSOLUTE (.); *(.got_plt) _GOT_PLT_END_ = ABSOLUTE (.); \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + _DYNAMIC_ = ABSOLUTE (.); *(.dynamic) _DYNAMIC_ = ABSOLUTE (.); \ + } \ + > _region_ \ + __rom_data_start = LOADADDR (.data); \ + __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \ + __rom_data_end = LOADADDR (.data) + SIZEOF(.data); + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + *(.scommon) *(.dynbss) *(.sbss) *(.sbss.*) *(.bss*) *(.bss.*) *(COMMON) \ + __bss_end = ABSOLUTE (.); } \ + > _region_ + +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); + +#include <pkgconf/hal_fr30.h> +#include CYGHWR_MEMORY_LAYOUT_LDI
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/src/hal_diag.c @@ -0,0 +1,564 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors:larsi +// Date: 2006-07-26 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/hal_misc.h> +/*---------------------------------------------------------------------------*/ + +//#define CYG_KERNEL_DIAG_LCD +#define CYG_KERNEL_DIAG_SERIAL0 // For ROM start but see immediately below: + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) +#undef CYG_KERNEL_DIAG_SERIAL0 +#undef CYG_KERNEL_DIAG_LCD +#define CYG_KERNEL_DIAG_CYGMON +#define CYG_KERNEL_DIAG_GDB + +#endif + +/*---------------------------------------------------------------------------*/ + +#if defined(CYG_KERNEL_DIAG_SERIAL0) || defined(CYG_KERNEL_DIAG_CYGMON) + +/*---------------------------------------------------------------------------*/ +// LED diag function +/* +void hal_diag_init_led(){ +// we only init the first 4 leds here + asm volatile( + "ldi:8 #0xf, r4;\n" + "ldi:20 #CYG_HAL_FR30_MB91360_DDRJ, r5;\n" + "stb r4, @r5;\n" + "ldi:20 #CYG_HAL_FR30_MB91360_PFRJ, r5;\n" + "stb r4, @r5;\n" + : : :"r4", "r5" + ); +} +*/ +// static cyg_uint8 leds = 0; + +void hal_diag_init(void){ + + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, 0x2); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, 0x3); + + // set up U-Timer + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_UTIMC0, 0x02); + // 115200 bps + HAL_WRITE_UINT16(CYG_HAL_FR30_MB91301_UTIMR0, 0x7); + + // setup UART + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_SCR0, 0x13); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_SMR0, 0x30); +} + + +void hal_diag_led(cyg_uint8 leds) +{ + + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PDRG, leds); + +} + +/*---------------------------------------------------------------------------*/ + +void hal_diag_write_char_serial0( char c) +{ + cyg_uint8 ssr; + + do + { + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_SSR0 , ssr ); + } while (!(ssr & BIT3)); + + HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_SODR0, c ); + +} + +void hal_diag_write_hex_serial0(unsigned int c) +{ + unsigned char chr; + int i; + + hal_diag_write_char_serial0('0'); + hal_diag_write_char_serial0('x'); + + for(i = 28; i >= 0; i = i - 4) + { + chr = (c >> i) & 0xf; + if (chr >= 10) chr = chr + 55; /* for A-F */ + else chr = chr + 48; /* for 0-9 */ + hal_diag_write_char_serial0(chr); + } + hal_diag_write_char_serial0('\n'); + hal_diag_write_char_serial0('\r'); +} + + +void hal_diag_drain(void) +{ + cyg_uint8 ssr; + + do + { + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_SSR0 , ssr ); + } while (!(ssr & BIT3)); +} + +void hal_diag_read_char_serial0(char *c) +{ + cyg_uint8 ssr; + + do + { + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_SSR0 , ssr ); + } while (!(ssr & BIT4)); + + HAL_READ_UINT8( CYG_HAL_FR30_MB91301_SIDR0, *c ); + +} + + +#if defined(CYG_KERNEL_DIAG_CYGMON) +void hal_diag_dumb_write_char(char c) +#else +void hal_diag_write_char(char c) +#endif +{ +#ifdef CYG_KERNEL_DIAG_GDB + static char line[100]; + static int pos = 0; +// register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + CYG_INTERRUPT_STATE oldstate; + HAL_DISABLE_INTERRUPTS(oldstate); + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + hal_diag_write_char_serial0('$'); + hal_diag_write_char_serial0('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial0(h); + hal_diag_write_char_serial0(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial0('#'); + hal_diag_write_char_serial0(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial0(hex[csum&0xF]); + + hal_diag_read_char_serial0( &c1 ); + + if( c1 == '+' ) break; + + { + extern void cyg_hal_user_break(CYG_ADDRWORD *regs); + extern cyg_bool cyg_hal_is_break(char *buf, int size); + if( cyg_hal_is_break( &c1 , 1 ) ) + cyg_hal_user_break( NULL ); + } + + break; + } + + pos = 0; + + // Wait for all data from serial line to drain + // and clear ready-to-send indication. + hal_diag_drain_serial0(); + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS( oldstate ); + + } +#else + hal_diag_write_char_serial0(c); +#endif +} + + +void hal_diag_read_char(char *c) +{ + for(;;) + { +#if defined(CYG_KERNEL_DIAG_GDB) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + typedef void rom_read_fn(char *c); + rom_read_fn *fn = ((rom_read_fn **)0x80000100)[62]; + + fn(c); + +#else + hal_diag_read_char_serial0(c); + +#endif + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + if( *c == 3 ) + { + // Ctrl-C: breakpoint. + extern void breakpoint(void); + breakpoint(); + continue; + } +#elif defined(CYGSEM_HAL_USE_ROM_MONITOR) + if( *c == 3 ) + { + // Ctrl-C: breakpoint. + +// HAL_BREAKPOINT(_breakinst); + typedef void bpt_fn(void); + bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; + + bfn(); + continue; + } +#endif + + break; + } +} + +#endif // defined(CYG_KERNEL_DIAG_SERIAL0) || defined(CYG_KERNEL_DIAG_CYGMON) + + +#if defined(CYG_KERNEL_DIAG_CYGMON) // only + +/* This code has been imported from the BSP module. The definitions have + * been left as-is, even though there was scope for doing more, to avoid + * too much drift from the original sources + */ + +struct bsp_comm_procs { + void *ch_data; + void (*__write)(void *ch_data, const char *buf, int len); + int (*__read)(void *ch_data, char *buf, int len); + void (*__putc)(void *ch_data, char ch); + int (*__getc)(void *ch_data); + int (*__control)(void *ch_data, int func, ...); +}; + +// This is pointed to by entry BSP_NOTVEC_BSP_COMM_PROCS: +typedef struct { + int version; /* version number for future expansion */ + void *__ictrl_table; + void *__exc_table; + void *__dbg_vector; + void *__kill_vector; + struct bsp_comm_procs *__console_procs; + struct bsp_comm_procs *__debug_procs; + void *__flush_dcache; + void *__flush_icache; + void *__cpu_data; + void *__board_data; + void *__sysinfo; + int (*__set_debug_comm)(int __comm_id); + int (*__set_console_comm)(int __comm_id); + int (*__set_serial_baud)(int __comm_id, int baud); + void *__dbg_data; + void (*__reset)(void); + int __console_interrupt_flag; +} bsp_shared_t; + +/* + * Core Exception vectors. + */ +#define BSP_EXC_INT 0 +#define BSP_EXC_TLBMOD 1 +#define BSP_EXC_TLBL 2 +#define BSP_EXC_TLBS 3 +#define BSP_EXC_ADEL 4 +#define BSP_EXC_ADES 5 +#define BSP_EXC_IBE 6 +#define BSP_EXC_DBE 7 +#define BSP_EXC_SYSCALL 8 +#define BSP_EXC_BREAK 9 +#define BSP_EXC_ILL 10 +#define BSP_EXC_CPU 11 +#define BSP_EXC_OV 12 +#define BSP_EXC_TRAP 13 +#define BSP_EXC_VCEI 14 +#define BSP_EXC_FPE 15 +#define BSP_EXC_RSV16 16 +#define BSP_EXC_RSV17 17 +#define BSP_EXC_RSV18 18 +#define BSP_EXC_RSV19 19 +#define BSP_EXC_RSV20 20 +#define BSP_EXC_RSV21 21 +#define BSP_EXC_RSV22 22 +#define BSP_EXC_WATCH 23 +#define BSP_EXC_RSV24 24 +#define BSP_EXC_RSV25 25 +#define BSP_EXC_RSV26 26 +#define BSP_EXC_RSV27 27 +#define BSP_EXC_RSV28 28 +#define BSP_EXC_RSV29 29 +#define BSP_EXC_RSV30 30 +#define BSP_EXC_VCED 31 +/* tx39 debug exception */ +#define BSP_EXC_DEBUG 32 +#define BSP_EXC_TLB 33 +#define BSP_EXC_NMI 34 +/* + * Hack for eCos on tx39 to set an async breakpoint. + */ +#define BSP_VEC_BP_HOOK 35 + +#define BSP_EXC_XTLB 36 +#define BSP_EXC_CACHE 37 + +#define BSP_MAX_EXCEPTIONS 38 + +/* + * Another hack for tx39 eCos compatibility. + */ +#if defined(__CPU_R3900__) +#define BSP_VEC_MT_DEBUG 15 +#else +#define BSP_VEC_MT_DEBUG 38 +#endif + +#define BSP_VEC_STUB_ENTRY 39 +#define BSP_VEC_BSPDATA 40 +#define BSP_VEC_MAGIC 41 +#define BSP_VEC_IRQ_CHECK 42 + +#define BSP_VEC_PAD 43 +#define NUM_VTAB_ENTRIES 44 + + +#define BSP_MAGIC_VAL 0x55aa4321 + +#define SYS_interrupt 1000 + +// These vectors should be called with: +// +// k0 - Exception Number + +#define CYGMON_VECTOR_TABLE_BASE 0x80000100 +#define CYGMON_VECTOR_TABLE ((CYG_ADDRESS *)CYGMON_VECTOR_TABLE_BASE) + +#if 0 // UNUSED +static int +hal_bsp_set_debug_comm(int arg) +{ + bsp_shared_t *shared; + + shared = (bsp_shared_t *) + (CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]); + + if (0 != shared->__set_debug_comm) { + return (*(shared->__set_debug_comm))(arg); + } + return 0; +} + +static int +hal_bsp_set_console_comm(int arg) +{ + bsp_shared_t *shared; + + shared = (bsp_shared_t *) + (CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]); + + if (0 != shared->__set_console_comm) { + return (*(shared->__set_console_comm))(arg); + } + return 0; +} +#endif // 0 UNUSED + +static void bsp_trap(int trap_num); + +static int +hal_bsp_console_write(const void *p, int len) +{ + bsp_shared_t *shared; + struct bsp_comm_procs *com; + int magic; + + /*hal_bsp_set_console_comm(0);*/ + + /* If this is not a BSP-based CygMon, return 0 */ + magic = (int)(CYGMON_VECTOR_TABLE[ BSP_VEC_MAGIC ]); + if (magic != BSP_MAGIC_VAL) + return 0; + + shared = (bsp_shared_t *) + (CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]); + + com = shared->__console_procs; + + if (0 != com) { + shared->__console_interrupt_flag = 0; + com->__write(com->ch_data, p, len); + if (shared->__console_interrupt_flag) { + /* debug interrupt; stop here */ + bsp_trap(SYS_interrupt); + } + + return 1; + } + return 0; +} + +static void +bsp_trap(int trap_num) +{ + asm("syscall\n"); +} + + +static void +hal_dumb_serial_write(const char *p, int len) +{ + int i; + for ( i = 0 ; i < len; i++ ) { + hal_diag_dumb_write_char(p[i]); + } +} +/* +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + + HAL_DISABLE_INTERRUPTS(old); + + if ( ! hal_bsp_console_write( line, pos ) ) + // then there is no function registered, just spew it out serial + hal_dumb_serial_write( line, pos ); + + pos = 0; + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS(old); + + } +}*/ + +int +hal_diag_irq_check(int vector) +{ + typedef int irq_check_fn(int irq_nr); + irq_check_fn *fn = (irq_check_fn *)(CYGMON_VECTOR_TABLE[ BSP_VEC_IRQ_CHECK ]); + int magic; + + + /* If this is not a BSP-based CygMon, return 0 */ + magic = (int)(CYGMON_VECTOR_TABLE[ BSP_VEC_MAGIC ]); + if (magic != BSP_MAGIC_VAL) + return 0; + +#if defined(CYGPKG_HAL_MIPS_TX3904) + /* convert vector to BSP irq number */ + if (vector == 16) + vector = 2; + else + vector += 3; +#endif + + return fn(vector); +} + +#endif // defined(CYG_KERNEL_DIAG_CYGMON) *only* + + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/src/var_misc.c @@ -0,0 +1,125 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_misc.h> +/*------------------------------------------------------------------------*/ +// Array which stores the configured priority levels for the configured +// interrupts. + +/* this may be useful later when interrupt masking of internal interrupt + sources is implemented + +volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; +*/ +/*------------------------------------------------------------------------*/ + +void hal_variant_init(void) +{ +} + +//-------------------------------------------------------------------------- +// Microsecond delay +// This uses reload timer 2, because timer 0 and 1 can cause DMA transfers +// and may be used by the application. +// Timer is initialized with 32 prescaler. If we need more precise delay +// this has to change. + +void hal_delay_us(cyg_int32 n){ +#define TIMER_TIME CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER / 32 + + unsigned int calc(unsigned long long n){ + return n * TIMER_TIME / 1000000; + } + + cyg_uint16 timer_status; + + n = 21;//calc(n); + // stop eventually running counter and initialize + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x812); + + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMRLR, 0xFFFF); + while(n > 0xffff){ + // start counting + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x813); + n = n - 0xffff; + // look for underflow + do { + HAL_READ_UINT16(CYG_HAL_FR30_DLY_TMCSR, timer_status); + } while (!(timer_status & BIT2)); + // clear underflow bit + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x813); + } + // clear count enable bit + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x810); + // set new remaining count value + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMRLR, n); + // start counting + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x813); + // look for underflow + do { + HAL_READ_UINT16(CYG_HAL_FR30_DLY_TMCSR, timer_status); + } while (!(timer_status & BIT2)); + // clear underflow and count enable bits + HAL_WRITE_UINT16(CYG_HAL_FR30_DLY_TMCSR, 0x810); +} + +/*------------------------------------------------------------------------*/ +/* End of var_misc.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/mb91301/current/src/variant.S @@ -0,0 +1,196 @@ +##============================================================================= +## +## variant.S +## +## FR30 MB91301 variant code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors:larsi +## Date: 2006-07-22 +## Purpose: FR30 MB91301 variant code +## Description: Variant specific code for MB91301 processor family. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +#============================================================================== +# Vector table for storage in flash +# base address is 0x000FFC00, which stores the vector address for number 255 +# address 0x000FFFFC is the last vector, the reset vector, which is not +# alterable. Vectors 255 to 80 are used by the INT instruction and set to 0 +# here for now ... + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + + .section ".rom_vectors","ax" + +# .data + + .balign 4 + .global hal_fr30_vector_table +hal_fr30_vector_table: + .rept 255-80 + 1 + .long 0x0 + .endr + .rept 79-67 + 1 + .long 0x0 + .endr + + .long 0x0 + .long 0x0 + .long 0x0 +# number 63 first interrupt source + .long hal_fr30_irq_63 + .long hal_fr30_irq_62 + .long hal_fr30_irq_61 + .long hal_fr30_irq_60 + .long hal_fr30_irq_59 + .long hal_fr30_irq_58 + .long hal_fr30_irq_57 + .long hal_fr30_irq_56 + .long hal_fr30_irq_55 + .long hal_fr30_irq_54 + .long hal_fr30_irq_53 + .long hal_fr30_irq_52 + .long hal_fr30_irq_51 + .long hal_fr30_irq_50 + .long hal_fr30_irq_49 + .long hal_fr30_irq_48 + .long hal_fr30_irq_47 + .long hal_fr30_irq_46 + .long hal_fr30_irq_45 + .long hal_fr30_irq_44 + .long hal_fr30_irq_43 + .long hal_fr30_irq_42 + .long hal_fr30_irq_41 + .long hal_fr30_irq_40 + .long hal_fr30_irq_39 + .long hal_fr30_irq_38 + .long hal_fr30_irq_37 + .long hal_fr30_irq_36 + .long hal_fr30_irq_35 + .long hal_fr30_irq_34 + .long hal_fr30_irq_33 + .long hal_fr30_irq_32 + .long hal_fr30_irq_31 + .long hal_fr30_irq_30 + .long hal_fr30_irq_29 + .long hal_fr30_irq_28 + .long hal_fr30_irq_27 + .long hal_fr30_irq_26 + .long hal_fr30_irq_25 + .long hal_fr30_irq_24 + .long hal_fr30_irq_23 + .long hal_fr30_irq_22 + .long hal_fr30_irq_21 + .long hal_fr30_irq_20 + .long hal_fr30_irq_19 + .long hal_fr30_irq_18 + .long hal_fr30_irq_17 + .long hal_fr30_irq_16 + .long hal_fr30_irq_15 + .long hal_fr30_exception_noerr_14 + .long hal_fr30_exception_noerr_13 + .long hal_fr30_exception_noerr_12 + .long hal_fr30_exception_noerr_11 + .long hal_fr30_exception_noerr_10 + .long hal_fr30_exception_noerr_9 + .long hal_fr30_exception_noerr_8 + .long hal_fr30_exception_noerr_7 + .long hal_fr30_exception_noerr_6 + .long hal_fr30_exception_noerr_5 + .long hal_fr30_exception_noerr_4 + .long hal_fr30_exception_noerr_3 + .long hal_fr30_exception_noerr_2 + +# mode vector (only the first of the four byte is relevant) + .byte 0x1 + .byte 0 + .byte 0 + .byte 0 + +# reset vector + .long _start + +#endif + +##----------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + + .extern hal_default_isr + + .data + .balign 4 + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .rept CYGNUM_HAL_ISR_COUNT + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S +
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/ChangeLog @@ -0,0 +1,55 @@ +2007-07-09 Lars Poeschel <larsi@wh2.tu-dresden.de> + + * src/platform.S: + * src/plf_misc.c: + * src/plf_stub.c: + * src/ser.c: + * misc/redboot_RAM.ecm: + * misc/redboot_ROM.ecm: + * include/pkgconf/mlt_fr30_skmb91302_ram.h: + * include/pkgconf/mlt_fr30_skmb91302_ram.ldi: + * include/pkgconf/mlt_fr30_skmb91302_rom.h: + * include/pkgconf/mlt_fr30_skmb91302_rom.ldi: + * include/platform.inc: + * include/plf_cache.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/plf_stub.h: + * cdl/hal_fr30_skmb91302.cdl: Initial fr30 ecos port + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/cdl/hal_fr30_skmb91302.cdl @@ -0,0 +1,282 @@ +# ==================================================================== +# +# hal_fr30_skmb91302.cdl +# +# Fujitsu Starterkit MB91302 board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_FR30_MB91301_SKMB91302 { + display "Fujitsu Starterkit MB91302 board" + parent CYGPKG_HAL_FR30 + requires CYGPKG_HAL_FR30_MB91301 + define_header hal_fr30_skmb91302.h + include_dir cyg/hal + + description "Fujitsu Starterkit MB91302 board platform HAL + package should be used when targeting the actual hardware for + the Fujitsu Starterkit MB91302 board platform." + + compile platform.S plf_misc.c ser.c + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_fr30_mb91301.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_fr30.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_fr30_mb91301.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_fr30_skmb91302.h>" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMRAM"} + default_value {"ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + + description "Should the system run from RAM, ROM, or copy itself from ROM + and RAM and then run in RAM?" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + description "The MB91302 board has 3 serial ports. Only the first + 2 have mounted 9 pin connectors. The 3rd is not + connected and should therefore not be used." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description "This option chooses which port will be used to connect + to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 57600 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 57600 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + + description "Global build options including control over compiler + flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "fr30-unknown-elf" } + description "This option specifies the command prefix used + when invoking the build tools." + + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -finit-priority -fomit-frame-pointer" } + description "This option controls the global compiler flags + which are used to compile all packages by default. + Individual packages may define options which + override these global flags." + + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { " -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description "This option controls the global linker flags. + Individual packages may define options which + override these global flags." + + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description "This option enables the building of the GDB + stubs for the board. The common HAL controls + takes care of most of the build process, but the + final conversion from ELF image to binary data is + handled by the platform CDL, allowing relocation + of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "mlt_fr30_skmb91302_ram" : \ + "mlt_fr30_skmb91302_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_fr30_skmb91302_ram.ldi>" : \ + "<pkgconf/mlt_fr30_skmb91302_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_fr30_skmb91302_ram.h>" : \ + "<pkgconf/mlt_fr30_skmb91302_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor bool + default_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Allow coexistence with ROM monitor (CygMon or GDB stubs) by + only initializing interrupt vectors on startup, thus leaving + exception handling to the ROM monitor." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + + description "Enable this option if this program is to be used as + a ROM monitor, i.e. applications will be loaded into + RAM on the board, and this ROM monitor may process + exceptions or interrupts generated from the + application. This enables features such as utilizing + a separate interrupt stack when exceptions are + generated." + + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-all $< $(@:.srec=.img) + $(OBJCOPY) -O srec $< $@ + } + } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/pkgconf/mlt_fr30_skmb91302_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x2000000) +#define CYGMEM_REGION_ram_SIZE (0x7fffff) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x03F00000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/pkgconf/mlt_fr30_skmb91302_ram.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x3F000, LENGTH = 0x1000 + sdram : ORIGIN = 0x2000000, LENGTH = 0x800000 +} + +SECTIONS +{ + SECTIONS_BEGIN +// SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (sdram, 0x2000000, LMA_EQ_VMA) + SECTION_text (sdram, 0x2008000, LMA_EQ_VMA) + SECTION_fini (sdram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (sdram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (sdram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (sdram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (sdram, ALIGN(0x4), FOLLOWING (.gcc_except_table)) +// SECTION_data (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_bss (sdram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x1000); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/pkgconf/mlt_fr30_skmb91302_rom.h @@ -0,0 +1,17 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x2000000) +#define CYGMEM_REGION_ram_SIZE (0x7fffff) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x03F00000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/pkgconf/mlt_fr30_skmb91302_rom.ldi @@ -0,0 +1,32 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x3F000, LENGTH = 0x1000 + rom1 : ORIGIN = 0x80000, LENGTH = 0x7fc00 // Length = 511 kB + ints : ORIGIN = 0xFFC00, LENGTH = 0x400 + rom2 : ORIGIN = 0x100000, LENGTH = 0x700000 + sdram : ORIGIN = 0x2000000, LENGTH = 0x800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_text (rom1, 0x80000, LMA_EQ_VMA) + SECTION_fini (rom1, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom1, ALIGN (0x4), LMA_EQ_VMA) +// SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom1, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom1, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rom_vectors (ints,0xffc00 , LMA_EQ_VMA) + SECTION_fixed_vectors (sdram, 0x2000000, LMA_EQ_VMA) + SECTION_data (sdram, ALIGN(0x4), FOLLOWING (.gcc_except_table)) +// SECTION_data (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_bss (sdram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x1000); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/platform.inc @@ -0,0 +1,189 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## Fujitsu Starterkit MB91302 board assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2007 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors: +## Date: 2007-07-09 +## Purpose: Fujitsu Starterkit MB91302 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the skmb91302 board. +## Usage: +## #include <cyg/hal/platform.inc> +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/fr30.inc> + +#------------------------------------------------------------------------------ + +#define CYGPKG_HAL_RESET_VECTOR_FIRST_CODE + .macro hal_reset_vector_first_code + .endm + + +##----------------------------------------------------------------------------- +## ext bus interface registers +## flash part + .equ FR30_MB91301_ASR0, 0x640 + .equ FR30_MB91301_ACR0, 0x642 + .equ FR30_MB91301_AWR0, 0x660 + .equ FR30_MB91301_CSER, 0x680 + + .equ FR30_MB91301_PDR9, 0x9 + .equ FR30_MB91301_DDR9, 0x609 + .equ FR30_MB91301_PFR9, 0x619 + .equ FR30_MB91301_PCR9, 0x629 + + .equ FR30_MB91301_PDR8, 0x8 + .equ FR30_MB91301_DDR8, 0x608 + .equ FR30_MB91301_PFR8, 0x618 + .equ FR30_MB91301_PCR8, 0x628 + +## sdram part + .equ FR30_MB91301_ASR6, 0x658 + .equ FR30_MB91301_ACR6, 0x65a + .equ FR30_MB91301_AWR6, 0x66c + .equ FR30_MB91301_MCRA, 0x670 + .equ FR30_MB91301_MCRB, 0x671 + .equ FR30_MB91301_RCR, 0x684 + +##------------------------------------------------------------------------------ +## ext Bus (memory controller) initialisation macros +## +## flash part + + +#define CYGPKG_HAL_FR30_FLASH_INIT_DEFINED +.macro hal_flash_init + + ldi:20 #FR30_MB91301_ASR0, r10 ; CS0 area starts at + ldi:8 0x000, r0 ; 0x00000000 + sth r0, @r10 ; + + ldi:20 #FR30_MB91301_ACR0, r11 ; configuration parameters for CS0 + ldi:20 #0x7422, r1 ; 8MB(0x0-0x7FFFFF),16bit data bus, + sth r1, @r11 ; pre-fetch off, single access, + ; write enable, big endian, + ; normal access(asynchronous), + ; WR pin enabled for write, + ; wait by RDY pin disabled + + ldi:20 #FR30_MB91301_AWR0, r12 ; first access auto-wait 3cyc + ldi:20 #0x3378, r2 ; inpage access auto-wait 3cyc + sth r2, @r12 ; read/write idle 1cyc + ; write recover 3cyc + ; async write strobe outp enabled + ; CS delay enabled + ; CS read/write setup delay 0 + ; RD/WR -> CS hold extension 0 cyc + + ldi:20 #FR30_MB91301_PFR9, r13 ; WRn, BAAE, ASXE enable + ldi:8 #0x7e, r3 ; + stb r3, @r13 ; + +## following would chip select enable +## we only use cs0 until here, which is already set by reset + +.endm + + +## sdram part + + +#define CYGPKG_HAL_FR30_MEMC_INIT_DEFINED + +.macro hal_memc_init + + ldi:20 #FR30_MB91301_ASR6, r10 ; CS6 area starts at + ldi:20 0x200, r0 ; 0x02000000 + sth r0, @r10 ; + + ldi:20 #FR30_MB91301_ACR6, r11 ; configuration parameters for CS6 + ldi:20 #0x7868, r1 ; 64MB(0x2000000-0x27FFFFF),32bit data bus, + sth r1, @r11 ; pre-fetch on, single access(no burst), + ; write enable, big endian, + ; FCRAM setting + + ldi:20 #FR30_MB91301_AWR6, r12 ; first access auto-wait 1cyc ?? + ldi:20 #0x1159, r2 ; inpage access auto-wait 1cyc ?? + sth r2, @r12 ; read/write idle 1cyc ?? + ; write recover 1cyc ?? + ; async write strobe outp enabled ?? + ; CS delay disabled ?? + ; CS read/write setup delay 0 ?? + ; RD/WR -> CS hold extension 1 cyc ?? + ; see Hardware Manual page 156ff + + ldi:20 #FR30_MB91301_MCRA, r13 ; 8 columns, single write, + ldi:8 #0x07, r3 ; 4 banks for burst write, + stb r3, @r13 ; 4 active banks + + ldi:20 #FR30_MB91301_PFR9, r10 ; enable WRn, BAAE, ASXE, + ldi:8 #0x7e, r0 ; sysclk, MCKE, MCKEE + stb r0, @r10 + + ldi:20 #FR30_MB91301_PFR8, r11 ; enable WR3XE, WR2XE, WR1XE + ldi:8 #0xe0, r1 + stb r1, @r11 + + ldi:20 #FR30_MB91301_CSER, r12 ; switch on CS6 & CS0 + ldi:8 #0x41, r2 + stb r2, @r12 + + ldi:20 #FR30_MB91301_RCR, r13 ; power on SDRAM I/F + ldi:20 #0xe247, r3 ; 0xe247 -> 0xe24f + sth r3, @r13 + ldi:20 #0xe24f, r3 + sth r3, @r13 + +.endm + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/plf_cache.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: +// Date: 2007-07-09 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/plf_intr.h @@ -0,0 +1,73 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Fujitsu Starterkit MB91302 board interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: +// Date: 2007-07-09 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the Fujitsu Starterkit MB91302 board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +// Interrupt controller stuff. + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/plf_io.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt, jskov, nickg +// Contributors: +// Date: 2007-07-09 +// Purpose: Fujitsu Starterkit MB91302 board IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +// Note: Based on information in +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_intr.h> // Interrupt vectors + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/include/plf_stub.h @@ -0,0 +1,77 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2007 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: +// Date: 2007-07-09 +// Purpose: Platform HAL stub support for Fujitsu Starterkit MB91302 boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/fr30_stub.h> // architecture stub support + + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +// Syscall support. +#ifdef CYGPKG_CYGMON +// Cygmon provides syscall handling for this board +#define SIGSYSCALL SIGSYS +extern int __get_syscall_num (void); +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/misc/redboot_RAM.ecm @@ -0,0 +1,67 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware phytec91f364g ; + template redboot ; + package -hardware CYGPKG_HAL_FR30 current ; + package -hardware CYGPKG_HAL_FR30_MB91301_SKMB91302 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +#cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { +# user_value 1 +#}; + +cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + inferred_value 0x1C00000 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/misc/redboot_ROM.ecm @@ -0,0 +1,68 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware phytec91f364g ; + template redboot ; + package -hardware CYGPKG_HAL_FR30 current ; + package -hardware CYGPKG_HAL_FR30_MB91301_SKMB91302 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + + +cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + inferred_value 0x1C00000 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/src/platform.S @@ -0,0 +1,73 @@ +## +#============================================================================= +## platform.S +## +## Fujitsu Starterkit MB91302 platform code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): larsi +## Contributors: +## Date: 2007-07-09 +## Purpose: Fujitsu Starterkit MB91302 platform code +## Description: Platform specific code for Fujitsu Starterkit MB91302 board. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- + +##----------------------------------------------------------------------------- +# Platform Initialization. +# This code performs platform specific initialization. + + +##----------------------------------------------------------------------------- +## end of platform.S
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/src/plf_misc.c @@ -0,0 +1,109 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, larsi +// Contributors: nickg, jlarmour, dmoseley +// Date: 2007-07-09 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +#include <cyg/hal/hal_if.h> + + +/*------------------------------------------------------------------------*/ + +void hal_platform_init(void) +{ +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) + // Set up eCos/ROM interfaces + hal_if_init(); +#endif + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + (defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) || \ + defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)) + +{ + extern CYG_ADDRESS hal_virtual_vector_table[32]; + void patch_dbg_syscalls( void * ); + patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); +} +#endif + +} + +/*------------------------------------------------------------------------*/ +/* Reset support */ + + +/*------------------------------------------------------------------------*/ +/* Syscall support */ +#ifdef CYGPKG_CYGMON +// Cygmon provides syscall handling for this board +#include <cyg/hal/hal_stub.h> +int __get_syscall_num (void) +{ + return SIGSYS; +} +#endif + + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/src/plf_stub.c @@ -0,0 +1,96 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter, larsi +// Contributors: +// Date: 2007-07-09 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_io.h> // HAL IO macros +#include <cyg/hal/hal_diag.h> // diag output. FIXME + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- +// Stub init + +void hal_plf_stub_init(void) +{ +// extern CYG_ADDRESS hal_virtual_vector_table[64]; + extern void init_thread_syscall( void *); + extern void install_async_breakpoint(void *epc); + void (*oldvsr)(void); + extern void __default_exception_vsr(void); + + // Ensure that the breakpoint VSR points to the default VSR. This will pass + // it on to the stubs. + HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, __default_exception_vsr, &oldvsr ); + + // Install async breakpoint handler into vector table. + hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint; + +#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT) + // Only include this code if we do not have a kernel. Otherwise + // the kernel supplies the functionality for the app we are linked + // with. + + // Prepare for application installation of thread info function in + // vector table. + hal_virtual_vector_table[15] = 0; + init_thread_syscall( (void *)&hal_virtual_vector_table[15] ); +#endif +} + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +// End of plf_stub.c
new file mode 100644 --- /dev/null +++ b/packages/hal/fr30/skmb91302/current/src/ser.c @@ -0,0 +1,427 @@ +//============================================================================= +// +// ser.c +// +// Simple (polling) driver for the Fujitsu MB91302 on-chip serial port +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): larsi +// Contributors: +// Date: 2007-01-10 +// Description: Simple driver for the MB91302 internal serial port +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +// We have no control over baud rate +// #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 +// #define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_57600 +// #endif + +// #ifndef CYG_DEV_SERIAL_BAUD_DIVISOR +// #error Missing/incorrect serial baud rate defined - CDL error? +// #endif + +#define CYG_HAL_FR30_MB91301_SMR0 0x63 +#define CYG_HAL_FR30_MB91301_SCR0 0x62 +#define CYG_HAL_FR30_MB91301_SIDR0 0x61 +#define CYG_HAL_FR30_MB91301_SODR0 0x61 +#define CYG_HAL_FR30_MB91301_SSR0 0x60 +#define CYG_HAL_FR30_MB91301_UTIM0 0x64 +#define CYG_HAL_FR30_MB91301_UTIMR0 0x64 +#define CYG_HAL_FR30_MB91301_DRCL 0x66 +#define CYG_HAL_FR30_MB91301_UTIMC0 0x67 + + +#define CYG_HAL_FR30_MB91301_SER0_BASE 0x60 +#define CYG_HAL_FR30_MB91301_SER1_BASE 0x68 +#define CYG_HAL_FR30_MB91301_SER2_BASE 0x70 + +#define CYG_HAL_FR30_MB91301_SMR_OFFSET 0x03 +#define CYG_HAL_FR30_MB91301_SCR_OFFSET 0x02 +#define CYG_HAL_FR30_MB91301_SIDR_OFFSET 0x01 +#define CYG_HAL_FR30_MB91301_SODR_OFFSET 0x01 +#define CYG_HAL_FR30_MB91301_SSR_OFFSET 0x00 +#define CYG_HAL_FR30_MB91301_UTIM_OFFSET 0x04 +#define CYG_HAL_FR30_MB91301_UTIMR_OFFSET 0x04 +#define CYG_HAL_FR30_MB91301_DRCL_OFFSET 0x06 +#define CYG_HAL_FR30_MB91301_UTIMC_OFFSET 0x07 + +#define CYG_HAL_FR30_MB91301_PDRG 0x10 +#define CYG_HAL_FR30_MB91301_DDRG 0x400 +#define CYG_HAL_FR30_MB91301_PFRG 0x410 +#define CYG_HAL_FR30_MB91301_PDRJ 0x13 +#define CYG_HAL_FR30_MB91301_DDRJ 0x403 +#define CYG_HAL_FR30_MB91301_PFRJ 0x413 + + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8 base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +static channel_data_t channels[2] = { + { CYG_HAL_FR30_MB91301_SER0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX}, + { CYG_HAL_FR30_MB91301_SER1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX}/*, + { CYG_HAL_FR30_MB91301_SER2_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART2_RX}*/ +}; + +//----------------------------------------------------------------------------- +// function for calculating and setting the baudrate + +static void cyg_hal_plf_serial_set_baudrate_internal(cyg_uint8 port, int baudrate){ + + float n, nn; + int t, tt; + + n = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) (32 * baudrate) - 1; + nn = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) (32 * baudrate) - 1.5; + + /* rounding */ + t = n; + tt = nn; + if ( (n-t) > (1 - (n-t)) ) t++; + if ( (nn-tt) > (1 - (nn-tt)) ) tt++; + + /* check which is better t or tt */ + + /* back calculation of baudrate from t and tt */ + n = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) ((2*t+2) * 16); + nn = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) ((2*tt+3) * 16); + + /* taking difference between wanted baudrate and back calculated br */ + if ((baudrate - n) < 0) + n = n - baudrate; + else + n = baudrate - n; + + if ((baudrate - nn) < 0) + nn = nn - baudrate; + else + nn = baudrate - nn; + + /* and finally take the best */ + if (n < nn){ + /* UCC1 = 0 */ + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x02); + HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, t); + } else { + /* UCC1 = 1 */ + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x82); + HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, tt); + } +} + +//----------------------------------------------------------------------------- +// The minimal init, get and put functions. All by polling. + +void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint8 port; + cyg_uint8 value; + + port = ((channel_data_t*)__ch_data)->base; + + // set the port direction and function registers to serial + switch (port){ + case CYG_HAL_FR30_MB91301_SER0_BASE: + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value | 0x2); + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x3); + if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0){ + cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); + } else { + cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); + } + break; + + case CYG_HAL_FR30_MB91301_SER1_BASE: + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value | 0x10); + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x18); + if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 1){ + cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); + } else { + cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); + } + break; +/* + case CYG_HAL_FR30_MB91301_SER2_BASE: + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRG, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRG, value | 0x40); + HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRG, value); + HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRG, value | 0x60); + break; +*/ + } + + + // set up U-Timer +/* HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x02); + // 115200 bps + HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, 0x7); + + cyg_hal_plf_serial_set_baudrate_internal(port, baudrate); +*/ + // setup UART + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SCR_OFFSET, 0x13); + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SMR_OFFSET, 0x30); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) +{ + cyg_uint8 ssr; + cyg_uint8 port; + + // wait for tx rdy + port = ((channel_data_t*)__ch_data)->base; + do + { + HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, ssr); + } while (!(ssr & BIT3)); + // Now, write it + HAL_WRITE_UINT8( port + CYG_HAL_FR30_MB91301_SODR_OFFSET, __ch ); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8 ssr; + cyg_uint8 port; + + port = ((channel_data_t*)__ch_data)->base; + HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, ssr); + if (!(ssr & BIT4)) + return false; + + HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SIDR_OFFSET, *ch); +// hal_diag_led(port); + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); +} + + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan; + cyg_bool res; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + delay_count = chan->msec_timeout; // delay in 1000 us steps + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + CYGACC_CALL_IF_DELAY_US(1000); + } + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan; + int ret = 0; + cyg_uint8 port; + cyg_uint8 value; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + port = ((channel_data_t*)__ch_data)->base; + HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, value); + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, value | BIT1); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + port = ((channel_data_t*)__ch_data)->base; + HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, value); + HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, value & ~BIT1); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + break; + case __COMMCTL_SETBAUD: + { + cyg_uint32 baud_rate; + va_list ap; + + va_start(ap, __func); + baud_rate = va_arg(ap, cyg_uint32); + va_end(ap); + port = ((channel_data_t*)__ch_data)->base; + cyg_hal_plf_serial_set_baudrate_internal(port, baud_rate); + } + break; + + case __COMMCTL_GETBAUD: + break; + default: + break; + } + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + *__ctrlc = 0; + return 0; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + +#define NUM_CHANNELS CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS + for (i = 0; i < NUM_CHANNELS; i++) { + + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[i].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel((void*)&channels[i]); + + // Setup procs in the vector table + + // Set COMM callbacks for channel + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); + +} + +//----------------------------------------------------------------------------- +// end of ser.c +