Mercurial > ecos
changeset 1160:71746e7a1cdc
* include/arch.inc: Changed mask for cause register interrupt bits
to 0x3f from 0x7f. The extra bit was wrong, but in all current
implementations, benign.
* include/mips-stub.h: Disabled use of 64 bit registers for TX49,
so we can work with the public release compiler.
| author | nickg |
|---|---|
| date | Wed, 06 Aug 2003 17:36:29 +0000 |
| parents | 46ec92b4d31c |
| children | e8588368a458 |
| files | packages/hal/mips/arch/current/ChangeLog packages/hal/mips/arch/current/include/arch.inc packages/hal/mips/arch/current/include/mips-stub.h |
| diffstat | 3 files changed, 11 insertions(+), 2 deletions(-) [+] |
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--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,12 @@ +2003-08-06 Andy Dyer <adyer@righthandtech.com> + + * include/arch.inc: Changed mask for cause register interrupt bits + to 0x3f from 0x7f. The extra bit was wrong, but in all current + implementations, benign. + + * include/mips-stub.h: Disabled use of 64 bit registers for TX49, + so we can work with the public release compiler. + 2003-04-27 Jonathan Larmour <jifl@eCosCentric.com> * src/vectors.S: Pass saved interrupt state pointer to interrupt
--- a/packages/hal/mips/arch/current/include/arch.inc +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -347,7 +347,7 @@ nop # delay slot and v0,v0,v1 # apply interrupt mask srl v0,v0,10 # shift interrupt bits down - andi v0,v0,0x7f # isolate 6 interrupt bits + andi v0,v0,0x3f # isolate 6 interrupt bits la v1,hal_intc_translation_table add v0,v0,v1 # index into table lb \vnum,0(v0) # pick up vector number
--- a/packages/hal/mips/arch/current/include/mips-stub.h +++ b/packages/hal/mips/arch/current/include/mips-stub.h @@ -97,7 +97,7 @@ typedef unsigned long target_register_t; typedef unsigned long long target_register_t; // We need to sign-extend the registers so GDB doesn't get confused. #define CYGARC_SIGN_EXTEND_REGISTERS -#elif defined(CYGPKG_HAL_MIPS_TX49) +#elif 0 // defined(CYGPKG_HAL_MIPS_TX49) // Even though we are only working with 32 bit registers, GDB expects 64 bits #define REGSIZE(X) 8 typedef unsigned long target_register_t;