Mercurial > ecos
changeset 2123:7af5a98be12b
Rework port configuration and handle parity errors better - from Will Wagner
| author | gthomas |
|---|---|
| date | Mon, 30 Jan 2006 23:28:35 +0000 |
| parents | cd6a5e166a38 |
| children | 272d1110cda1 |
| files | packages/devs/serial/powerpc/quicc/current/ChangeLog packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h packages/hal/powerpc/quicc/current/ChangeLog packages/hal/powerpc/quicc/current/include/ppc8xx.h |
| diffstat | 5 files changed, 32 insertions(+), 15 deletions(-) [+] |
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--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog +++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog @@ -1,3 +1,9 @@ +2006-01-27 Will Wagner <willw@carallon.com> + + * src/quicc_smc_serial.h: Removed unused structure + * src/quicc_smc_serial.c(quicc_smc_serial_config_port): Corrected CLEN in SMCMR + * src/quicc_smc_serial.c(quicc_smc_serial_DSR & quicc_scc_serial_DSR): Better handling of frame and parity errors + 2004-05-10 Robert Chenault <robertchenault@yahoo.com> * src/quicc_smc_serial.h: Added two casts of (int) on
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c +++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @@ -345,7 +345,7 @@ quicc_smc_serial_config_port(serial_chan ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode HAL_IO_BARRIER(); // Inforce I/O ordering // Disable port interrupts while changing hardware - _lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + _lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) | smc_select_stop_bits[new_config->stop] | smc_select_parity[new_config->parity]; // Stop transmitter while changing baud rate @@ -970,12 +970,17 @@ quicc_smc_serial_DSR(serial_channel *cha while (ctl->smc_smce & QUICC_SMCE_RX) { // Receive interrupt ctl->smc_smce = QUICC_SMCE_RX; // Reset interrupt state; - rxlast = (struct cp_bufdesc *) ( - (char *)eppc_base() + pram->rbptr ); + rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr); while (rxbd != rxlast) { if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) { - for (i = 0; i < rxbd->length; i++) { - (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + } else { + // is this necessary? + rxbd->ctrl &= QUICC_BD_CTL_MASK; + // should we report the error? } // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! HAL_DCACHE_IS_ENABLED(cache_state); @@ -1035,8 +1040,14 @@ quicc_scc_serial_DSR(serial_channel *cha rxlast = (struct cp_bufdesc *) ((char *)eppc_base() + pram->rbptr); while (rxbd != rxlast) { if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) { - for (i = 0; i < rxbd->length; i++) { - (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + if((rxbd->ctrl & (QUICC_BD_CTL_Frame | QUICC_BD_CTL_Parity)) == 0) { + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + } else { + // is this necessary? + rxbd->ctrl &= QUICC_BD_CTL_MASK; + // should we report the error? } // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! HAL_DCACHE_IS_ENABLED(cache_state);
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h +++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h @@ -58,13 +58,6 @@ #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions -static unsigned int smc_select_word_length[] = { - QUICC_SMCMR_CLEN(5), // 5 bits / word (char) - QUICC_SMCMR_CLEN(6), - QUICC_SMCMR_CLEN(7), - QUICC_SMCMR_CLEN(8) -}; - static unsigned int smc_select_stop_bits[] = { 0, QUICC_SMCMR_SB(1), // 1 stop bit
--- a/packages/hal/powerpc/quicc/current/ChangeLog +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -1,3 +1,8 @@ +2006-01-27 Will Wagner <willw@carallon.com> + + * include/ppc8xx.h: Add definition for frame and parity errors in BD ctrl. + Changed macro calculating SMCMR CLEN. + 2004-04-01 Robert Chenault <robertchenault@yahoo.com> * include/ppc8xx.h: Add definition for 8 bytes to spi_pram structure
--- a/packages/hal/powerpc/quicc/current/include/ppc8xx.h +++ b/packages/hal/powerpc/quicc/current/include/ppc8xx.h @@ -968,6 +968,8 @@ static inline EPPC *eppc_base(void) #define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list #define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx) #define QUICC_BD_CTL_Last 0x0800 // Last buffer in a sequence +#define QUICC_BD_CTL_Frame 0x0010 // Framing Error +#define QUICC_BD_CTL_Parity 0x0008 // Parity Error #define QUICC_BD_CTL_MASK 0xB000 // User settable bits // Command register @@ -996,7 +998,7 @@ static inline EPPC *eppc_base(void) #define QUICC_SMCE_RX 0x01 // Rx interrupt // SMC Mode Register -#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length +#define QUICC_SMCMR_CLEN(n) (n<<11) // Character length + parity + stop bits #define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2) #define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable) #define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)