Mercurial > ecos
changeset 2216:835a35352df8
* cdl/hal_arm_mac7100.cdl:
* include/hal_cache.h:
* include/hal_diag.h:
* include/mac7100_misc.h:
* include/plf_stub.h: unchanged from AT91
* include/var_arch.h:
* include/var_io.h:
* src/flash_security.S:
* src/hal_diag.c:
* src/mac7100_misc.c
New variant port - based on at91 variant by Gary Thomas
line wrap: on
line diff
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/ChangeLog @@ -0,0 +1,45 @@ +2006-05-24 Ilija Koco <ilijak@siva.com.mk> + + * cdl/hal_arm_mac7100.cdl: + * include/hal_cache.h: + * include/hal_diag.h: + * include/mac7100_misc.h: + * include/plf_stub.h: unchanged from AT91 + * include/var_arch.h: + * include/var_io.h: + * src/flash_security.S: + * src/hal_diag.c: + * src/mac7100_misc.c + New variant port - based on at91 variant by Gary Thomas + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/cdl/hal_arm_mac7100.cdl @@ -0,0 +1,125 @@ +# ==================================================================== +# +# hal_arm_mac7100.cdl +# +# Freescale MAC7100 HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett <nickg@calivar.com> +## Copyright (C) 2006 eCosCentric Ltd +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Koco <ilijak@siva.com.mk> +# Contributors: +# Date: 2006-02-03 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_MAC7100 { + display "Freescale MAC7100 variant HAL" + parent CYGPKG_HAL_ARM + define_header hal_arm_mac7100.h + include_dir cyg/hal + hardware + description " + The MAC7100 HAL package provides the support needed to run + eCos on Freescale MAC7100 based targets." + + compile flash_security.S hal_diag.c mac7100_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + implements CYGINT_HAL_ARM_ARCH_ARM7 + implements CYGINT_HAL_ARM_THUMB_ARCH + implements CYGINT_HAL_ARM_BIGENDIAN + requires { CYGHWR_HAL_ARM_BIGENDIAN == 1 } + + # Let the architectural HAL see this variant's files + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_ARCH_H" + } + + cdl_option CYGHWR_HAL_ARM_MAC7100 { + display "MAC7100 variant used" + flavor data + default_value {"MAC7121"} + legal_values {"MAC7111" "MAC7121" "MAC7116" } + description " + The MAC7100 microcontroller family has several variants, + the main differences being the amount of on-chip SRAM, + peripherals and their layout. This option allows the + platform HALs to select the specific microcontroller being + used." + } + + cdl_option CYGHWR_HAL_ARM_MAC7100_FIQ { + display "handle FIQ as an IRQ" + flavor bool + default_value 0 + description " + Enable this option if you need to handle FIQ interrupts in the + normal way, i.e. a FIQ interrupt will be treated as a normal IRQ + using the highest priority + " + } + + cdl_option CYGHWR_HAL_ARM_MAC7100_INTC_FIQDEF { + display "Set FIQDEF" + flavor data + default_value CYGHWR_HAL_ARM_MAC7100_FIQ ? 14 : 16 + legal_values 0 to 32 + description " + Set maximum level that shall be routed to IRQ. + " + } + + cdl_option CYGHWR_HAL_ARM_MAC7100_INTC_EMASK { + display "enable INTC to automatically handle CLMASK" + flavor data + default_value 0x20 + legal_values 0x00 0x20 + description " + Enable this option if you need INTC to automatically mask + lower level IRQ. + + - 0x00 - disable + - 0x20 - enable + + " + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/hal_cache.h @@ -0,0 +1,189 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/hal_diag.h @@ -0,0 +1,81 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas, tkoeller, ilijak +// Date: 2001-07-12 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +//----------------------------------------------------------------------------- +// LED +externC void hal_diag_led(int mask); + +//----------------------------------------------------------------------------- +// delay + +externC void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(n) hal_delay_us(n); + +//----------------------------------------------------------------------------- +// reset + +extern void hal_mac7100_reset_cpu(void); + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/mac7100_misc.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_MAC7100_MISC_H +#define CYGONCE_HAL_MAC7100_MISC_H +//============================================================================= +// +// mac7100_misc.h +// +// Variant specific functions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) eCosCentric Ltd +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-02-03 +// Purpose: MAC7100 specific hal functions +// Description: +// Usage: #include <cyg/hal/mac7100_misc.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// ********************************************************************* +// +// ESCI Module +// +// ********************************************************************* + +externC void hal_mac7100_esci_pins(cyg_uint32 i_esci); + +#endif // CYGONCE_HAL_MAC7100_MISC_H +// end of mac7100_misc.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/plf_stub.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas +// Date: 2001-07-12 +// Purpose: Platform HAL stub support for MAC7100 based boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/arm_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/var_arch.h @@ -0,0 +1,75 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// MAC7100 variant architecture overrides +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com> +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-02-03 +// Purpose: MAC7100 variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +//-------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. These implementations halt the system core clock. + +#ifndef HAL_IDLE_THREAD_ACTION + +#if defined(CYGHWR_HAL_ARM_MAC7100_MAC7121) +// No idle action for the MAC7121 +#else +#error Unknown MAC7100 variant + +#endif + +#endif + +#endif // CYGONCE_HAL_VAR_ARCH_H +//----------------------------------------------------------------------------- +// end of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/include/var_io.h @@ -0,0 +1,464 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2006 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-02-03 +// Purpose: MAC7100 variant specific registers +// Description: based on freescale's mac7100.h +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/plf_io.h> + +#if !defined HAL_IO_MACROS_NO_ADDRESS_MUNGING +#define HAL_IO_MACROS_NO_ADDRESS_MUNGING 1 +#endif // HAL_IO_MACROS_NO_ADDRESS_MUNGING + +// ********************************************************************* +// +// INTC Module +// +// ********************************************************************* + +// Interrupt Controller Definitions +#define MAC7100_INTC_BASE (0xFC048000) + +#define MAC7100_IPRH_OFFSET (0x0000) +#define MAC7100_IPRL_OFFSET (0x0004) +#define MAC7100_IMRH_OFFSET (0x0008) +#define MAC7100_IMRL_OFFSET (0x000C) +#define MAC7100_INTFRCH_OFFSET (0x0010) +#define MAC7100_INTFRCL_OFFSET (0x0014) +#define MAC7100_ICONFIG_OFFSET (0x001B) +#define MAC7100_SIMR_OFFSET (0x001C) +#define MAC7100_CIMR_OFFSET (0x001D) +#define MAC7100_CLMASK_OFFSET (0x001E) // CLMASK - Current Level Mask Register +#define MAC7100_SLMASK_OFFSET (0x001F) // SLMASK - Saved Level Mask Register +#define MAC7100_ICR_OFFSET (0x0040) +#define MAC7100_IRQIACK_OFFSET (0x00EC) +#define MAC7100_FIQIACK_OFFSET (0x00F0) + +#define MAC7100_INTC_IPRH(intc_base) (intc_base + MAC7100_IPRH_OFFSET) +#define MAC7100_INTC_IPRL(intc_base) (intc_base + MAC7100_IPRL_OFFSET) +#define MAC7100_INTC_IMRH(intc_base) (intc_base + MAC7100_IMRH_OFFSET) +#define MAC7100_INTC_IMRL(intc_base) (intc_base + MAC7100_IMRL_OFFSET) +#define MAC7100_INTC_INTFRC(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET) +#define MAC7100_INTC_INTFRCH(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET) +#define MAC7100_INTC_INTFRCL(intc_base) (intc_base + MAC7100_INTFRCL_OFFSET) +#define MAC7100_INTC_ICONFIG(intc_base) (intc_base + MAC7100_ICONFIG_OFFSET) +#define MAC7100_INTC_IRQIACK(intc_base) (intc_base + MAC7100_IRQIACK_OFFSET) +#define MAC7100_INTC_FIQIACK(intc_base) (intc_base + MAC7100_FIQIACK_OFFSET) +#define MAC7100_INTC_ICR(intc_base,src) (intc_base + MAC7100_ICR_OFFSET + src) +#define MAC7100_INTC_SIMR(intc_base) (intc_base + MAC7100_SIMR_OFFSET) +#define MAC7100_INTC_CIMR(intc_base) (intc_base + MAC7100_CIMR_OFFSET) +#define MAC7100_INTC_CLMASK(intc_base) (intc_base + MAC7100_CLMASK_OFFSET) +#define MAC7100_INTC_SLMASK(intc_base) (intc_base + MAC7100_SLMASK_OFFSET) + +#define MAC7100_INTC_INT_LEVEL(lev) (lev) + +// hardware interrupt source vector numbers +#define MAC7100_EDMA0_IV (0) +#define MAC7100_EDMA1_IV (1) +#define MAC7100_EDMA2_IV (2) +#define MAC7100_EDMA3_IV (3) +#define MAC7100_EDMA4_IV (4) +#define MAC7100_EDMA5_IV (5) +#define MAC7100_EDMA6_IV (6) +#define MAC7100_EDMA7_IV (7) +#define MAC7100_EDMA8_IV (8) +#define MAC7100_EDMA9_IV (9) +#define MAC7100_EDMA10_IV (10) +#define MAC7100_EDMA11_IV (11) +#define MAC7100_EDMA12_IV (12) +#define MAC7100_EDMA13_IV (13) +#define MAC7100_EDMA14_IV (14) +#define MAC7100_EDMA15_IV (15) +#define MAC7100_EDMA_Error_IV (16) +#define MAC7100_MCM_SWT_IV (17) +#define MAC7100_CRG_IV (18) +#define MAC7100_PIT1_IV (19) +#define MAC7100_PIT2_IV (20) +#define MAC7100_PIT3_IV (21) +#define MAC7100_PIT4_RTI_IV (22) +#define MAC7100_VREG_IV (23) +#define MAC7100_CAN_A_MB_IV (24) +#define MAC7100_CAN_A_MB14_IV (25) +#define MAC7100_CAN_A_Error_IV (26) +#define MAC7100_CAN_B_MB_IV (27) +#define MAC7100_CAN_B_MB14_IV (28) +#define MAC7100_CAN_B_Error_IV (29) +#define MAC7100_CAN_C_MB_IV (30) +#define MAC7100_CAN_C_MB14_IV (31) +#define MAC7100_CAN_C_Error_IV (32) +#define MAC7100_CAN_D_MB_IV (33) +#define MAC7100_CAN_D_MB14_IV (34) +#define MAC7100_CAN_D_Error_IV (35) +#define MAC7100_I2C_IV (36) +#define MAC7100_DSPI_A_IV (37) +#define MAC7100_DSPI_B_IV (38) +#define MAC7100_ESCI_A_IV (39) +#define MAC7100_ESCI_B_IV (40) +#define MAC7100_ESCI_C_IV (41) +#define MAC7100_ESCI_D_IV (42) +#define MAC7100_EMIOS0_IV (43) +#define MAC7100_EMIOS1_IV (44) +#define MAC7100_EMIOS2_IV (45) +#define MAC7100_EMIOS3_IV (46) +#define MAC7100_EMIOS4_IV (47) +#define MAC7100_EMIOS5_IV (48) +#define MAC7100_EMIOS6_IV (49) +#define MAC7100_EMIOS7_IV (50) +#define MAC7100_EMIOS8_IV (51) +#define MAC7100_EMIOS9_IV (52) +#define MAC7100_EMIOS10_IV (53) +#define MAC7100_EMIOS11_IV (54) +#define MAC7100_EMIOS12_IV (55) +#define MAC7100_EMIOS13_IV (56) +#define MAC7100_EMIOS14_IV (57) +#define MAC7100_EMIOS15_IV (58) +#define MAC7100_ATD_IV (59) +#define MAC7100_CFM_IV (60) +#define MAC7100_PIM_IV (61) +#define MAC7100_IRQ_IV (62) +#define MAC7100_XIRQ_IV (63) + +#define MAC7100_IRQ_SPURIOUS (-1) + +// ******************************************************************* +// +// eSCI Module +// Note: eSCI definitions are in cyg/devs/ser_esci.h +// ******************************************************************* +#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE 0xFC0C4000 +#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR MAC7100_ESCI_A_IV + +#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE 0xFC0C8000 +#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR MAC7100_ESCI_B_IV + +#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE 0xFC0CC000 +#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR MAC7100_ESCI_C_IV + +#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE 0xFC0D0000 +#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR MAC7100_ESCI_D_IV + +// ********************************************************************* +// +// PIT Module +// +// ********************************************************************* + +// Periodic Interrupt Timer Module Definitions + +#define MAC7100_PIT_BASE (0xFC08C000) +#define MAC7100_TLVAL0_OFFSET (0x0000) +#define MAC7100_TVAL0_OFFSET (0x0080) + +#define MAC7100_PIT_TLVAL(pit_base,chan) \ + (pit_base + MAC7100_TLVAL0_OFFSET + (4 * chan)) +#define MAC7100_PIT_TVAL(pit_base,chan) \ + (pit_base + MAC7100_TVAL0_OFFSET + (4 * chan)) + +#define MAC7100_PITFLG_OFFSET (0x0100) +#define MAC7100_PITINTEN_OFFSET (0x0104) +#define MAC7100_PITINTSEL_OFFSET (0x0108) +#define MAC7100_PITEN_OFFSET (0x010C) +#define MAC7100_PITCTRL_OFFSET (0x0110) + +#define MAC7100_PIT_FLAG_RTIF (0x00000001) +#define MAC7100_PIT_FLAG_TIF(chan) (0x00000001 << chan) +#define MAC7100_PIT_INTSEL_ISEL(chan) (0x00000001 << chan) +#define MAC7100_PIT_INTEN_RTIE (0x00000001) +#define MAC7100_PIT_INTEN_TIE(chan) (0x00000001 << chan) + +#define MAC7100_PIT_EN_RTIEN (0x00000001) +#define MAC7100_PIT_EN_PEN(chan) (0x00000001 << chan) + +#define MAC7100_PIT_FLG(pit_base) (pit_base + MAC7100_PITFLG_OFFSET) +#define MAC7100_PIT_INTEN(pit_base) (pit_base + MAC7100_PITINTEN_OFFSET) +#define MAC7100_PIT_INTSEL(pit_base) (pit_base + MAC7100_PITINTSEL_OFFSET) +#define MAC7100_PIT_EN(pit_base) (pit_base + MAC7100_PITEN_OFFSET) + +#define MAC7100_PIT_CTRL(pit_base) (pit_base + MAC7100_PITCTRL_OFFSET) +#define MAC7100_PIT_MDIS (0x01000000) + + +// ********************************************************************* +// +// PIM Module +// +// *********************************************************************/ + +#define MAC7100_PIM_BASE (0xFC0E8000) + +#define MAC7100_PORT_A_OFFSET (0x000) +#define MAC7100_PORT_B_OFFSET (0x040) +#define MAC7100_PORT_C_OFFSET (0x080) +#define MAC7100_PORT_D_OFFSET (0x0C0) +#define MAC7100_PORT_E_OFFSET (0x100) +#define MAC7100_PORT_F_OFFSET (0x140) +#define MAC7100_PORT_G_OFFSET (0x180) +#define MAC7100_PORT_H_OFFSET (0x1C0) +#define MAC7100_PORT_I_OFFSET (0x200) + +// PORT Pin Configuration Registers +#define MAC7100_PIM_CONFIG(port,pin) (MAC7100_PIM_BASE+port+((pin)*2)) +// Port Wide Interrupt Flag Register +#define MAC7100_PIM_PORTIFR(port) (MAC7100_PIM_BASE+port+0x20) +// Port Wide Data Read/Write Register +#define MAC7100_PIM_PORTDATA(port) (MAC7100_PIM_BASE+port+0x24) +// Port Wide Input Register +#define MAC7100_PIM_PORTIR(port) (MAC7100_PIM_BASE+port+0x26) +// Port Pin Data Registers +#define MAC7100_PIM_DATA(port,pin) (MAC7100_PIM_BASE+port+0x28+pin) + +// Global Interrupt Status Register +#define MAC7100_PIM_GLBLINT (MAC7100_PIM_BASE+0x03C0) +// PIM Configuration Register +#define MAC7100_PIM_PIMCONFIG (MAC7100_PIM_BASE+0x03C2) +// TDI Pin Configuration Register +#define MAC7100_PIM_CONFIG_TDI (MAC7100_PIM_BASE+0x03C4) +// TDO Pin Configuration Register +#define MAC7100_PIM_CONFIG_TDO (MAC7100_PIM_BASE+0x03C6) +// TMS Pin Configuration Register +#define MAC7100_PIM_CONFIG_TMS (MAC7100_PIM_BASE+0x03C8) +// TCK Pin Configuration Register +#define MAC7100_PIM_CONFIG_TCK (MAC7100_PIM_BASE+0x03CA) +// TA Pin Configuration Register +#define MAC7100_PIM_CONFIG_TA (MAC7100_PIM_BASE+0x03CC) + +// Bit definitions and macros for PIM_PA_CONFIGn +// Pin Interrupt Flag Register +#define MAC7100_PIM_PIFR (0x0001) +// Pin Interrupt Enable Register +#define MAC7100_PIM_PIER (0x0002) +// Pull-up/down Enable Register +#define MAC7100_PIM_PULL(x) (((x)&0x0003)<<2) +// Reduced Drive Strength Register +#define MAC7100_PIM_RDR (0x0010) +// Open Drain Enable Register +#define MAC7100_PIM_ODER (0x0020) +// Data Direction Register +#define MAC7100_PIM_DDR (0x0040) +#define MAC7100_PIM_MODE (0x0080) +#define MAC7100_PIM_MODE_PERIPHERAL MAC7100_PIM_MODE + +// Bit definitions and macros for PIM_GLBLINT +// Interrupt Pending +#define MAC7100_PIM_INT_PENDING(x) (((x)&0x01FF)<<0) + +// Bit definitions and macros for PIM_PIMCONFIG +// Clock Enable for the EIM module +#define MAC7100_PIM_PORTHSEL (0x0001) +// Port H Select +#define MAC7100_PIM_EIMCLKEN (0x0002) + +#define MAC7100_PIM_PORT32IR(port32ir) (MAC7100_PIM_BASE+0x03E0+port32ir) + +#define MAC7100_PIM_PORT32IR_AB (0x00) +#define MAC7100_PIM_PORT32IR_CD (0x04) +#define MAC7100_PIM_PORT32IR_EF (0x08) +#define MAC7100_PIM_PORT32IR_GH (0x0C) +#define MAC7100_PIM_PORT32IR_BC (0x10) +#define MAC7100_PIM_PORT32IR_DE (0x14) +#define MAC7100_PIM_PORT32IR_FG (0x18) +#define MAC7100_PIM_PORT32IR_HI (0x1C) + + +// ******************************************************************** +// +// CRG Module +// +// ******************************************************************** + +// Register read/write macros +#define MAC7100_CRG_BASE 0xFC088000 // SYNR - Synthesizer Register +#define MAC7100_CRG_SYNR 0xFC088000 // SYNR - Synthesizer Register +#define MAC7100_CRG_REFDV 0xFC088001 // REFDV - Reference Divider Register +#define MAC7100_CRG_CTFLG 0xFC088002 // CTFLG - Test Flags Register (reserved) +#define MAC7100_CRG_CRGFLG 0xFC088003 // CRGFLG - Flags Register +#define MAC7100_CRG_CRGINT 0xFC088004 // CRGINT - Interrupt Enable Register +#define MAC7100_CRG_CLKSEL 0xFC088005 // CLKSEL - Clock Select Register +#define MAC7100_CRG_PLLCTL 0xFC088006 // PLLCTL - PLL Control Register +#define MAC7100_CRG_SDMCTL 0xFC088007 // SDMCTL - STOP/DOZE Control Register +#define MAC7100_CRG_BDMCTL 0xFC088008 // BDMCTL - BDM Control Register +#define MAC7100_CRG_FORBYP 0xFC088009 // FORBYP - Force and Bypass Test +#define MAC7100_CRG_CTCTL 0xFC08800A // CTCTL - Test Control Register (resvd) + +// Bit definitions and macros for CRG_SYNR +#define MAC7100_CRG_SYN(x) (((x)&0x3F)<<0) // Synthesizer Count value + +// Bit definitions and macros for CRG_REFDV +#define MAC7100_CRG_REFD(x) (((x)&0x0F)<<0) //Reference divider + +// Bit definitions and macros for CRG_CRGFLG +#define MAC7100_CRG_SCM (0x01) //Self Clock Mode Status +#define MAC7100_CRG_SCMIF (0x02) //Self Clock Mode Interrupt Flag +#define MAC7100_CRG_TRACK (0x04) //Track Status +#define MAC7100_CRG_LOCK (0x08) //Lock Status +#define MAC7100_CRG_LOCKIF (0x10) //PLL Lock Interrupt Flag +#define MAC7100_CRG_LVRF (0x20) //Low Voltage Reset Flag +#define MAC7100_CRG_PORF (0x40) //Power on Reset Flag +#define MAC7100_CRG_STPEF (0x80) //Stop Entry Flag + +// Bit definitions and macros for CRG_CRGINT +#define MAC7100_CRG_SCMIE (0x02) //Self Clock Mode Interrupt Enable +#define MAC7100_CRG_LOCKIE (0x10) //Lock Interrupt Enable + +// Bit definitions and macros for CRG_CLKSEL +#define MAC7100_CRG_SWTDOZE (0x01) //SWT stops in Doze Mode +#define MAC7100_CRG_RTIDOZE (0x02) /* RTI stops in Doze Mode */ +#define MAC7100_CRG_PLLDOZE (0x08) /* PLL stops in Doze Mode */ +#define MAC7100_CRG_DOZE_ROA (0x10) /* Reduced Osc Amp in Doze Mode */ +#define MAC7100_CRG_PSTP (0x40) /* Pseudo Stop */ +#define MAC7100_CRG_PLLSEL (0x80) /* PLL Select */ + +// Bit definitions and macros for CRG_PLLCTL +#define MAC7100_CRG_SCME (0x01) //Self Clock Mode Enable +#define MAC7100_CRG_PWE (0x02) //SWT Enable during Pseudo Stop +#define MAC7100_CRG_PRE (0x04) //RTI Enable during Pseudo Stop +#define MAC7100_CRG_FSTWKP (0x08) //Fast Wake-up from Full Stop Bit +#define MAC7100_CRG_ACQ (0x10) //Acquisition +#define MAC7100_CRG_AUTO (0x20) //Automatic Bandwidth Control +#define MAC7100_CRG_PLLON (0x40) //Phase Lock Loop On +#define MAC7100_CRG_CME (0x80) //Clock Monitor Enable + +// Bit definitions and macros for CRG_SDMCTL +#define MAC7100_CRG_STOP (0x01) //STOP mode +#define MAC7100_CRG_DOZE (0x02) //DOZE mode + +// Bit definitions and macros for CRG_BDMCTL +#define MAC7100_CRG_RSBCK (0x40) //SWT & RTI stop in Active BDM mode + + +// ********************************************************************* +// +// MCM Module +// +// ********************************************************************* + +// Register read/write macros +#define MAC7100_MCM_PCT 0xFC040000 // +#define MAC7100_MCM_REV 0xFC040002 // +#define MAC7100_MCM_AMC 0xFC040004 // +#define MAC7100_MCM_ASC 0xFC040006 // +#define MAC7100_MCM_IMC 0xFC040008 // +// MRSR - Miscellaneous Reset Status Register +#define MAC7100_MCM_MRSR 0xFC04000F +// MWCR - Miscellaneous Wakeup Control Register +#define MAC7100_MCM_MWCR 0xFC040013 +// MSWTCR - Miscellaneous Software Watchdog Timer Control Register +#define MAC7100_MCM_MSWTCR 0xFC040016 +// MSWTSR - Miscellaneous Software Watchdog Timer Service Register +#define MAC7100_MCM_MSWTSR 0xFC04001B +// MSWTIR - Miscellaneous Software Watchdog Timer Interrupt Register +#define MAC7100_MCM_MSWTIR 0xFC04001F +// AAMR - AXBS Address Map Register +#define MAC7100_MCM_AAMR 0xFC040020 +// CFADR - Core Fault Address Register +#define MAC7100_MCM_CFADR 0xFC040070 +// CFLOC - Core Fault Location Register +#define MAC7100_MCM_CFLOC 0xFC040076 +// CFATR - Core Fault Attributes Register +#define MAC7100_MCM_CFATR 0xFC040077 +// CFDTR - Core Fault Data Register +#define MAC7100_MCM_CFDTR 0xFC04007C + +// Bit definitions and macros for MCM_AMC + +// AXBS Master Configuration +#define MAC7100_MCM_AXMC(x) (((x)&0x00FF)<<0) + +// Bit definitions and macros for MCM_ASC +// AXBS Slave Configuration +#define MAC7100_MCM_AXSC(x) (((x)&0x00FF)<<0) +#define MAC7100_MCM_DP64 (0x8000) // 64-bit Datapath + +// Bit definitions and macros for MCM_MRSR +#define MAC7100_MCM_SWTR (0x20) // Watchdog Timer Reset +#define MAC7100_MCM_DIR (0x40) // Device Input Reset +#define MAC7100_MCM_POR (0x80) // Power-On Reset + +// Bit definitions and macros for MCM_MWCR +#define MAC7100_MCM_PRILVL(x) (((x)&0x0F)<<0) // Interrupt Priority Level +#define MAC7100_MCM_ENBWCR (0x80) // Enable WCR + +// Bit definitions and macros for MCM_MSWTCR +#define MAC7100_MCM_SWT(x) (((x)&0x001F)<<0) // Watchdog Time-Out Period +#define MAC7100_MCM_SWRI(x) (((x)&0x0003)<<5) // Watchdog Reset/Interrupt +#define MAC7100_MCM_SWE (0x0080) // Watchdog Enable +#define MAC7100_MCM_SWRWH (0x0100) // Watchdog Run While Halted +#define MAC7100_MCM_SWCIN16 (0x0200) // Force SWT CarryIn16 +#define MAC7100_MCM_RO (0x8000) // Read-Only + +// Bit definitions and macros for MCM_MSWTIR +#define MAC7100_MCM_SWTIC (0x01) // Watchdog Interrupt Flag + +// Bit definitions and macros for MCM_AAMR + + +// Address 0 Slave Number +#define MAC7100_MCM_ASLAVE(adr_reg,sl_n) (((sl_n)&0x00000007)<<(adr_reg*4) +// Enable Address Region 0 +#define MAC7100_MCM_EA(adr_reg) (0x00000008<<(adr_reg*4)) + +// Bit definitions and macros for MCM_CFLOC +#define MAC7100_MCM_LOCALERR (0x80) // Bus Error Indicator + +// Bit definitions and macros for MCM_CFATR +// Protection fault type +#define MAC7100_MCM_PROTECTION(x) (((x)&0x0F)<<0) +// 8-16-32-64-bit core access +#define MAC7100_MCM_SIZE(x) (((x)&0x07)<<4) +// Core read/write access +#define MAC7100_MCM_WRITE (0x80) + +//============================================================================= +// FIQ interrupt vector which is shared by all HAL variants. + +#define CYGNUM_HAL_INTERRUPT_FIQ 0 +#endif // CYGONCE_HAL_VAR_IO_H +//----------------------------------------------------------------------------- +// end of var_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/src/flash_security.S @@ -0,0 +1,77 @@ +/*========================================================================== +// +// flash_security.S +// +// MAC7100 Flash security area +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2006 eCosCentric Ltd +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-04-11 +// Purpose: HAL board support +// Description: MAC7100 Flash security area. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +///////////////////////////////////////////////////////////////////////////// +// This section contains Common Flash Module (CFM) configuration field +// For detail description see Common Flash Module (CFM) chapter +// @ MAC7100 Microcontroller Familly Reference Manual +// +// Deafault factorry setting: +// 0xffffffff for All words except Flash Security Word +// 0xfffffffe for Flash Security Word +///////////////////////////////////////////////////////////////////////////// + + .section ".mac7100_flash_security", "a" + .code 32 + .global VAE_MAC7100_FlashSecurity +VAE_MAC7100_FlashSecurity: + .long 0xffffffff // Backdoor Comparison Key bit 63-32 + .long 0xffffffff // Backdoor Comparison key bit 31-0 + .long 0xffffffff // Program FLASH protection Bytes + .long 0xffffffff // Program FLASH SUPV Access Bytes + .long 0xffffffff // Program FLASH DATA Access Bytes + .long 0xfffffffe // Flash Security Word + .long 0xffffffff // Data FLASH protection, SUPV access, DATA access + + .long 0xe0f00420 // Just a placeholder (round to 0x420) + .end + +//-------------------------------------------------------------------------- +// EOF flash_security.S
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/src/hal_diag.c @@ -0,0 +1,385 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-04-15 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + */ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/var_io.h> // +#include <cyg/devs/ser_esci.h> // ESCI registers + +//----------------------------------------------------------------------------- +typedef struct { + void *base; + cyg_int32 msec_timeout; + int isr_vector; + int isr_level; + int baud_rate; +} channel_data_t; + + + +//----------------------------------------------------------------------------- + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c); + + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 *esci_base = chan->base; + + + // Reset device + // 8-1-no parity. + + HAL_WRITE_UINT8(FREESCALE_ESCI_CR3(esci_base), 0); + HAL_WRITE_UINT16(FREESCALE_ESCI_LINCTRL(esci_base), 0); + HAL_WRITE_UINT16(FREESCALE_ESCI_BD(esci_base), + FREESCALE_ESCI_BAUD(chan->baud_rate)); + + // Enable RX and TX + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), (FREESCALE_ESCI_CR12_TE | + FREESCALE_ESCI_CR12_RE)); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, char ch_out) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base; + cyg_uint16 esci_sr; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + } while (!(esci_sr & FREESCALE_ESCI_SR_TDRE)); + + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_TDRE); + HAL_WRITE_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_out); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base; + cyg_uint16 esci_sr; + cyg_uint8 ch_in; + + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + if (!(esci_sr & FREESCALE_ESCI_SR_RDRF)) + return false; + + HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in); + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF); + *p_ch_in = ch_in; + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in) +{ + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // delay in .1 ms steps + delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10; + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint16 ser_port_reg; + int ret = 0; + va_list ap; + + CYGARC_HAL_SAVE_GP(); + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + cyg_hal_plf_serial_init_channel(chan); + ret = 0; + break; + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + + HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg); + ser_port_reg |= FREESCALE_ESCI_CR12_RIE; + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg); + + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + + HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg); + ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE; + HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + default: + break; + } + + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base; + cyg_uint16 esci_sr; + int res = 0; + cyg_uint8 ch_in; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); + if (esci_sr & FREESCALE_ESCI_SR_RDRF){ + HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in); + if( cyg_hal_is_break( &ch_in , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF); + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static channel_data_t mac7100_ser_channels[4] = { + { (cyg_uint16*)FREESCALE_ESCI_A_BASE, 1000, MAC7100_ESCI_A_IV, + MAC7100_ESCI_A_LEVEL, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, + { (cyg_uint16*)FREESCALE_ESCI_B_BASE, 1000, MAC7100_ESCI_B_IV, + MAC7100_ESCI_B_LEVEL, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, + { (cyg_uint16*)FREESCALE_ESCI_C_BASE, 1000, MAC7100_ESCI_C_IV, + MAC7100_ESCI_C_LEVEL, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, + { (cyg_uint16*)FREESCALE_ESCI_D_BASE, 1000, MAC7100_ESCI_D_IV, + MAC7100_ESCI_D_LEVEL, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}, +}; + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channels + cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[0]); +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1 + cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[1]); +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2 + cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[2]); +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 3 + cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[3]); +#endif + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1 + // Set channel 1 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2 + CYGACC_CALL_IF_SET_CONSOLE_COMM(2); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[2]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 3 + CYGACC_CALL_IF_SET_CONSOLE_COMM(3); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[3]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); +#endif + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/mac7100/var/current/src/mac7100_misc.c @@ -0,0 +1,341 @@ +/*========================================================================== +// +// mac7100_misc.c +// +// HAL misc board support code for Freescale MAC7100 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett <nickg@calivar.com> +// Copyright (c) 2006 eCosCentric Ltd +// +// Ecos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Koco <ilijak@siva.com.mk> +// Contributors: +// Date: 2006-04-12 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // necessary? +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_if.h> // calling interface +#include <cyg/hal/hal_misc.h> // helper functions +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/drv_api.h> // HAL ISR support +#endif +#include <cyg/hal/var_io.h> // platform registers +#include <cyg/devs/ser_esci.h> // ESCI registers +#include <pkgconf/io_serial_freescale_esci.h> + +// ------------------------------------------------------------------------- +// Clock support + +static cyg_uint32 _period; + +void hal_clock_initialize(cyg_uint32 period) +{ + CYG_ADDRESS pit_base = MAC7100_PIT_BASE; + cyg_uint32 pit_en; + + CYG_ASSERT(period < 0x10000, "Invalid clock period"); + + // Disable counter + HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + pit_en &= ~MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK); + HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + + // Set registers + _period=period; + HAL_WRITE_UINT32(MAC7100_PIT_TLVAL(pit_base, CYGNUM_PIT_CHAN_CLOCK), + period); + + // Start timer + pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK); + HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + + // Enable timer interrupt + HAL_READ_UINT32(MAC7100_PIT_INTEN(pit_base), pit_en); + pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK); + HAL_WRITE_UINT32(MAC7100_PIT_INTEN(pit_base), pit_en); + + HAL_READ_UINT32(MAC7100_PIT_INTSEL(pit_base), pit_en); + pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK); + HAL_WRITE_UINT32(MAC7100_PIT_INTSEL(pit_base), pit_en); +} + +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + HAL_WRITE_UINT32(MAC7100_PIT_FLG(MAC7100_PIT_BASE), + MAC7100_PIT_FLAG_TIF(CYGNUM_PIT_CHAN_CLOCK)); +} + + +void hal_clock_read(cyg_uint32 *pvalue) +{ + cyg_uint32 val; + + HAL_READ_UINT32(MAC7100_PIT_TLVAL(MAC7100_PIT_BASE,CYGNUM_PIT_CHAN_CLOCK), + val); + *pvalue = _period-val; +} + +// ------------------------------------------------------------------------- +// +// Delay for some number of micro-seconds +// + +#if CYGNUM_PIT_CHAN_US!=0 +#define CYGNUM_1_US (CYGNUM_HAL_ARM_MAC7100_CLOCK_SPEED/2000000) +#else +#define CYGNUM_1_US (CYGNUM_HAL_ARM_MAC7100_F_OSC/1000000) +#endif + +void hal_delay_us(cyg_int32 usecs) +{ + CYG_ADDRESS pit_base = MAC7100_PIT_BASE; + cyg_uint32 pit_en; + + + // Clear flag + HAL_WRITE_UINT32(MAC7100_PIT_FLG(pit_base), + MAC7100_PIT_FLAG_TIF(CYGNUM_PIT_CHAN_US)); + + // Set timer + HAL_WRITE_UINT32(MAC7100_PIT_TLVAL(pit_base, CYGNUM_PIT_CHAN_US), + usecs*CYGNUM_1_US-1); + HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_US); + HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + + do { + HAL_READ_UINT32(MAC7100_PIT_FLG(pit_base), pit_en); + }while (!(pit_en & MAC7100_PIT_FLAG_TIF(CYGNUM_PIT_CHAN_US))); + + // Disable counter + HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en); + pit_en &= ~MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_US); + HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en); +} + + +// ------------------------------------------------------------------------- +// Hardware init + +void hal_intc_init(void); +void hal_pit_init(void); +static void hal_mac7100_esci_pins(cyg_uint32); +void hal_hardware_init(void) +{ + // Reset all interrupts + // + + // Flush internal priority level stack + // + + // Set up eCos/ROM interfaces +#if (defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_A) || \ + (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0) + hal_mac7100_esci_pins(FREESCALE_ESCI_A_I); +#endif +#if (defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_B) || \ + (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1) + hal_mac7100_esci_pins(FREESCALE_ESCI_B_I); +#endif +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_C + hal_mac7100_esci_pins(FREESCALE_ESCI_C_I); +#endif +#if defined CYGPKG_IO_SERIAL_FREESCALE_ESCI_D + hal_mac7100_esci_pins(FREESCALE_ESCI_D_I); +#endif + + hal_intc_init(); // Initialize interrupt controller + hal_pit_init(); // Initilaize CLOCK for channels 1..10 + hal_if_init(); +} + +void hal_pit_init(void) +{ + cyg_uint32 pit_ctrl; + + CYG_ADDRESS pit_base=MAC7100_PIT_BASE; + + HAL_READ_UINT32(MAC7100_PIT_CTRL(pit_base), pit_ctrl); + pit_ctrl &= ~MAC7100_PIT_MDIS; + HAL_WRITE_UINT32(MAC7100_PIT_CTRL(pit_base), pit_ctrl); +} + + +// ------------------------------------------------------------------------- +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. + +typedef struct ClSlMask_T { + cyg_uint8 ClMask; + cyg_uint8 SlMask; +} ClSlMask_T; + +static ClSlMask_T ClSlMasks[CYGNUM_HAL_ISR_COUNT]; + +void hal_intc_init(void) +{ + cyg_uint8 iconfig; + CYG_ADDRESS intc_base=MAC7100_INTC_BASE; + + iconfig = (CYGHWR_HAL_ARM_MAC7100_INTC_FIQDEF | + CYGHWR_HAL_ARM_MAC7100_INTC_EMASK); + HAL_WRITE_UINT8(MAC7100_INTC_ICONFIG(intc_base), iconfig); +} + +int hal_IRQ_handler(void) +{ + CYG_ADDRESS intc_base=MAC7100_INTC_BASE; + cyg_int8 irq_num; + ClSlMask_T clslmask; + + HAL_READ_UINT8(MAC7100_INTC_CLMASK(intc_base), clslmask.ClMask); + HAL_READ_UINT8(MAC7100_INTC_SLMASK(intc_base), clslmask.SlMask); +#ifdef CYGHWR_HAL_ARM_MAC7100_FIQ + HAL_READ_UINT8(MAC7100_FIQIACK(intc_base), irq_num); + if((irq_num-=CYGNUM_HAL_ISR_COUNT)<0){ +#endif //CYGHWR_HAL_ARM_MAC7100_FIQ + HAL_READ_UINT8(MAC7100_INTC_IRQIACK(intc_base), irq_num); + if((irq_num-=CYGNUM_HAL_ISR_COUNT)<0){ + irq_num=CYGNUM_HAL_INTERRUPT_NONE; + }else{ + ClSlMasks[irq_num]=clslmask; + } + return irq_num; +#ifdef CYGHWR_HAL_ARM_MAC7100_FIQ + } +#endif // CYGHWR_HAL_ARM_MAC7100_FIQ +} + +// ------------------------------------------------------------------------- +// Interrupt control +// + +void hal_interrupt_mask(int vector) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_WRITE_UINT8(MAC7100_INTC_SIMR(MAC7100_INTC_BASE), vector); +} + +void hal_interrupt_unmask(int vector) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_WRITE_UINT8(MAC7100_INTC_CIMR(MAC7100_INTC_BASE), vector); +} + +void hal_interrupt_acknowledge(int vector) +{ + // ?? No check for valid vector here! Spurious interrupts + // ?? must be acknowledged, too. + + if(vector>=0) + HAL_WRITE_UINT8(MAC7100_INTC_CLMASK(MAC7100_INTC_BASE), + ClSlMasks[vector].ClMask); +} + +void hal_interrupt_configure(int vector, int level, int up) +{ + // TO DO +} + +void hal_interrupt_set_level(int vector, int level) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + CYG_ASSERT(level >=0 level <= 15, "Invalid level"); + + HAL_WRITE_UINT8(MAC7100_INTC_ICR(MAC7100_INTC_BASE,vector), + MAC7100_INTC_INT_LEVEL(level)); +} + +void hal_show_IRQ(int vector, int data, int handler) +{ +// UNDEFINED(__FUNCTION__); // FIXME +} + + +void hal_mac7100_reset_cpu(void) +{ + // TO DO use watchdog to reset cpu +} + +// Set ESCI channel pins in perpheral mode + +void +hal_mac7100_esci_pins(cyg_uint32 i_esci){ + cyg_uint16 *p_pim_config=0; + + switch(i_esci){ + case FREESCALE_ESCI_A_I: + p_pim_config= + (cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,2); + break; + case FREESCALE_ESCI_B_I: + p_pim_config=(cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,0); + break; + case FREESCALE_ESCI_C_I: + p_pim_config= + (cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,14); + break; + case FREESCALE_ESCI_D_I: + p_pim_config= + (cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,15); + break; + } + HAL_WRITE_UINT16(p_pim_config++, MAC7100_PIM_MODE_PERIPHERAL); + HAL_WRITE_UINT16(p_pim_config, MAC7100_PIM_MODE_PERIPHERAL); +} + + +//-------------------------------------------------------------------------- +// EOF mac7100_misc.c