--- a/packages/hal/arm/at91/at91sam7s/current/ChangeLog
+++ b/packages/hal/arm/at91/at91sam7s/current/ChangeLog
@@ -1,3 +1,11 @@
+2008-05-11  James G. Smith <jsmith@rallysmith.co.uk
+            Andrew Lunn  <andrew@lunn.ch>
+
+	* cdl/hal_arm_at91sam7s.cdl: CDL for crystal vs clock signal.
+	* include/hal_platform_setup.h: Rework flash wait states to remove
+	redundant code when running at > 60MHz. Support clock signal input
+	when starting the main clock.
+
 2008-04-30  John Eigelaar  <jeigelaar@mweb.co.za>
 
 	* include/pkgconf/mlt_arm_at91sam7x512_rom.{h|ldi}: Added the 

--- a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
+++ b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
@@ -220,10 +220,20 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
     cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN {
         display       "Main oscillator frequency"
         flavor        data
-        legal_values { 3000000 to 20000000} 
+        legal_values  { 3000000 to 20000000} 
         default_value { 18432000 }
         description   "
-            What frequency of crystal is clocking the device."
+            The frequency of the clock input, be it a crystal or a clock 
+            signal"
+    }
+
+    cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_TYPE {
+        display       "Type of main frequency input"
+        flavor        data
+        default_value { "CRYSTAL" }
+        legal_values  { "CRYSTAL" "EXTCLOCK" } 
+        description   "
+            Whether a crystal or a XIN input clock is clocking the device."
     }
 
     cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER {

--- a/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h
@@ -60,15 +60,19 @@
         .macro _flash_init
 __flash_init__:
         ldr     r0,=AT91_MC
-#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
+#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
+        // When the clock is running faster than 60MHz we need two wait states
+        ldr     r1,=(AT91_MC_FMR_2FWS)
+#else 
+# if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
         // When the clock is running faster than 30MHz we need a wait state
         ldr     r1,=(AT91_MC_FMR_1FWS)
-        str     r1,[r0,#AT91_MC_FMR]
+# else
+        // We have a slow clock, no extra wait states are needed
+        ldr     r1,=AT91_MC_FMR_0FWS
+# endif
 #endif
-#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
-        ldr     r1,=(AT91_MC_FMR_2FWS)
         str     r1,[r0,#AT91_MC_FMR]
-#endif
         .endm
 
 // Macro to start the main clock.
@@ -79,7 +83,11 @@
         ldr     r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK)
         str     r1,[r0,#AT91_PMC_MCKR]
 	// startup time
+#if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK)
+        ldr     r1,=(AT91_PMC_MOR_OSCBYPASS)
+#else
         ldr     r1,=(AT91_PMC_MOR_OSCCOUNT(6)|AT91_PMC_MOR_MOSCEN)
+#endif
         str     r1,[r0,#AT91_PMC_MOR]
 
         // Wait for oscilator start timeout