Mercurial > ecos
changeset 1769:8fd28bfdf6c1
* cdl/hal_arm_at91_jtst.cdl:
* include/plf_io.h:
* include/hal_platform_setup.h:
* include/hal_platform_ints.h:
* include/pkgconf/mlt_arm_at91_jtst_ram.ldi:
* include/pkgconf/mlt_arm_at91_jtst_ram.h:
* include/pkgconf/mlt_arm_at91_jtst_rom.ldi:
* include/pkgconf/mlt_arm_at91_jtst_rom.h:
* include/pkgconf/mlt_arm_at91_jtst_romram.ldi:
* include/pkgconf/mlt_arm_at91_jtst_romram.h:
* src/jtst_misc.c:
New HAL added to support Atmel JTST board (based on Diopsis chip).
Adapted from the EB40 and EB40A HALs by Thomas Koeller and Tim Drury.
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new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/ChangeLog @@ -0,0 +1,52 @@ +2004-06-6 Andrea Michelotti <amichelotti@atmel.com> + + * cdl/hal_arm_at91_jtst.cdl: + * include/plf_io.h: + * include/hal_platform_setup.h: + * include/hal_platform_ints.h: + * include/pkgconf/mlt_arm_at91_jtst_ram.ldi: + * include/pkgconf/mlt_arm_at91_jtst_ram.h: + * include/pkgconf/mlt_arm_at91_jtst_rom.ldi: + * include/pkgconf/mlt_arm_at91_jtst_rom.h: + * include/pkgconf/mlt_arm_at91_jtst_romram.ldi: + * include/pkgconf/mlt_arm_at91_jtst_romram.h: + * src/jtst_misc.c: + New HAL added to support Atmel JTST board (based on Diopsis chip). + Adapted from the EB40 and EB40A HALs by Thomas Koeller and Tim Drury. + + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett <nickg@calivar.com> +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/cdl/hal_arm_at91_jtst.cdl @@ -0,0 +1,296 @@ +# ==================================================================== +# +# hal_arm_at91_jtst.cdl +# +# ARM AT91 AT572D74-DK1(JTST) HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett <nickg@calivar.com> +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): amichelotti +# Contributors: gthomas, tkoeller, nickg +# Date: 2004-06-3 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_AT91_JTST { + display "Atmel AT572D740 eval board (JTST) HAL" + parent CYGPKG_HAL_ARM_AT91 + define_header hal_arm_at91_jtst.h + include_dir cyg/hal + hardware + description " + The JTST HAL package provides the support needed to run + eCos on an Atmel AT572D740-DK1 (diopsis) eval board." + + compile jtst_misc.c + + requires { CYGHWR_HAL_ARM_AT91 == "JTST" } + requires { CYGHWR_HAL_ARM_AT91_FIQ } + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_at91.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_at91_jtst.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Atmel (jtst) AT572D74-DK1\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + +cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/32) / CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the AT91 EBxx eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM" + } + + # Real-time clock/counter specifics + cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_SPEED { + display "CPU clock speed" + flavor data + default_value 50000000 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The AT91 EBxx board has two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The AT91 EBxx board has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used + to compile all packages by default. Individual packages may + define options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_at91_jtst_ram" : + "arm_at91_jtst_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? + "<pkgconf/mlt_arm_at91_jtst_ram.ldi>" : + "<pkgconf/mlt_arm_at91_jtst_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? + "<pkgconf/mlt_arm_at91_jtst_ram.h>" : + "<pkgconf/mlt_arm_at91_jtst_rom.h>" } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/hal_platform_ints.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for JTST +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): amichelotti +// Contributors: gthomas +// Date: 2001-07-12 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the JTST board/platform are +// defined here. +// +// Usage: #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// JTST MAGICHLT is the AIC FIQ that's connected to the halt signal of +// the magic DSP +#define CYGNUM_HAL_INTERRUPT_MAGICHLT 0 + +#define CYGNUM_HAL_INTERRUPT_TIMER0 1 +#define CYGNUM_HAL_INTERRUPT_TIMER1 2 +#define CYGNUM_HAL_INTERRUPT_TIMER2 3 +#define CYGNUM_HAL_INTERRUPT_USART0 4 +#define CYGNUM_HAL_INTERRUPT_USART1 5 +#define CYGNUM_HAL_INTERRUPT_SPI0 6 +#define CYGNUM_HAL_INTERRUPT_SPI1 7 +#define CYGNUM_HAL_INTERRUPT_SIRQ0 8 +#define CYGNUM_HAL_INTERRUPT_SIRQ1 9 +#define CYGNUM_HAL_INTERRUPT_SIRQ2 10 +#define CYGNUM_HAL_INTERRUPT_SIRQ3 11 +#define CYGNUM_HAL_INTERRUPT_SIRQ4 12 +#define CYGNUM_HAL_INTERRUPT_SIRQ5 13 +//exception signal from DSP +#define CYGNUM_HAL_INTERRUPT_MAGICEX 15 +#define CYGNUM_HAL_INTERRUPT_WATCHDOG 16 +#define CYGNUM_HAL_INTERRUPT_PIO 17 +#define CYGNUM_HAL_INTERRUPT_EXT4 24 +//change mode signal system/run and run/system from DSP +//I/O operation are allowed only in system mode +#define CYGNUM_HAL_INTERRUPT_MAGICMOD 25 +#define CYGNUM_HAL_INTERRUPT_EXT5 26 +// endTX from DSP dma +#define CYGNUM_HAL_INTERRUPT_ENDTXRX 27 +#define CYGNUM_HAL_INTERRUPT_EXT0 28 +#define CYGNUM_HAL_INTERRUPT_EXT1 29 +#define CYGNUM_HAL_INTERRUPT_EXT2 30 +#define CYGNUM_HAL_INTERRUPT_EXT3 31 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 31 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 + + +//---------------------------------------------------------------------------- +// Reset. +__externC void hal_at91_reset_cpu(void); +#define HAL_PLATFORM_RESET() hal_at91_reset_cpu() + +#define HAL_PLATFORM_RESET_ENTRY 0x01010000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/hal_platform_setup.h @@ -0,0 +1,156 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: amichelotti +// Date: 2004-06-4 +// Purpose: JTST platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <cyg/hal/var_io.h> +#include <cyg/hal/hal_misc.h> + + .macro __pio_clkgen_init + ldr r0,=AT91_PIO + ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3 + str r1,[r0,#AT91_PIO_SODR] // set this bit must be always 1, + // otherwise resets + ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3 + str r1,[r0,#AT91_PIO_OER] // set to output + str r1,[r0,#AT91_PIO_PER] // software control + ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27 + str r1,[r0,#AT91_PIO_CODR] // leds all on + ldr r1,=BIT30 + ldr r1,[r0,#AT91_PIO_PDR] // usb interrupt line in + // clockgen 1 is connected to timer ext clk 2 + ldr r0,=AT91_CLKGEN + ldr r1,=32 + str r1,[r0,#AT91_CLKGEN_CPTMAX0] + str r1,[r0,#AT91_CLKGEN_CPTMAX1] + ldr r1,=1 + str r1,[r0,#AT91_CLKGEN_CLKENABLE] + +#if defined(CYG_HAL_STARTUP_RAM) + // set internal ram as interrupt stack and other + ldr r0, =0x7ffc + ldr r1,=__startup_stack + ldr r2,=__startup_stack_base + sub r3,r1,r2 + ldr r1,=.__startup_stack + str r0,[r1] + sub r0,r0,r3 +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + ldr r1,=__interrupt_stack + ldr r2,=__interrupt_stack_base + sub r3,r1,r2 + ldr r1,=.__interrupt_stack + str r0,[r1] +#endif +#endif + .endm + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + + .macro _setup + ldr r10,=_InitMemory // Initialize memory controller + movs r0,pc,lsr #20 // If ROM startup, PC < 0x100000 + moveq r10,r10,lsl #12 // mask address to low 20 bits + moveq r10,r10,lsr #12 + ldmia r10!,{r0-r9,r11-r12} // Table of initialization constants +#if defined(CYG_HAL_STARTUP_ROMRAM) + ldr r10,=0x0000FFFF + and r12,r12,r10 + ldr r10,=0x00510000 + orr r12,r12,r10 +#endif + stmia r11!,{r0-r9} // Write to controller + mov pc,r12 // Change address space, break pipeline +_InitMemory: + .long 0x00502031 // FLASH + .long 0x00602021 // RAM + .long 0x00702021 // unused + .long 0x00802021 // unused + .long 0x00902021 // unused + .long 0x00A02021 // unused + .long 0x00b02021 // unused + .long 0x00c02021 // unused + .long 0x00000001 // REMAP commande + .long 0x00000006 // 7 memory regions, standard read + .long AT91_EBI // External Bus Interface address + .long 10f // address where to jump +10: + +#if defined(CYG_HAL_STARTUP_ROMRAM) + ldr r0,=0x00510000 // Relocate FLASH/ROM to on-chip RAM + ldr r1,=0x00600000 // RAM base & length + ldr r2,=0x00610000 +20: ldr r3,[r0],#4 + str r3,[r1],#4 + cmp r1,r2 + bne 20b + ldr r0,=30f + mov pc,r0 +30: + +#endif + +__pio_clkgen_init + .endm + +#define CYGSEM_HAL_ROM_RESET_USES_JUMP +#define PLATFORM_SETUP1 _setup +#else + +#define PLATFORM_SETUP1 __pio_clkgen_init + +#endif + +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h +#endif // CYGONCE_HAL_PLATFORM_SETUP_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_ram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0) +#define CYGMEM_REGION_sram_SIZE (0x8000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x606000) +#define CYGMEM_REGION_ram_SIZE (0x40000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x640000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_ram.ldi @@ -0,0 +1,53 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0, LENGTH = 0x8000 + ram : ORIGIN = 0x606000, LENGTH = 0x40000 + aicvect : ORIGIN = 0xFFF080, LENGTH = 0x00020 + magic : ORIGIN = 0x410000, LENGTH = 1024K +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA) + .internal_vectors ALIGN(0x4) : { . = . ; KEEP (*(.internal_vectors)) } > sram + SECTION_rom_vectors (ram, 0x606000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END + + . = 0x410000; + .mdata_sx ALIGN (0x8) : {*(.P0_sx)} > magic + + . = 0x411800; + .BUFFER_sx ALIGN (0x8) : {*(.BUFFER_sx)} > magic + .XM_sx ALIGN (0x8) : {*(.XM_sx*)} > magic + + . = 0x420000; + .mdata_dx ALIGN (0x8) : {*(.P0_dx)} > magic + + . = 0x411800; + .BUFFER_dx ALIGN (0x8) : {*(.BUFFER_dx)} > magic + .XM_sx ALIGN (0x8) : {*(.XM_sx*)} > magic + + . = 0x490000; + .PARM_sx ALIGN (0x8) : {*(.PARM_sx)} > magic + . = 0x4A0000; + .PARM_dx ALIGN (0x8) : {*(.PARM_dx)} > magic + + . = 0x430000; + .prog ALIGN (0x10) : {*(prog.*)} > magic +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_ram.mlt @@ -0,0 +1,14 @@ +version 0 +region sram 0 8000 0 !On-chip SRAM +region ram 500000 40000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 501000 501000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_rom.h @@ -0,0 +1,26 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x0600000) +#define CYGMEM_REGION_ram_SIZE (0x40000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x0500000) +#define CYGMEM_REGION_rom_SIZE (0x80000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_bootmon) []; +#endif +#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon)) +//#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x10000) +#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x0000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x0640000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_rom.ldi @@ -0,0 +1,55 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x00000000, LENGTH = 0x8000 + ram : ORIGIN = 0x600000, LENGTH = 0x40000 + rom : ORIGIN = 0x500000, LENGTH = 0x80000 + aicvect : ORIGIN = 0xFFF080, LENGTH = 0x00020 + magic : ORIGIN = 0x410000, LENGTH = 1024K +} + +// +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_bootmon) = 0x0500000; . = CYG_LABEL_DEFN(__reserved_bootmon); + SECTION_rom_vectors (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA) + .internal_vectors ALIGN(0x4) : { . = . ; KEEP (*(.internal_vectors)) } > sram + SECTION_data (ram, 0x0600000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END + . = 0x410000; + .data_sx ALIGN (0x8) : {*(.P0_sx)} > magic + + . = 0x411800; + .BUFFER_sx ALIGN (0x8) : {*(.BUFFER_sx)} > magic + .XM_sx ALIGN (0x8) : {*(.XM_sx*)} > magic + + . = 0x420000; + .data_dx ALIGN (0x8) : {*(.P0_dx)} > magic + + . = 0x411800; + .BUFFER_dx ALIGN (0x8) : {*(.BUFFER_dx)} > magic + .XM_sx ALIGN (0x8) : {*(.XM_sx*)} > magic + + . = 0x490000; + .PARM_sx ALIGN (0x8) : {*(.PARM_sx)} > magic + . = 0x4A0000; + .PARM_dx ALIGN (0x8) : {*(.PARM_dx)} > magic + + . = 0x430000; + .prog ALIGN (0x10) : {*(prog.*)} > magic +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/pkgconf/mlt_arm_at91_jtst_rom.mlt @@ -0,0 +1,17 @@ +version 0 +region sram 0 80000 00100000 ! +region ram 0 80000 00100000 ! +region rom 01000000 20000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 00100000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section svrsect 0 4 0 1 0 1 0 1 heap2 heap2 ! +section heap1 0 8 0 0 0 0 0 0 ! +section reserved_bootmon 10000 1 0 0 1 1 1 1 01000000 01000000 rom_vectors rom_vectors ! +section rom_vectors 0 8 0 1 0 1 0 1 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/include/plf_io.h @@ -0,0 +1,226 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// JTST board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tkoeller +// Contributors: amichelotti +// Date: 2004-06-6 +// Purpose: Atmel JTST board specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#define CYGARC_PHYSICAL_ADDRESS(_x_) + +// mapping diopsis internal resources +#define AT91_USART0 0xFFFC0000 +#define AT91_USART1 0xFFFC4000 +#define AT91_SPI0 0xFFFC8000 +#define AT91_SPI1 0xFFFCC000 + +#define AT91_PIO 0xFFFF0000 +#define AT91_AIC 0xFFFFF000 +#define AT91_TC 0xFFFEC000 +#define AT91_EBI 0xFFFE4000 +#define AT91_WD 0xFFFF8000 +#define AT91_CLKGEN 0xFFF00000 // clock divider +#define AT91_ADDA 0xFFF08000 // ADDA Analog Digital Digital Analog + +// PDC2 USART control +#define AT91_US_RPR 0x100 // Receive Pointer Register +#define AT91_US_RCR 0x104 // Receive Counter Register +#define AT91_US_TPR 0x108 // Transmit Pointer Register +#define AT91_US_TCR 0x10C // Transmit Counter Register +#define AT91_US_NRPR 0x110 // Next Receive Pointer Register +#define AT91_US_NRCR 0x114 // Next Receive Counter Register +#define AT91_US_NTPR 0x118 // Next Transmit Pointer Register +#define AT91_US_NTCR 0x11C // Next Trsnsmit Counter Register + +// PDC2 SPI control +#define AT91_SPI_RPR 0x100 // equal meaning for SPI +#define AT91_SPI_RCR 0x104 +#define AT91_SPI_TPR 0x108 +#define AT91_SPI_TCR 0x10C +#define AT91_SPI_NRPR 0x110 +#define AT91_SPI_NRCR 0x114 +#define AT91_SPI_NTPR 0x118 +#define AT91_SPI_NTCR 0x11C + + +#define AT91_PDC_PTCR 0x120 // Pdc Transfer control register +#define AT91_PDC_PTCR_TXEN 0x100 +#define AT91_PDC_PTCR_RXEN 0x1 + +#define AT91_PDC_PTCR_TXDIS 0x200 +#define AT91_PDC_PTCR_RXDIS 0x2 + + +// SPI interface +#define AT91_SPI_CR 0x0 // control register +#define AT91_SPI_CR_DIS 0x2 // disable SP +#define AT91_SPI_CR_EN 0x1 // enable SPI +#define AT91_SPI_CR_RST 0x80 // SW reset SPI +#define AT91_SPI_MR 0x4 // mode register +#define AT91_SPI_RDR 0x8 // receive data register +#define AT91_SPI_TDR 0x8 // trasmit data register +#define AT91_SPI_SR 0x10 // status register +#define AT91_SPI_IER 0x14 // interrupt register +#define AT91_SPI_IDR 0x18 // interrupt disable register +#define AT91_SPI_IMR 0x1C // interrupt mask register +#define AT91_SPI_CSR0 0x30 // chip select 0 +#define AT91_SPI_CSR1 0x34 // chip select 1 +#define AT91_SPI_CSR2 0x38 // chip select 2 +#define AT91_SPI_CSR3 0x3C // chip select 3 +// interrupts mask +#define AT91_SPI_INT_RDRF 0x1 +#define AT91_SPI_INT_TDRE 0x2 +#define AT91_SPI_INT_MODF 0x4 +#define AT91_SPI_INT_OVRE 0x8 +#define AT91_SPI_INT_ENDRX 0x10 +#define AT91_SPI_INT_ENDTX 0x20 +#define AT91_SPI_INT_RXBUFF 0x40 +#define AT91_SPI_INT_TXBUFF 0x80 + +// +#define AT91_SPI_BIT_WIDTH_8 0x0 +#define AT91_SPI_BIT_WIDTH_9 0x1 +#define AT91_SPI_BIT_WIDTH_10 0x2 +#define AT91_SPI_BIT_WIDTH_11 0x3 +#define AT91_SPI_BIT_WIDTH_12 0x4 +#define AT91_SPI_BIT_WIDTH_13 0x5 +#define AT91_SPI_BIT_WIDTH_14 0x6 +#define AT91_SPI_BIT_WIDTH_15 0x7 +#define AT91_SPI_BIT_WIDTH_16 0x8 + +#define AT91_SPI_DATA_CHANGE_HILO 0 +#define AT91_SPI_DATA_CHANGE_LOHI 1 + + +#define AT91_SPI_CLK_PHASE_HI 0 +#define AT91_SPI_CLK_PHASE_LOW 1 + + + +// CLOCK divider interface + +#define AT91_CLKGEN_CPTMAX0 0x0 //counter 0 +#define AT91_CLKGEN_CPTMAX1 0x4 //counter 1 +#define AT91_CLKGEN_CPTMAX2 0x8 //.. +#define AT91_CLKGEN_CPTMAX3 0xC +#define AT91_CLKGEN_CPTMAX4 0x10 +#define AT91_CLKGEN_CPTMAX5 0x14 +#define AT91_CLKGEN_CPTMAX6 0x18 +#define AT91_CLKGEN_CPTMAX7 0x1C +#define AT91_CLKGEN_CPTMAX8 0x20 +#define AT91_CLKGEN_CLKENABLE 0x24 // enable clocks out, wronly +#define AT91_CLKGEN_CLKDISABLE 0x28 // disable clocks out, wronly + +// ADDA Analog Digital Digital Analog interface + +#define AT91_ADDA_CR 0x0 // adda configuration +#define AT91_ADDA_ADCL0 0x20 // ADC input channel0 LEFT +#define AT91_ADDA_ADCR0 0x24 // ADC input channel0 RIGHT +#define AT91_ADDA_ADCL1 0x28 // ADC input channel1 LEFT +#define AT91_ADDA_ADCR1 0x2C // ADC input channel1 RIGHT +#define AT91_ADDA_ADCL2 0x30 // ADC input channel2 LEFT +#define AT91_ADDA_ADCR2 0x34 // ADC input channel2 RIGHT +#define AT91_ADDA_ADCL3 0x38 // ADC input channel3 LEFT +#define AT91_ADDA_ADCR3 0x3C // ADC input channel3 RIGHT + +#define AT91_ADDA_DACL0 0x20 // DAC output channel0 LEFT +#define AT91_ADDA_DACR0 0x24 // DAC output channel0 RIGHT +#define AT91_ADDA_DACL1 0x28 // DAC output channel1 LEFT +#define AT91_ADDA_DACR1 0x2C // DAC output channel1 RIGHT +#define AT91_ADDA_DACL2 0x30 // DAC output channel2 LEFT +#define AT91_ADDA_DACR2 0x34 // DAC output channel2 RIGHT +#define AT91_ADDA_DACL3 0x38 // DAC output channel3 LEFT +#define AT91_ADDA_DACR4 0x3C // DAC output channel3 RIGHT + +///// MAGIC DSP +// Magic Data Memory Left BASE 40 bit width (64 bit aligned) +#define AT91_MAARDML 0x00410000 +// Magic Data Memory Right BASE 40 bit width (64 bit aligned) +#define AT91_MAARDMR 0x00420000 +// Magic Parm Left Base (arm interchange memory) 40 bit width (64 bit aligned) +#define AT91_MAARPARML 0x00490000 +// Magic Parm Right Base (arm interchange memory) 40 bit width (64 bit aligned) +#define AT91_MAARPARMR 0x004A0000 +// Magic Program Memory +#define AT91_MAARPM 0x00430000 + +// Magic Global Controller registers +#define AT91_MAARGSR 0x00450000 +#define AT91_MAARGSR_SAR 0x0 // start magic program address +#define AT91_MAARGSR_CONF 0x4 // magic configuration +#define AT91_MAARGSR_STAT 0x8 // magic status rdonly +#define AT91_MAARGSR_EXC 0xC // magic exception rdonly +#define AT91_MAARGSR_EXC_MSK 0x10 // magic exception mask +#define AT91_MAARGSR_PC 0x14 // magic program counter +#define AT91_MAARGSR_QCS 0x18 // magic condition stack Q +#define AT91_MAARGSR_ICS 0x1C // magic condition stack I +#define AT91_MAARGSR_PMS 0x20 // magic pma stack +#define AT91_MAARGSR_DMA_TYPE 0x24 // magic dma type +#define AT91_MAARGSR_DMA_LEN 0x28 // magic dma len +#define AT91_MAARGSR_DMA_MOD 0x2C // magic modifier/stride +#define AT91_MAARGSR_DMA_BADD 0x30 // magic dma buffer address + // (internal address) +#define AT91_MAARGSR_DMA_XADD 0x34 // magic dma external address +#define AT91_MAARGSR_DMA_START 0x38 // magic start dma +#define AT91_MAARGSR_STEP_MODE 0x3C // magic single cycle mode + +// Magic MAAR (MAgic ARm interface) Controller registers base +#define AT91_MAARCSE 0x00460000 +#define AT91_MAARCSE_CMD 0x0 // command register +#define AT91_MAARCSE_CMD_RUN 0x1 // run +#define AT91_MAARCSE_SR 0x4 // status register +#define AT91_MAARCSE_EXC 0x8 // exception register +#define AT91_MAARCSE_EXC_MSK 0xC // mask exception register + +// usarts are connected to clock divider +#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud))) +#define AT91_SPI_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(4*(baud))) + +#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/misc/redboot_RAM.ecm @@ -0,0 +1,58 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware jtst ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AT91 current ; + package -hardware CYGPKG_DEVS_FLASH_JTST current ; + package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/misc/redboot_ROM.ecm @@ -0,0 +1,66 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware jtst ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AT91 current ; + package -hardware CYGPKG_DEVS_FLASH_JTST current ; + package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/at91/jtst/current/src/jtst_misc.c @@ -0,0 +1,111 @@ +//========================================================================== +// +// jtst_misc.c +// +// HAL misc board support code for Atmel JTST eval board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett <nickg@calivar.com> +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, tkoeller, nickg,amichelotti +// Date: 2004-06-6 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/hal/var_io.h> // platform registers + +// in JTST only has a 7 segments display available +void +hal_at91_led(int val){ + unsigned led=BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21; + // turn all leds off + HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR,led); + + switch(val&0xf){ + case 0: + led = BIT27|BIT26|BIT25|BIT24|BIT23|BIT21; + break; + case 1: + led = BIT26|BIT25; + break; + case 2: + led = BIT27|BIT26|BIT24|BIT23|BIT22; + break; + case 3: + led = BIT27|BIT26|BIT25|BIT24|BIT22; + break; + case 4: + led = BIT26|BIT21|BIT22|BIT25; + break; + case 5: + led = BIT27|BIT25|BIT24|BIT21|BIT22; + break; + case 6: + led = BIT27|BIT25|BIT24|BIT21|BIT22|BIT23; + break; + case 7: + led = BIT27|BIT26|BIT25; + break; + case 8: + led = BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21; + break; + case 9: + led = BIT27|BIT26|BIT25|BIT22|BIT21; + break; + default: // Show an E for out of range values + led = BIT27|BIT24|BIT23|BIT22|BIT21; + } + // leds on + HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR,led); +} + +void +hal_at91_set_leds(int val){ + hal_at91_led(val); +} + +//-------------------------------------------------------------------------- +// EOF jtst_misc.c