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changeset 2702:933a098bce82

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* include/var_intr.h: * include/var_intr.c: Corrected some interrupt priority level defines used by asserts. Changed confusing SCI0/1 naming to SCI1/2 to be consistent with actual register names. Removed some SCI related interrupt acknowledges so that the status is preserved for the DSR.
author asl
date Tue, 23 Dec 2008 18:33:04 +0000
parents 8fede7f6c559
children 3f1ca3a57e72
files packages/hal/powerpc/mpc5xx/current/ChangeLog packages/hal/powerpc/mpc5xx/current/include/var_intr.h packages/hal/powerpc/mpc5xx/current/src/var_intr.c
diffstat 3 files changed, 68 insertions(+), 94 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/powerpc/mpc5xx/current/ChangeLog
+++ b/packages/hal/powerpc/mpc5xx/current/ChangeLog
@@ -1,3 +1,14 @@
+2008-09-02  Steven Clusgton  <steven.clugston@ncl.ac.uk>
+
+    * include/var_intr.h:
+    * include/var_intr.c: 
+
+    Corrected some interrupt priority level defines used by asserts.
+    Changed confusing SCI0/1 naming to SCI1/2 to be consistent with actual 
+    register names. 
+    Removed some SCI related interrupt acknowledges so that the status 
+    is preserved for the DSR.
+
 2006-11-13  Andreas Fritiofson  <andreas.fritiofson@newmad.se>
 
     * include/var_intr.h: Fixed a set of incorrect asserts.
--- a/packages/hal/powerpc/mpc5xx/current/include/var_intr.h
+++ b/packages/hal/powerpc/mpc5xx/current/include/var_intr.h
@@ -34,9 +34,6 @@
 //
 // This exception does not invalidate any other reasons why a work based on
 // this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
 // -------------------------------------------
 //####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
@@ -186,14 +183,14 @@ hal_mpc5xx_remove_arbitration_isr(cyg_ui
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1    28  // QUADCB queue 1 pause
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2    29  // QUADCB queue 2 completion
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2    30  // QUADCB queue 2 pause
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX       31  // SCI 0 transmit
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC      32  // SCI 0 transmit complete
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX       33  // SCI 0 receiver full
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE     34  // SCI 0 idle line detected
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX       35  // SCI 1 transmit
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC      36  // SCI 1 transmit complete
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX       37  // SCI 1 receiver full
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE     38  // SCI 1 idle line detected
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX       31  // SCI 1 transmit
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC      32  // SCI 1 transmit complete
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX       33  // SCI 1 receiver full
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE     34  // SCI 1 idle line detected
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX       35  // SCI 2 transmit
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC      36  // SCI 2 transmit complete
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX       37  // SCI 2 receiver full
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE     38  // SCI 2 idle line detected
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF   39  // SCI 1 RX Queue top half full
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF   40  // SCI 1 RX Queue bottom half full
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE   41  // SCI 1 TX Queue top half full
@@ -295,11 +292,11 @@ hal_mpc5xx_remove_arbitration_isr(cyg_ui
 #define CYGNUM_HAL_ISR_MIN      CYGNUM_HAL_INTERRUPT_DECREMENTER
 #define CYGNUM_HAL_ISR_MAX      CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31
 
-#define CYGARC_SIU_PRIORITY_HIGH                 7 // Maximum interrupt priority on SIU 
-#define CYGARC_SIU_PRIORITY_LOW                  0 // Minimum interrupt priority on SIU
-#define CYGARC_IMB3_PRIORITY_HIGH               31 // Maximum interrupt priority on IMB3
-#define CYGARC_IMB3_PRIORITY_LOW                 0 // Minimum interrupt priority on IMB3
-
+// Note: highest priority has the lowest numerical value.
+#define CYGARC_SIU_PRIORITY_HIGH                 0  // Maximum interrupt priority on SIU 
+#define CYGARC_SIU_PRIORITY_LOW                  7  // Minimum interrupt priority on SIU
+#define CYGARC_IMB3_PRIORITY_HIGH                0  // Maximum interrupt priority on IMB3
+#define CYGARC_IMB3_PRIORITY_LOW                 31 // Minimum interrupt priority on IMB3
 
 //--------------------------------------------------------------------------
 // Interrupt controller access
@@ -470,7 +467,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
     {
         cyg_uint16 sccxr1;
 
@@ -480,7 +477,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
     {
         cyg_uint16 sccxr1;
 
@@ -490,7 +487,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
     {
         cyg_uint16 sccxr1;
 
@@ -500,7 +497,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
     {
         cyg_uint16 sccxr1;
 
@@ -510,7 +507,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX:
     {
         cyg_uint16 sccxr1;
 
@@ -520,7 +517,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC:
     {
         cyg_uint16 sccxr1;
 
@@ -530,7 +527,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
  
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX:
     {
         cyg_uint16 sccxr1;
 
@@ -540,7 +537,7 @@ cyg_hal_interrupt_mask ( cyg_uint32 vect
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE:
     {
         cyg_uint16 sccxr1;
 
@@ -1144,7 +1141,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
     {
         cyg_uint16 sccxr1;
 
@@ -1154,7 +1151,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
     {
         cyg_uint16 sccxr1;
 
@@ -1164,7 +1161,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
     {
         cyg_uint16 sccxr1;
 
@@ -1174,7 +1171,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
     {
         cyg_uint16 sccxr1;
 
@@ -1184,7 +1181,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX:
     {
         cyg_uint16 sccxr1;
 
@@ -1194,7 +1191,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC:
     {
         cyg_uint16 sccxr1;
 
@@ -1204,7 +1201,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
  
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX:
     {
         cyg_uint16 sccxr1;
 
@@ -1214,7 +1211,7 @@ cyg_hal_interrupt_unmask ( cyg_uint32 ve
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE:
     {
         cyg_uint16 sccxr1;
 
@@ -1819,38 +1816,20 @@ cyg_hal_interrupt_acknowledge ( cyg_uint
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
-        // Nothing needs to be done here
-        break;
-
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
-    {
-        cyg_uint16 scxsr;
-   
-        HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
-        scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
-        HAL_WRITE_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
-        break;
-    }
-
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
+    // Nothing needs to be done here
+        break;
+
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE:
         // nothing needs to be done here
         break;
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
-    {
-        cyg_uint16 scxsr;
-   
-        HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
-        scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
-        HAL_WRITE_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
-        break;
-    }
-
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
     {
         cyg_uint16 qsci1sr;
@@ -1872,24 +1851,8 @@ cyg_hal_interrupt_acknowledge ( cyg_uint
     }
 
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
-    {
-        cyg_uint16 qsci1sr;
-
-        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
-        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE);
-        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
         break;
-    }
-
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
-    {
-        cyg_uint16 qsci1sr;
-
-        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
-        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE);
-        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
-        break;
-    }
 
     case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
     {
@@ -2335,13 +2298,13 @@ cyg_hal_interrupt_set_level ( cyg_uint32
     if(vector < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1)
     {
         // Note: highest priority has the lowest numerical value.
-        CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
-        CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
+        CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
+        CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
     }
     else
     {
-        CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
-        CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
+        CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
+        CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
     }
 
     switch (vector) {
@@ -2387,7 +2350,7 @@ cyg_hal_interrupt_set_level ( cyg_uint32
         rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK);
         rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level;
         rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
-        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do wahat is asked.
+        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asked.
         HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
         break;
     }
@@ -2456,14 +2419,14 @@ cyg_hal_interrupt_set_level ( cyg_uint32
         break;
     }
 
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
-    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX:
+    case CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
     case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
@@ -2742,14 +2705,14 @@ externC cyg_uint32 hal_arbitration_isr_s
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1_PRIORITY   CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2_PRIORITY   CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2_PRIORITY   CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC_PRIORITY     CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI 
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE_PRIORITY    CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC_PRIORITY     CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
-#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE_PRIORITY    CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI 
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI 
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE_PRIORITY    CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_TXC_PRIORITY     CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX_PRIORITY      CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
+#define CYGNUM_HAL_INTERRUPT_IMB3_SCI2_IDLE_PRIORITY    CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI 
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF_PRIORITY  CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF_PRIORITY  CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI  
 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE_PRIORITY  CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI 
--- a/packages/hal/powerpc/mpc5xx/current/src/var_intr.c
+++ b/packages/hal/powerpc/mpc5xx/current/src/var_intr.c
@@ -169,7 +169,7 @@ hal_arbitration_isr_sci(CYG_ADDRWORD vec
 	HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scc_sr);
 	HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, scc_cr);
 	if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
-	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
+	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
         if (isr_ret & CYG_ISR_HANDLED)
 #endif
@@ -179,7 +179,7 @@ hal_arbitration_isr_sci(CYG_ADDRWORD vec
 	HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scc_sr);
 	HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, scc_cr);
 	if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
-	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
+	    isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX);
 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
         if (isr_ret & CYG_ISR_HANDLED)
 #endif
@@ -386,8 +386,8 @@ hal_variant_IRQ_init(void)
   sci_arbiter.arbiter = hal_arbitration_isr_sci;
 
   hal_mpc5xx_install_arbitration_isr(&sci_arbiter);
-  HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);	
-  HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);	
+  HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);	
+  HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);	
 #endif
 }