--- a/packages/devs/spi/arm/lpc2xxx/current/ChangeLog
+++ b/packages/devs/spi/arm/lpc2xxx/current/ChangeLog
@@ -1,3 +1,12 @@
+2009-02-17  Jonathan Larmour  <jifl@eCosCentric.com>
+2009-01-27  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/spi_lpc2xxx.cdl: Ensure the SPI interrupts are using different
+	priorities: CYGNUM_IO_SPI_ARM_LPC2XXX_SPI{0,1}_INTPRIO entered.
+	* include/spi_lpc2xxx.h: cyg_spi_lpc2xxx_bus_t: spi_prio field added.
+	* src/spi_lpc2xxx.cxx: spi_lpc2xxx_set_config(): fixed copy & paste
+	typo, spi_lpc2xxx_init_bus(): added 'prio' argument to initializer.
+
 2009-02-10  Bart Veer  <bartv@ecoscentric.com>
 
 	* src/spi_lpc2xxx.cxx: update init priority.

--- a/packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl
+++ b/packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl
@@ -57,19 +57,47 @@ cdl_package CYGPKG_DEVS_SPI_ARM_LPC2XXX 
     include_dir cyg/io
     compile     spi_lpc2xxx.cxx
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
         display       "Enable SPI interface 0"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
-                       Enable this option to get support for SPI interface 0."
+                       Enable this component to get support for SPI
+                       interface 0."
+
+        cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_BUS0_INTPRIO {
+            display       "Interrupt priority of the SPI bus 0 ISR"
+            flavor        data
+            legal_values  0 to 15
+            default_value 12
+            requires      { is_active(CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
+                             implies (CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO !=
+                             CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
+            }
+            description "
+                This option specifies the interrupt priority of the ISR of
+                the SPI bus 0 interrupt in the VIC. Slot 0 has the highest
+                priority and slot 15 the lowest."
+        }
     }
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
         display       "Enable SPI interface 1"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
-                       Enable this option to get support for SPI interface 1."
+                       Enable this component to get support for SPI
+                       interface 1."
+
+        cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO {
+            display       "Interrupt priority of the SPI bus 1 ISR"
+            flavor        data
+            legal_values  0 to 15
+            default_value 13
+            description "
+                This option specifies the interrupt priority of the ISR of
+                the SPI bus 1 interrupt in the VIC. Slot 0 has the highest
+                priority and slot 15 the lowest."
+        }
     }
 }

--- a/packages/devs/spi/arm/lpc2xxx/current/include/spi_lpc2xxx.h
+++ b/packages/devs/spi/arm/lpc2xxx/current/include/spi_lpc2xxx.h
@@ -75,6 +75,7 @@ typedef struct {
   cyg_interrupt   spi_intr;
   cyg_handle_t    spi_hand;
   cyg_vector_t    spi_vect;
+  cyg_priority_t  spi_prio;
   cyg_drv_mutex_t spi_lock;
   cyg_drv_cond_t  spi_wait;
   

--- a/packages/devs/spi/arm/lpc2xxx/current/src/spi_lpc2xxx.cxx
+++ b/packages/devs/spi/arm/lpc2xxx/current/src/spi_lpc2xxx.cxx
@@ -180,7 +180,7 @@ spi_lpc2xxx_set_config(cyg_spi_device *d
   cyg_spi_lpc2xxx_dev_t *dev = (cyg_spi_lpc2xxx_dev_t *) device;
   
   switch(key) {
-    case CYG_IO_GET_CONFIG_SPI_CLOCKRATE:
+    case CYG_IO_SET_CONFIG_SPI_CLOCKRATE:
       if(*len == sizeof(cyg_uint32)) {
         dev->spi_baud = * (cyg_uint32 *) buf;
         spi_lpc2xxx_baud((cyg_spi_lpc2xxx_bus_t *) dev->spi_device.spi_bus, 
@@ -304,7 +304,8 @@ spi_lpc2xxx_end(cyg_spi_device *device)
 static void 
 spi_lpc2xxx_init_bus(cyg_spi_lpc2xxx_bus_t *bus, 
                      cyg_addrword_t dev,
-                     cyg_vector_t vec)
+                     cyg_vector_t vec,
+                     cyg_priority_t prio)
 {
   bus->spi_bus.spi_transaction_begin    = spi_lpc2xxx_begin;
   bus->spi_bus.spi_transaction_transfer = spi_lpc2xxx_transfer;
@@ -319,8 +320,9 @@ spi_lpc2xxx_init_bus(cyg_spi_lpc2xxx_bus
   
   bus->spi_dev = (struct spi_dev *) dev;
   bus->spi_vect = vec;
+  bus->spi_prio = prio;
   cyg_drv_interrupt_create(
-                           vec, 0, (cyg_addrword_t) bus,
+                           vec, prio, (cyg_addrword_t) bus,
                            &spi_lpc2xxx_isr, &spi_lpc2xxx_dsr,
                            &bus->spi_hand, &bus->spi_intr);
   cyg_drv_interrupt_attach(bus->spi_hand);
@@ -343,7 +345,8 @@ public:
     
     spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus0,
                          CYGARC_HAL_LPC2XXX_REG_SPI0_BASE,
-                         CYGNUM_HAL_INTERRUPT_SPI0);
+                         CYGNUM_HAL_INTERRUPT_SPI0,
+                         CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO);
 #endif
 #ifdef CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1
     addr = (CYGARC_HAL_LPC2XXX_REG_PIN_BASE
@@ -353,7 +356,8 @@ public:
     HAL_WRITE_UINT32(addr, tmp);
     spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus1,
                          CYGARC_HAL_LPC2XXX_REG_SPI1_BASE,
-                         CYGNUM_HAL_INTERRUPT_SPI1);
+                         CYGNUM_HAL_INTERRUPT_SPI1,
+                         CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO);
 #endif
   }
 };