Mercurial > ecos
changeset 2499:a4719c33db09
* Initial release of Embedded Artists LPC2468 OEM board package
* cdl/hal_arm_lpc2xxx_ea2468.cdl
* include/plf_io.h
* include/hal_platform_setup.h
* src/ea2468_misc
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new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/ChangeLog @@ -0,0 +1,41 @@ +2008-07-06 Uwe Kindler <uwe_kindler@web.de> + + * Initial release of Embedded Artists LPC2468 OEM board package + * cdl/hal_arm_lpc2xxx_ea2468.cdl + * include/plf_io.h + * include/hal_platform_setup.h + * src/ea2468_misc + +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/cdl/hal_arm_lpc24xx_ea2468.cdl @@ -0,0 +1,316 @@ +# ==================================================================== +# +# hal_arm_lpc24xx_ea2468.cdl +# +# Embedded Artists LPC2468 OEM Board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2008 eCosCentric Limited +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Uwe Kindler +# Contributors: Uwe Kindler +# Date: 2008-07-06 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_LPC24XX_EA2468 { + display "Embedded Artists LPC2468 OEM Board board HAL" + parent CYGPKG_HAL_ARM_LPC24XX + define_header hal_arm_lpc24xx_ea2468.h + include_dir cyg/hal + hardware + implements CYGINT_DEVS_CAN_LPC2XXX_CAN0 + implements CYGINT_DEVS_CAN_LPC2XXX_CAN1 + implements CYGINT_IO_SERIAL_LPC24XX_UART0 + implements CYGINT_IO_SERIAL_LPC24XX_UART1 + description " + The LPC2468 OEM HAL package provides the support needed to run + eCos on Embedded Artists LPC2468 OEM 16/32 boards." + + compile ea2468_misc.c + + requires { CYGHWR_HAL_ARM_LPC24XX == "LPC2468" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_lpc24xx.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_lpc24xx_ea2468.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI-S\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Embedded Artists LPC2468 OEM Board\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_option CYGNUM_HAL_ARM_LPC24XX_XTAL_FREQ { + display "CPU xtal frequency" + parent CYGNUM_HAL_ARM_LPC24XX_CLOCKING + flavor data + default_value {12000000} + } + + cdl_option CYGNUM_HAL_ARM_LPC24XX_MAX_CLOCK_SPEED { + display "Max. CPU clock speed" + parent CYGNUM_HAL_ARM_LPC24XX_CLOCKING + flavor data + calculated {57600000} + requires CYGNUM_HAL_ARM_LPC24XX_CLOCK_SPEED <= 57600000 + description " + Due to a silicon errata, the highest internal core + clock frequency (at the time of writing this document) + is 57.6 MHz. This corresponds to an internal PLL + frequency of 288 MHz that is divided by 6 to get a 48 + MHz clock for the core and the USB interface." + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"ROM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + Choose RAM or ROM startup type. Typically ROM startup is used for + building RedBoot. RedBoot runs from internal on chip flash of + LPC24xx. Use RAM startup for building eCos applications. + RedBoot manages the external on board flash devices. It copies + the eCos application image from FLASH to on board SDRAM + and then starts the eCos application." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + description " + Channel 0: UART0, Channel 1: UART1" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The LPC2468 OEM board has two serial channels. The first + channel, UART0, ist routed to an USB-to-serial bridge and + the second channel, UART1, is available on the Sub-D9 + RS232 connector. This option chooses which channel will be + used to connect to a host running GDB." } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the baud rate used for the GDB + connection." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The LPC2468 OEM board has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH { + display "Data bus width" + flavor data + default_value { 16 } + legal_values { 16 32 } + description " + The LPC2468 OEM board is sold in two different data bus + versions - a 16-bit version and a 32-bit version." + } + + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over compiler flags, + linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by default. Individual + packages may define options which override these global + flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global + flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM"} + description " + Enable this option if this program is to be used as a + ROM monitor, i.e. applications will be loaded into RAM on + the board, and this ROM monitor may process exceptions or + interrupts generated from the application. This enables + features such as utilizing a separate interrupt stack when + exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM + monitor. This support changes various eCos semantics such + as the encoding of diagnostic output, or the overriding of + hardware interrupt vectors. + Firstly there is \"Generic\" support which prevents the + HAL from overriding the hardware vectors that it does not + use, to instead allow an installed ROM monitor to handle + them. This is the most basic support which is likely to be + common to most implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included + in the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid + Redboot configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + requires { !CYGBLD_BUILD_REDBOOT_WITH_EXEC } + default_value 1 + no_define + description " + This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O ihex $< $(@:.bin=.hex) + $(OBJCOPY) -O binary $< $@ + } + + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_lpc24xx_ea2468_ram" : + "arm_lpc24xx_ea2468_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? + "<pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi>" : + "<pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? + "<pkgconf/mlt_arm_lpc24xx_ea2468_ram.h>" : + "<pkgconf/mlt_arm_lpc24xx_ea2468_rom.h>" } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/hal_platform_setup.h @@ -0,0 +1,122 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2008 eCosCentric Limited +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler +// Contributors: Uwe Kindler +// Date: 2008-06-05 +// Purpose: EA LPC2468 OEM platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ +#include <pkgconf/system.h> +#include <cyg/hal/var_io.h> + + +// +// The minimum initialisation code - we simply setup a valid C stack in +// internal SRAM and do any further initialisation in C code +// +#if defined(CYG_HAL_STARTUP_ROM) +.macro _setup + // + // While setting the stack pointer please note that the + // Flash programming routines use a + // section of the on-chip SRAM. In-System Programming (ISP) uses + // the top 256 bytes and In-Application Programming (IAP) uses the + // top 128 bytes of the on-chip SRAM. The application stack should + // not overlap this area. + // + ldr r2,=0x4000ffff // ram end + sub sp,r2,#0xff + + // + // now map the vector table to internal flash - normally this should be + // the default value after boot - but we go the save way here and force + // the mapping to internal flash (the value for + // CYGARC_HAL_LPC24XX_REG_MEMMAP is 1) + // + ldr r0,=CYGARC_HAL_LPC24XX_REG_SCB_BASE + mov r1,#1 + str r1, [r0,#CYGARC_HAL_LPC24XX_REG_MEMMAP] + + // + // Now its is save to copy the first 64 bytes of flash to RAM + // + mov r0,#0 + mov r1,#0x40000000 + mov r2,#0x40 +1: + ldr r3,[r0,#4]! + str r3,[r1,#4]! + cmps r0,r2 + bne 1b + + // + // Now we can map the vector table to internal SRAM because the SRAM no + // contains a copy of the vector table from flash (the value for + // CYGARC_HAL_LPC24XX_REG_MEMMAP is 2 = SRAM) + // + ldr r0,=CYGARC_HAL_LPC24XX_REG_SCB_BASE + mov r1,#2 // User RAM Mode. Interrupt + // vectors are re-mapped to Static RAM. + str r1, [r0,#CYGARC_HAL_LPC24XX_REG_MEMMAP] + + // + // now we have a valid stack and we can jump into the beautiful + // world of C and do any further initialisation in C code + // + bl hal_plf_startup +.endm +#define CYGSEM_HAL_ROM_RESET_USES_JUMP +#else +.macro _setup +.endm +#endif + +#define PLATFORM_SETUP1 _setup + +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h +#endif // CYGONCE_HAL_PLATFORM_SETUP_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.h @@ -0,0 +1,21 @@ +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif + +#define CYGMEM_REGION_sram (0x40000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0xA0000000) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif + +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0xA2000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi @@ -0,0 +1,26 @@ +#include <cyg/infra/cyg_type.inc> +#include <pkgconf/hal_arm_lpc24xx_ea2468.h> + +MEMORY +{ + sram : ORIGIN = 0x40000000, LENGTH = 0x10000 + ram : ORIGIN = 0xA0000000, LENGTH = 0x2000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0xA0010000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.h @@ -0,0 +1,28 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x40000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0xA0000000) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_rom (0x00000000) +#define CYGMEM_REGION_rom_SIZE (0x00080000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) + + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0xA2000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi @@ -0,0 +1,27 @@ +#include <cyg/infra/cyg_type.inc> +#include <pkgconf/hal_arm_lpc24xx_ea2468.h> + +MEMORY +{ + rom : ORIGIN = 0x00000000, LENGTH = 0x80000 + sram : ORIGIN = 0x40000000, LENGTH = 0x10000 + ram : ORIGIN = 0xA0000000, LENGTH = 0x2000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x00000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA) + SECTION_data (ram, 0xA0000000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/include/plf_io.h @@ -0,0 +1,68 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Embedded Artists LPC2468 OEM board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2008 eCosCentric Limited +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler +// Contributors: +// Date: 2008-07-06 +// Purpose: EA LPC2468 oem board specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= +// On-chip device base addresses + + +//---------------------------------------------------------------------- +// The platform needs this initialization during the +// hal_hardware_init() function in the varient HAL. +#ifndef __ASSEMBLER__ +extern void hal_plf_hardware_init(void); +#define HAL_PLF_HARDWARE_INIT() \ + hal_plf_hardware_init() +#endif //__ASSEMBLER__ + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/lpc24xx/ea2468/current/src/ea2468_misc.c @@ -0,0 +1,432 @@ +/*========================================================================== +// +// ea2468_misc.c +// +// HAL misc board support code for EA LPC2468 OEM board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2008 eCosCentric Limited +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler +// Contributors: Uwe Kindler +// Date: 2008-06-15 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + + +//=========================================================================== +// INCLUDES +//=========================================================================== +#include <pkgconf/hal.h> +#include <pkgconf/hal_arm_lpc24xx_ea2468.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_io.h> // IO macros + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/hal/var_io.h> +#include <cyg/hal/plf_io.h> +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#endif + + +//=========================================================================== +// DEFINES +//=========================================================================== +#define SCB_BASE CYGARC_HAL_LPC24XX_REG_SCB_BASE +#define EMC_BASE CYGARC_HAL_LPC24XX_REG_EMC_BASE +#define PIN_BASE CYGARC_HAL_LPC24XX_REG_PIN_BASE +#define IO_BASE CYGARC_HAL_LPC24XX_REG_IO_BASE +#define FIO_BASE CYGARC_HAL_LPC24XX_REG_FIO_BASE +#define SDRAM_BASE 0xA0000000 + +extern void cyg_hal_plf_serial_init(void); + + +//=========================================================================== +// Initialize communication channels +//=========================================================================== +void cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + + cyg_hal_plf_serial_init(); +} + + +//=========================================================================== +// Finalize hardware initialisation of platform +//=========================================================================== +void hal_plf_hardware_init(void) +{ + +} + + +//=========================================================================== +// hal_gpio_init +//=========================================================================== +void hal_gpio_init(void) +{ + // + // Enable UART0 pins + // + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0); + + HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0); + HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0); + HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff); + HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff); + + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0); + + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff); + HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff); +} + + +//=========================================================================== +// hal_pll_init - initialize pll and all clocks +//=========================================================================== +void hal_pll_init(void) +{ + cyg_uint32 regval; + + HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval); + if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC) + { + // + // Enable PLL, disconnected + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, + CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55); + } + + // + // Disable PLL, disconnected + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, 0x00); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55); + + // + // Enables main oscillator and wait until it is usable + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, + CYGARC_HAL_LPC24XX_REG_SCS_OSCEN); + do + { + HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval); + } while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT)); + + // + // select main OSC, 12MHz, as the PLL clock source + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL, + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN); + + // + // Configure PLL multiplier and pre divider according to + // configuration values + // + regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) | + (CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG, regval); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55); + + // + // Enable PLL, disconnected + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, + CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55); + + // + // Set CPU clock divider + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG, + CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1); + + // + // Set USB clock divider + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG, + CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1); + + // + // Check lock bit status + // + do + { + HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval); + } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK)); + + // + // Enable PLL and connect + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, + CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE | + CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55); + + // + // Check connect bit status + // + do + { + HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval); + } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)); + + // + // entry for JTAG debugger- enable this while loop as a stop for + // the JTAG debugger - the JTAG debugger only works after the PLL is + // initialized properly + // + /*while (1) + { + }*/ +} + + +//=========================================================================== +// hal_mem_init - initalize external memory interface +//=========================================================================== +void hal_mem_init(void) +{ + volatile unsigned int i; + volatile unsigned int dummy; + volatile cyg_uint32 regval; + + // + // Enable external memory interface + // + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL, + CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN); + HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, regval); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, + regval | CYGARC_HAL_LPC24XX_REG_PCONP_EMC); + + // + // Setup pin functions + // + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000); +#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32) + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555); +#else + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555); +#endif + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555); + HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555); + +#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32) + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0, + 0x00000202); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, + 0x00005480); +#else + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 7); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 7); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0, + 0x00000303); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, + 0x00000680); +#endif + + // + // Wait 100 ms and then send command: NOP + // + HAL_DELAY_US(100000); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL, + 0x00000183); + + // + // wait 200 ms and then send command: PRECHARGE-ALL, shortest + // possible refresh period + // + HAL_DELAY_US(200000); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL, + 0x00000103); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, + 0x00000002); + + // + // wait 128 ABH clock cycles + // + for(i = 0; i < 64; i++) + { + asm volatile(" nop"); + } + + // + // Set correct refresh period and the send command MODE + // + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL, + 0x00000083); + + // + // Set mode register in SDRAM + // +#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32) + dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x22 << 11))); +#else + dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x33 << 12))); +#endif + + // + //Send command: NORMAL, enable buffer and wait for 1 second + // + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL, + 0x00000000); + HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, + regval | 0x00080000); + HAL_DELAY_US(1000); + + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0, 0x1f); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0, 0x1f); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0, + 0x00000081); + + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1, 0x8); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1, 0x8); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf); + HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1, + 0x00000080); +} + + +//=========================================================================== +// hal_plf_startup +//=========================================================================== +void hal_plf_startup(void) +{ + hal_pll_init(); + + // + // Set clock speed of all peripherals to reset value (CPU speed / 4) + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000); + + // + // Setup memory acceleration module + // + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0); + HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4); + + hal_gpio_init(); + HAL_DELAY_US(20000); + hal_mem_init(); +} + + +//=========================================================================== +// hal_lpc2xxx_set_leds +//=========================================================================== +void hal_lpc24xx_set_leds (int mask) +{ + // + // implement function for setting diagnostic leds + // +} + +//-------------------------------------------------------------------------- +// EOF ea2468_misc.c