Mercurial > ecos
changeset 537:b0e7b1f888d6
pxa2x0/mpc50 port from Knud Woehler
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,8 @@ +2003-01-24 Knud Woehler <knud.woehler@microplex.de> +2003-01-24 Mark Salter <msalter@redhat.com> + + * ecos.db: Add packages for XScale PXA2x0/MPC50. + 2003-01-24 John Dallaway <jld@ecoscentric.com> * ecosadmin.tcl: Accommodate latest Cygwin Tcl shell (tclsh83.exe)
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/mpc50/current/ChangeLog @@ -0,0 +1,39 @@ +2003-01-24 Knud Woehler <knud.woehler@microplex.de> +2003-01-24 Mark Salter <msalter@redhat.com> + + * Initial import from Knud Woehler. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/mpc50/current/cdl/flash_mpc50.cdl @@ -0,0 +1,71 @@ +# ==================================================================== +# +# flash_mpc50.cdl +# +# MPC 5.0 flash package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with eCos; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +# +# As a special exception, if other files instantiate templates or use macros +# or inline functions from this file, or you compile this file and link it +# with other works to produce a work based on this file, this file does not +# by itself cause the resulting work to be covered by the GNU General Public +# License. However the source code for this file must still be made available +# in accordance with section (3) of the GNU General Public License. +# +# This exception does not invalidate any other reasons why a work based on +# this file might be covered by the GNU General Public License. +# +# Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +# at http://sources.redhat.com/ecos/ecos-license +# ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): woehler +# Date: 2002-09-02 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_MPC50 { + display "MPC 5.0 FLASH memory support" + description "FLASH memory device support for MPC 5.0" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_XSCALE_MPC50 + requires CYGPKG_DEVS_FLASH_STRATA + + include_dir cyg/io + + cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED { + display "Generic StrataFLASH driver required" + } + + implements CYGINT_DEVS_FLASH_STRATA_REQUIRED + + define_proc { + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL <cyg/io/mpc50_strataflash.inl>" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG <pkgconf/devs_flash_mpc50.h>" + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/mpc50/current/include/mpc50_strataflash.inl @@ -0,0 +1,63 @@ +#ifndef CYGONCE_DEVS_FLASH_MPC50_STRATAFLASH_INL +#define CYGONCE_DEVS_FLASH_MPC50_STRATAFLASH_INL +//========================================================================== +// +// mpc50_strataflash.inl +// +// Flash programming - device constants, etc. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): woehler +// Date: 2002-09-02 +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// There is a single 16-bit device, on the MPC 5.0 +// a StrataFlash RC28F128J3A. -> 128Mb Chip + +#define CYGNUM_FLASH_DEVICES (1) +#define CYGNUM_FLASH_BASE (0x50000000u) +#define CYGNUM_FLASH_BASE_MASK (0xFC000000u) +#define CYGNUM_FLASH_WIDTH (16) +#define CYGNUM_FLASH_BLANK (1) + +#endif // CYGONCE_DEVS_FLASH_MPC50_STRATAFLASH_INL +// ------------------------------------------------------------------------ +// EOF mpc50_strataflash.inl
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -362,6 +362,15 @@ package CYGPKG_DEVS_FLASH_FLEXANET { on the SA-1100 Flexanet platform." } +package CYGPKG_DEVS_FLASH_MPC50 { + alias { "FLASH memory support for MPC 5.0" flash_mpc50 } + directory devs/flash/arm/mpc50 + script flash_mpc50.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the MPC 5.0." +} package CYGPKG_DEVS_FLASH_MALTA { alias { "FLASH memory support for MIPS Malta board" flash_malta } @@ -2169,6 +2178,26 @@ package CYGPKG_HAL_ARM_XSCALE_IQ80321 { eCos on an Intel XScale IQ80321 evaluation board." } +package CYGPKG_HAL_ARM_XSCALE_PXA2X0 { + alias { "Intel PXA2X0" hal_arm_xscale_pxa2x0 } + directory hal/arm/xscale/pxa2x0 + script hal_arm_xscale_pxa2x0.cdl + hardware + description " + The PXA2X0 HAL package provides the support needed to run + eCos on Intel PXA2X0 based systems." +} + +package CYGPKG_HAL_ARM_XSCALE_MPC50 { + alias { "MICROPLEX Printer Controller 5.0" hal_arm_xscale_mpc50 } + directory hal/arm/xscale/mpc50 + script hal_arm_xscale_mpc50.cdl + hardware + description " + The MPC50 HAL package provides the support needed to run + eCos on a MPC 5.0." +} + # -------------------------------------------------------------------------- # SH packages package CYGPKG_HAL_SH { @@ -3522,6 +3551,21 @@ target snds { The snds target provides the packages needed to run eCos on a Samsung SNDS eval board." } + +target mpc50 { + alias { "MICROPLEX Printer Controller 5.0" mpc50 } + packages { + CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_XSCALE_CORE + CYGPKG_HAL_ARM_XSCALE_PXA2X0 + CYGPKG_HAL_ARM_XSCALE_MPC50 + CYGPKG_DEVS_FLASH_STRATA + CYGPKG_DEVS_FLASH_MPC50 + } + description " + MICROPLEX Printer Controller 5.0" +} + # -------------------------------------------------------------------------- # SH targets
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/ChangeLog @@ -0,0 +1,39 @@ +2003-01-24 Knud Woehler <knud.woehler@microplex.de> +2003-01-24 Mark Salter <msalter@redhat.com> + + * Initial import from Knud Woehler. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/cdl/hal_arm_xscale_mpc50.cdl @@ -0,0 +1,273 @@ +# ==================================================================== +# +# hal_arm_xscale_mpc50.cdl +# +# MPC 5.0 platform HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with eCos; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +# +# As a special exception, if other files instantiate templates or use macros +# or inline functions from this file, or you compile this file and link it +# with other works to produce a work based on this file, this file does not +# by itself cause the resulting work to be covered by the GNU General Public +# License. However the source code for this file must still be made available +# in accordance with section (3) of the GNU General Public License. +# +# This exception does not invalidate any other reasons why a work based on +# this file might be covered by the GNU General Public License. +# +# Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +# at http://sources.redhat.com/ecos/ecos-license +# ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): <knud.woehler@microplex.de> +# Date: 2003-01-06 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_XSCALE_MPC50 { + display "MPC 5.0" + parent CYGPKG_HAL_ARM_PXA2X0 + hardware + include_dir cyg/hal + define_header hal_arm_xscale_mpc50.h + description " + This HAL platform package provides support for the MPC 5.0 + printer controller" + compile mpc50_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_ARM_ARCH_XSCALE + implements CYGINT_HAL_ARM_MEM_REAL_REGION_TOP + implements CYGHWR_HAL_ARM_PXA2X0_FFUART + + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_xscale_pxa2x0.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_xscale_mpc50.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MPC 5.0\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK mpc50_program_new_stack" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"ROM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description "" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Console channel." + flavor data + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + calculated CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option selects the baud rate used for the GDB port." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "xscale-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -mapcs-frame" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_component CYGPKG_HAL_ARM_PXA2X0_MPC50_OPTIONS { + display "Intel PXA250/MPC50 build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_PXA2X0_MPC50_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description "" + } + + cdl_option CYGPKG_HAL_ARM_PXA2X0_MPC50_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description "" + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_pxa2x0_mpc50_ram" : \ + "arm_pxa2x0_mpc50_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_pxa2x0_mpc50_ram.ldi>" : \ + "<pkgconf/mlt_arm_pxa2x0_mpc50_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_pxa2x0_mpc50_ram.h>" : \ + "<pkgconf/mlt_arm_pxa2x0_mpc50_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description "" + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description "" + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + compile -library=libextras.a + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + } +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/hal_platform_setup.h @@ -0,0 +1,584 @@ +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2003-01-09 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_pxa2x0.h> // Platform specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/hal_mm.h> // more MMU definitions +#include <cyg/hal/mpc50.h> + +/********************************************************************************************************************** +* MMU/Cache +**********************************************************************************************************************/ +.macro init_mmu_cache_on + ldr r0, =0x2001 + mcr p15, 0, r0, c15, c1, 0 + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB + CPWAIT r0 + mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs + CPWAIT r0 + + // Icache on + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + orr r0, r0, #MMU_Control_BTB // Enable the BTB + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // create stack for "C" + ldr r1,=__startup_stack + ldr r2,=PXA2X0_RAM_BANK0_BASE + orr sp,r1,r2 + bl hal_mmu_init // create MMU Tables + + // Enable permission checks in all domains + ldr r0, =0x55555555 + mcr p15, 0, r0, c3, c0, 0 + + // MMU on + ldr r2,=1f + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_M + orr r0, r0, #MMU_Control_R + mcr p15, 0, r0, c1, c0, 0 + mov pc,r2 + nop + nop + nop +1: + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // Dcache on + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_C + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // clean/drain/flush the main Dcache + mov r1, #0xc0000000 + mov r0, #1024 +2: + mcr p15, 0, r1, c7, c2, 5 + add r1, r1, #32 + subs r0, r0, #1 + bne 2b + + // clean/drain/flush the mini Dcache + //ldr r1, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of + mov r0, #64 // number of lines in the mini Dcache +3: + mcr p15, 0, r1, c7, c2, 5 // allocate a Dcache line + add r1, r1, #32 // increment the address to + subs r0, r0, #1 // decrement the loop count + bne 3b + + // flush Dcache + mcr p15, 0, r0, c7, c6, 0 + CPWAIT r0 + + // drain the write & fill buffers + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + +.endm + + + +.macro init_mmu_off + mov r0, #0x78 + mcr p15, 0, r0, c1, c0, 0 // caches off -- MMU off or ID map + mcr p15, 0, r0, c7, c7, 0 // Invalidate the I & D cache, mini- d cache, and BTB + mcr p15, 0, r0, c7, c10, 4 // Drain write buffer -- r0 ignored + CPWAIT r0 + nop + nop + nop + nop + mvn r0, #0 + mcr p15, 0, r0, c3, c0, 0 +.endm + +/********************************************************************************************************************** +* Clock +**********************************************************************************************************************/ +#define CCCR_OFFS (PXA2X0_CCCR-PXA2X0_CLK_BASE) +.macro init_clks + ldr r1, =PXA2X0_CLK_BASE + // TurboMode=400MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz +// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N20) + // TurboMode=300MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz +// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N15) + adr r0, mpc50_static_info + ldr r0, [r0, #MPC50_VAL_OFFS_CCCR] + + str r0, [r1, #CCCR_OFFS] // set Core Clock + mov r0, #3 + mcr p14, 0, r0, c6, c0, 0 // Turbo Mode on +.endm + +/********************************************************************************************************************** +* Interrupt controller +**********************************************************************************************************************/ +#define ICLR_OFFS (PXA2X0_ICLR-PXA2X0_IC_BASE) +#define ICMR_OFFS (PXA2X0_ICMR-PXA2X0_IC_BASE) +.macro init_intc_cnt + ldr r1, =PXA2X0_IC_BASE + mov r0, #0 + str r0, [r1, #ICLR_OFFS] // clear Interrupt level Register + str r0, [r1, #ICMR_OFFS] // clear Interrupt mask Register +.endm + +/********************************************************************************************************************** +* SDRAM +**********************************************************************************************************************/ + +//#define MDCNFG_VAL 0x094B094B // SDRAM Config Reg (32Bit, 9 Col, 13 Row, 2 Bank, CL2) +//#define MDREFR_VAL 0x0005b018 // SDRAM Refresh Reg SDCLK=memory clock +//#define MDREFR_VAL 0x000ff018 // SDRAM Refresh Reg SDCLK=1/2 memory clock +#define MDMRS_VAL 0x00000000 // SDRAM Mode Reg Set Config Reg +#define MSC0_VAL 0x199123da // CS1(FPGA)/CS0(Flash) +#define MSC1_VAL 0x7ff07ff1 // CS3(not used)/CS2(ETH) + +#define OSCR_OFFS (PXA2X0_OSCR-PXA2X0_OSTIMER_BASE) +#define MDREFR_OFFS (PXA2X0_MDREFR-PXA2X0_MEMORY_CTL_BASE) +#define MDCNFG_OFFS (PXA2X0_MDCNFG-PXA2X0_MEMORY_CTL_BASE) +#define MDMRS_OFFS (PXA2X0_MDMRS-PXA2X0_MEMORY_CTL_BASE) +#define MSC0_OFFS (PXA2X0_MSC0-PXA2X0_MEMORY_CTL_BASE) +#define MSC1_OFFS (PXA2X0_MSC1-PXA2X0_MEMORY_CTL_BASE) +#define MSC2_OFFS (PXA2X0_MSC2-PXA2X0_MEMORY_CTL_BASE) +.macro init_sdram_cnt +// Hardware Reset Operation (S. 5-83) +// Step 1 + +// wait 200 usec + ldr r1, =PXA2X0_OSTIMER_BASE // set OS Timer Count + mov r0, #0 + str r0, [r1, #OSCR_OFFS] + ldr r2, =0x300 // wait 200 usec +61: + ldr r0, [r1, #OSCR_OFFS] + cmp r2, r0 + bgt 61b + + ldr r1, =PXA2X0_MEMORY_CTL_BASE + + ldr r0, =MSC0_VAL + str r0, [r1, #MSC0_OFFS] // FPGA/Flash + + ldr r0, =MSC1_VAL + str r0, [r1, #MSC1_OFFS] // ETH + + // Refresh Register + //ldr r3, =MDREFR_VAL // load SDRAM refresh info + adr r3, mpc50_static_info + ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR] + + + ldr r2, =0xFFF // DRI field + and r3, r3, r2 + ldr r4, [r1, #MDREFR_OFFS] // read Reset Status + bic r4, r4, r2 + bic r4, r4, #(0x01000000 | 0x02000000) // clear K1Free, K2Free, + bic r4, r4, #0x00004000 // K0DB2 + orr r4, r4, r3 // add DRI field + str r4, [r1, #MDREFR_OFFS] // + ldr r4, [r1, #MDREFR_OFFS] + +// Step 2 +// + +// Step 3 + //ldr r3, =MDREFR_VAL // load SDRAM Refresh Info + adr r3, mpc50_static_info + ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR] + + + ldr r2, =0x000f0000 + and r3, r3, r2 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFS] + ldr r4, [r1, #MDREFR_OFFS] + + bic r4, r4, #0x00400000 // Self Refresh off + str r4, [r1, #MDREFR_OFFS] + ldr r4, [r1, #MDREFR_OFFS] + + orr r4, r4, #0x00008000 // SDCKE1 on + str r4, [r1, #MDREFR_OFFS] + ldr r4, [r1, #MDREFR_OFFS] + + orr r4, r4, #0x00800000 // K0Free on + str r4, [r1, #MDREFR_OFFS] + ldr r4, [r1, #MDREFR_OFFS] + nop + nop + + // Step 4 + //ldr r2, =MDCNFG_VAL + adr r2, mpc50_static_info + ldr r2, [r2, #MPC50_VAL_OFFS_MDCNFG] + + + bic r2, r2, #0x0003 // DE1-0 + bic r2, r2, #0x00030000 // DE3-2 + str r2, [r1, #MDCNFG_OFFS] + +// Step 5 +// wait 200 usec + ldr r1, =PXA2X0_OSTIMER_BASE + mov r0, #0 + str r0, [r1, #OSCR_OFFS] + ldr r2, =0x300 +71: + ldr r0, [r1, #OSCR_OFFS] + cmp r2, r0 + bgt 71b + +// Step 6 + mov r0, #0x78 + mcr p15, 0, r0, c1, c0, 0 // (caches off, MMU off, etc.) + +// Step 7 + ldr r2, =PXA2X0_RAM_BANK0_BASE + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + +// Step 8 +// +// Step 9 +// SDRAM enable + //ldr r3, =MDCNFG_VAL + adr r3, mpc50_static_info + ldr r3, [r3, #MPC50_VAL_OFFS_MDCNFG] + + + ldr r2, =0x00030003 + and r2, r3, r2 + ldr r1, =PXA2X0_MEMORY_CTL_BASE + ldr r3, [r1, #MDCNFG_OFFS] + orr r3, r3, r2 + str r3, [r1, #MDCNFG_OFFS] + +// Step 10 + ldr r2, =MDMRS_VAL + str r2, [r1, #MDMRS_OFFS] +.endm + + +/********************************************************************************************************************** +* GPIOs +**********************************************************************************************************************/ + +// GPIO Name Pin GPDR GAFR GPSR + +// 0 INT0 L10 0 00 0 +// 1 INT1 L12 0 00 0 +// 2 FLX-CLK L13 1 00 0 +// 3 FLX-DAT K14 1 00 0 + +// 4 FLX-CONFIG J12 1 00 1 +// 5 FLX-STATUS J11 0 00 0 +// 6 FLX-CONFDONE H14 0 00 0 +// 7 LAN_INT G15 0 00 0 + +// 8 USB-H-ON F14 1 00 1 +// 9 USB-CL-ON F12 0 00 0 +// 10 MPSB-INT0 F7 0 00 0 +// 11 - A7 0 00 0 + +// 12 MPSB-INT1 B6 0 00 0 +// 13 MBGNT B5 1 10 0 +// 14 MBREQ B4 0 01 0 +// 15 nCS_1 T8 1 10 1 + +#define GAFR0_L_VAL 0x80000000 //0x98000000 + +// 16 PWM0 E12 0 00 0 +// 17 PWM1 D12 0 00 0 +// 18 RDY C1 0 01 0 +// 19 DREQ[1] N14 0 00 0 + +// 20 DREQ[0] N12 0 00 0 +// 21 DVAL0 N15 0 00 0 +// 22 DVAL1 M12 0 00 0 +// 23 SSPSCLK F9 0 00 0 + +// 24 SSPSFRM E9 0 00 0 +// 25 SSPTXD D9 0 00 0 +// 26 SSPRXD A9 0 00 0 +// 27 SSPEXTCLK B9 0 00 0 + +// 28 BITCLK C9 0 00 0 +// 29 SDATIN0 E10 0 00 0 +// 30 SDATOUT A10 0 00 0 +// 31 SYNC E11 0 00 0 + +#define GPDR0_VAL 0x0000811c //0x0000a11c +#define GAFR0_U_VAL 0x00000010 +#define GPSR0_VAL 0x00008110 + +// 32 SDATIN1 A16 0 00 0 +// 33 Reset-Button T13 0 00 0 +// 34 FFRXD A13 0 01 0 +// 35 FFCTS A14 0 01 0 + +// 36 FFDCD A12 0 01 0 +// 37 FFDSR B11 0 01 0 +// 38 FFRI B10 0 01 0 +// 39 FFTXD E13 1 10 1 + +// 40 FFDTR F10 1 10 1 +// 41 FFRTS F8 1 10 1 +// 42 BTRXD B13 0 00 0 +// 43 BTTXD D13 0 00 0 + +// 44 BTCTS A15 0 00 0 +// 45 BTRTS B14 0 00 0 +// 46 IRRXD B15 0 00 0 +// 47 IRTXD C15 0 00 0 + +#define GAFR1_L_VAL 0x000a9550 + + +// 48 LED_DP P13 1 00 0 +// 49 LED_G T14 1 00 0 +// 50 LED_F T15 1 00 0 +// 51 LED_E R15 1 00 0 + +// 52 LED_D P14 1 00 0 +// 53 LED_C R16 1 00 0 +// 54 LED_B P16 1 00 0 +// 55 LED_A M13 1 00 0 + +// 56 GPIO56 N16 0 00 0 +// 57 GPIO57 M16 0 00 0 +// 58 LCDD0 E7 0 00 0 +// 59 LCDD1 D7 0 00 0 + +// 60 LCDD2 C7 0 00 0 +// 61 LCDD3 B7 0 00 0 +// 62 LCDD4 E6 0 00 0 +// 63 LCDD5 D6 0 00 0 + +#define GPDR1_VAL 0x00ff0380 +#define GAFR1_U_VAL 0x00000000 +#define GPSR1_VAL 0x00000380 +#define GPSR_LED_VAL 0x00ff0000 + +// 64 LCDD6 E5 0 00 0 +// 65 LCDD7 A6 0 00 0 +// 66 LCDD8 C5 0 00 0 +// 67 LCDD9 A5 0 00 0 + +// 68 LCDD10 D5 0 00 0 +// 69 LCDD11 A4 0 00 0 +// 70 LCDD12 A3 0 00 0 +// 71 LCDD13 A2 0 00 0 + +// 72 LCDD14 C3 0 00 0 +// 73 LCDD15 B3 0 00 0 +// 74 LCDFCLK E8 0 00 0 +// 75 LCDLCLK D8 0 00 0 + +// 76 LCDPCLK B8 0 00 0 +// 77 LCDBIAS A8 0 00 0 +// 78 n_CS2 P9 1 10 1 +// 79 LAN_RES T9 1 00 1 + +#define GAFR2_L_VAL 0x20000000 + +// 80 n_CS4 R13 0 00 0 + +#define GPDR2_VAL 0x0000c000 +#define GAFR2_U_VAL 0x00000000 +#define GPSR2_VAL 0x0000c000 + + +#define GPSR0_OFFS (PXA2X0_GPSR0-PXA2X0_GPIO_BASE) +#define GPCR0_OFFS (PXA2X0_GPCR0-PXA2X0_GPIO_BASE) +#define GPSR1_OFFS (PXA2X0_GPSR1-PXA2X0_GPIO_BASE) +#define GPCR1_OFFS (PXA2X0_GPCR1-PXA2X0_GPIO_BASE) +#define GPSR2_OFFS (PXA2X0_GPSR2-PXA2X0_GPIO_BASE) +#define GPCR2_OFFS (PXA2X0_GPCR2-PXA2X0_GPIO_BASE) +#define GPDR0_OFFS (PXA2X0_GPDR0-PXA2X0_GPIO_BASE) +#define GPDR1_OFFS (PXA2X0_GPDR1-PXA2X0_GPIO_BASE) +#define GPDR2_OFFS (PXA2X0_GPDR2-PXA2X0_GPIO_BASE) +#define GAFR0_L_OFFS (PXA2X0_GAFR0_L-PXA2X0_GPIO_BASE) +#define GAFR0_U_OFFS (PXA2X0_GAFR0_U-PXA2X0_GPIO_BASE) +#define GAFR1_L_OFFS (PXA2X0_GAFR1_L-PXA2X0_GPIO_BASE) +#define GAFR1_U_OFFS (PXA2X0_GAFR1_U-PXA2X0_GPIO_BASE) +#define GAFR2_L_OFFS (PXA2X0_GAFR2_L-PXA2X0_GPIO_BASE) +#define GAFR2_U_OFFS (PXA2X0_GAFR2_U-PXA2X0_GPIO_BASE) +#define PSSR_OFFS (PXA2X0_PSSR-PXA2X0_PM_BASE) + +.macro init_mpc_gpio + ldr r1, =PXA2X0_GPIO_BASE + + ldr r0, =GPSR0_VAL // set GPIO outputs to default + str r0, [r1, #GPSR0_OFFS] + mvn r0, r0 + str r0, [r1, #GPCR0_OFFS] + ldr r0, =GPSR1_VAL // set GPIO outputs to default + str r0, [r1, #GPSR1_OFFS] + mvn r0, r0 + str r0, [r1, #GPCR1_OFFS] + ldr r0, =GPSR2_VAL // set GPIO outputs to default + str r0, [r1, #GPSR2_OFFS] + mvn r0, r0 + str r0, [r1, #GPCR2_OFFS] + + ldr r0, =GPDR0_VAL // GPIO direction + str r0, [r1, #GPDR0_OFFS] + ldr r0, =GPDR1_VAL // GPIO direction + str r0, [r1, #GPDR1_OFFS] + ldr r0, =GPDR2_VAL // GPIO direction + str r0, [r1, #GPDR2_OFFS] + + ldr r0, =GAFR0_L_VAL // GPIO alternate function + str r0, [r1, #GAFR0_L_OFFS] + ldr r0, =GAFR0_U_VAL // GPIO alternate function + str r0, [r1, #GAFR0_U_OFFS] + ldr r0, =GAFR1_L_VAL // GPIO alternate function + str r0, [r1, #GAFR1_L_OFFS] + ldr r0, =GAFR1_U_VAL // GPIO alternate function + str r0, [r1, #GAFR1_U_OFFS] + ldr r0, =GAFR2_L_VAL // GPIO alternate function + str r0, [r1, #GAFR2_L_OFFS] + ldr r0, =GAFR2_U_VAL // GPIO alternate function + str r0, [r1, #GAFR2_U_OFFS] + + ldr r1, =PXA2X0_PM_BASE + ldr r0, =0x20 + str r0, [r1, #PSSR_OFFS] // enable GPIO inputs + +.endm + +/********************************************************************************************************************** +* LED +**********************************************************************************************************************/ +// -7- +// | | +// 1 6 +// | | +// -2- +// | | +// 3 5 +// | | +// -4- 0 + +#define CYGHWR_LED_MACRO \ + b 2f ;\ +1: ;\ + .byte 0xfb, 0x61, 0xdd, 0xf5 ;\ + .byte 0x67, 0xb7, 0xbf, 0xe1 ;\ + .byte 0xff, 0xf7, 0xef, 0x3f ;\ + .byte 0x1d, 0x7d, 0x9f, 0x8f ;\ +2: ;\ + ldr r1, =PXA2X0_GPIO_BASE ;\ + mov r0, #0x00ff0000 ;\ + str r0, [r1, #GPSR1_OFFS] ;\ + sub r0, pc, #((3f+4)-1b) ;\ +3: ;\ + ldrb r0, [r0, #\x] ;\ + mov r0, r0, lsl #16 ;\ + str r0, [r1, #GPCR1_OFFS] ; + +/********************************************************************************************************************** +* initialize controller +**********************************************************************************************************************/ + +#if defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU +#else +#define PLATFORM_SETUP1 +#endif + +.macro _platform_setup1 + .rept 0x20/4 + nop + .endr + b 1f + +.globl mpc50_static_info // Space for some static information +mpc50_static_info: + .byte 'M','P','C','5' // Magic + .rept 16 + .long 0 + .endr +1: + init_mmu_off // MMU on (and Cache) + init_mpc_gpio // GPIOs + LED(12) + init_sdram_cnt // SDRAM + LED(11) + init_intc_cnt // Interrupt Controller + LED(10) + init_clks // Clocks + LED(9) + init_mmu_cache_on // MMU and Cache + LED(8) +.endm + +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/mpc50.h @@ -0,0 +1,93 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_MPC50_H +#define CYGONCE_HAL_ARM_XSCALE_MPC50_H +//========================================================================== +// +// mpc50.h +// +// Platform specific support (register layout, etc) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2003-01-06 +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// FPGA +// Config +#define MPC50_FPGA_DATA_CLOCK 0x00000004 +#define MPC50_FPGA_DATA 0x00000008 +#define MPC50_FPGA_CONFIG 0x00000010 +#define MPC50_FPGA_STATUS 0x00000020 +#define MPC50_FPGA_CONFIG_DONE 0x00000040 +// Use +#define MPC50_FPGA_IRQ0 CYGNUM_HAL_INTERRUPT_GPIO0 +#define MPC50_FPGA_IRQ1 CYGNUM_HAL_INTERRUPT_GPIO1 + +#define MPC_FPGA_IRQ MPC50_FPGA_IRQ0 +#define MPC_FPGA_BASE ((unsigned char *)0x60000000) + +// Ethernet +#define MPC50_ETH_IOBASE 0x68000000 +#define MPC50_ETH_IRQ CYGNUM_HAL_INTERRUPT_GPIO7 +#define MPC50_ETH_RESET 0x00008000 + +// Flash +#define MPC50_FLASH_BASE 0x50000000 + +// Button +#ifndef __ASSEMBLER__ +#define MPC50_BUTTON_PRESSED ((*PXA2X0_GPLR1 & 0x00000002)==0) +#endif + +// static values (offsets) +#define MPC50_VAL_MAGIC (('5'<<24)+('C'<<16)+('P'<<8)+'M') +#define MPC50_VAL_OFFS_CCCR 4 +#define MPC50_VAL_OFFS_MDREFR 8 +#define MPC50_VAL_OFFS_MDCNFG 12 + +#ifndef __ASSEMBLER__ +void mpc50_program_new_stack(void *func); +void mpc50_user_hardware_init(void); +#endif + + + + +#endif //CYGONCE_HAL_ARM_XSCALE_MPC50_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_ram.h @@ -0,0 +1,14 @@ +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x2000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x2000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_ram.ldi @@ -0,0 +1,24 @@ +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x02000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x10000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + .romfs ALIGN(0x20) : {*(.romfs)} > ram + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_ram.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 0 2000000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 20000 20000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_rom.h @@ -0,0 +1,17 @@ +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x2000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x20000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x2000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_rom.ldi @@ -0,0 +1,24 @@ +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x02000000 + rom : ORIGIN = 0x50000000, LENGTH = 0x00020000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0xa000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/pkgconf/mlt_arm_pxa2x0_mpc50_rom.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 00000000 02000000 0 ! +region rom 50000000 00020000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 a000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/include/plf_io.h @@ -0,0 +1,53 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_MPC50_PLF_IO_H +#define CYGONCE_HAL_ARM_XSCALE_MPC50_PLF_IO_H +//========================================================================== +// +// plf_io.h +// +// Platform specific support (register layout, etc) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2003-01-06 +// +//####DESCRIPTIONEND#### +// +//========================================================================== +#include <cyg/hal/mpc50.h> + +#endif //CYGONCE_HAL_ARM_XSCALE_MPC50_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/mpc50/current/src/mpc50_misc.c @@ -0,0 +1,183 @@ +//========================================================================== +// +// mpc50_misc.c +// +// HAL misc board support code for MPC 5.0 +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2003-01-06 +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_pxa2x0.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/mpc50.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_mm.h> + + +void hal_mmu_init(void) +{ +#ifdef CYG_HAL_STARTUP_ROM + + typedef cyg_uint32 aptr; // for arithmetic + + unsigned long ttb_base = PXA2X0_RAM_BANK0_BASE + 0x4000; + unsigned long *SDRAMConfig; + int *p_hdsize = (int *)((aptr)(&hal_dram_size) | (0xA00u *SZ_1M)); + int *p_hdtype = (int *)((aptr)(&hal_dram_type) | (0xA00u *SZ_1M)); + + *p_hdtype = 0; + for(SDRAMConfig=0; *SDRAMConfig != MPC50_VAL_MAGIC ;SDRAMConfig++); + SDRAMConfig += (MPC50_VAL_OFFS_MDCNFG>>2); + + // set TTB Register + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base)); + + // erase Page Table + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + // create Page Table + + /* Actual Virtual Size Attribute Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x500, 16, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */ + X_ARM_MMU_SECTION(0x040, 0x600, 64, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* FPGA Register */ + X_ARM_MMU_SECTION(0x080, 0x680, 64, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* LAN Register */ + X_ARM_MMU_SECTION(0x400, 0x400, 192, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PXA2x0 Register */ + + if((*SDRAMConfig & 0x00000018) == 0x08) // 32MB per bank + { + X_ARM_MMU_SECTION(0xA00, 0x0, 32, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 0 */ + X_ARM_MMU_SECTION(0xA40, 0x020, 32, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 1 */ + *p_hdsize = 64 * SZ_1M; // 64MB + if((*SDRAMConfig & 0x00030000) != 0) // 4 banks + { + X_ARM_MMU_SECTION(0xA80, 0x040, 32, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 2 */ + X_ARM_MMU_SECTION(0xAc0, 0x060, 32, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 3 */ + *p_hdsize = 128 * SZ_1M; // 128MB + } + }else{ // 64MB per bank + X_ARM_MMU_SECTION(0xA00, 0x0, 64, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 0 */ + X_ARM_MMU_SECTION(0xA40, 0x040, 64, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 1 */ + *p_hdsize = 128 * SZ_1M; // 128MB + if((*SDRAMConfig & 0x00030000) != 0) // 4 banks + { + X_ARM_MMU_SECTION(0xA80, 0x080, 64, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 2 */ + X_ARM_MMU_SECTION(0xAc0, 0x0c0, 64, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM Bank 3 */ + *p_hdsize = 256 * SZ_1M; // 256MB + } + } + X_ARM_MMU_SECTION(0xA00, 0xA00, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Unmapped Memory */ + + X_ARM_MMU_SECTION(0xC00, 0xC00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); +#endif +} + +void plf_hardware_init(void) +{ + int t; + unsigned long int gpioValue ; + + // enable FFUART clock + gpioValue = *PXA2X0_CKEN ; + gpioValue = gpioValue | (unsigned long)0x40 ; + *PXA2X0_CKEN = gpioValue ; + + mpc50_user_hardware_init(); + + return ; +} + +#include CYGHWR_MEMORY_LAYOUT_H +typedef void code_fun(void); +void mpc50_program_new_stack(void *func) +{ + register CYG_ADDRESS stack_ptr asm("sp"); + register CYG_ADDRESS old_stack asm("r4"); + register code_fun *new_func asm("r0"); + old_stack = stack_ptr; + stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS); + new_func = (code_fun*)func; + new_func(); + stack_ptr = old_stack; + return; +} + +// +// Memory layout +// +externC cyg_uint8 * +hal_arm_mem_real_region_top( cyg_uint8 *regionend ) +{ + CYG_ASSERT( hal_dram_size > 0, "Didn't detect DRAM size!" ); + CYG_ASSERT( hal_dram_size <= 256<<20, "More than 256MB reported - that can't be right" ); + CYG_ASSERT( 0 == (hal_dram_size & 0xfffff), "hal_dram_size not whole Mb" ); + // is it the "normal" end of the DRAM region? If so, it should be + // replaced by the real size + if ( regionend == ((cyg_uint8 *)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) ) + { + regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size; + } + return regionend; +} + +void mpc50_user_hardware_init(void) CYGBLD_ATTRIB_WEAK; + +void mpc50_user_hardware_init() +{ +} + + + +/*------------------------------------------------------------------------*/ +// EOF mpc50_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/ChangeLog @@ -0,0 +1,39 @@ +2003-01-24 Knud Woehler <knud.woehler@microplex.de> +2003-01-24 Mark Salter <msalter@redhat.com> + + * Initial import from Knud Woehler. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/cdl/hal_arm_xscale_pxa2x0.cdl @@ -0,0 +1,136 @@ +# ==================================================================== +# +# hal_arm_xscale_pxa2x0.cdl +# +# Intel PXA2X0 architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with eCos; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +# +# As a special exception, if other files instantiate templates or use macros +# or inline functions from this file, or you compile this file and link it +# with other works to produce a work based on this file, this file does not +# by itself cause the resulting work to be covered by the GNU General Public +# License. However the source code for this file must still be made available +# in accordance with section (3) of the GNU General Public License. +# +# This exception does not invalidate any other reasons why a work based on +# this file might be covered by the GNU General Public License. +# +# Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +# at http://sources.redhat.com/ecos/ecos-license +# ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): <knud.woehler@microplex.de> +# Date: 2003-01-06 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_XSCALE_PXA2X0 { + display "ARM PXA2X0 architecture" + parent CYGPKG_HAL_ARM + hardware + include_dir cyg/hal + define_header hal_arm_xscale_pxa2x0.h + description " + This HAL variant package provides generic + support for the Intel PXA2x0 processors. It is also + necessary to select a specific target platform HAL + package." + + implements CYGINT_HAL_ARM_ARCH_PXA2X0 + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + define_proc { + puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>" + puts $::cdl_header "#define CYGBLD_HAL_VAR_H <cyg/hal/hal_pxa2x0.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" + } + + compile hal_diag.c pxa2x0_misc.c + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + description " + This option selects the heartbeat rate for the real-time clock. + The rate is specified in ticks per second. Change this value + with caution - too high and your system will become saturated + just handling clock interrupts, too low and some operations + such as thread scheduling may become sluggish." + } + + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + # UART + cdl_interface CYGHWR_HAL_ARM_PXA2X0_FFUART { + display "FFUART available as diagnostic/debug channel" + description " + The PXA2X0 chip has multiple serial channels which may be + used for different things on different platforms. This + interface allows a platform to indicate that the specified + serial port can be used as a diagnostic and/or debug channel." + } + + cdl_interface CYGHWR_HAL_ARM_PXA2X0_BTUART { + display "BTUART available as diagnostic/debug channel" + description " + The PXA2X0 chip has multiple serial channels which may be + used for different things on different platforms. This + interface allows a platform to indicate that the specified + serial port can be used as a diagnostic and/or debug channel." + } + + cdl_interface CYGHWR_HAL_ARM_PXA2X0_STUART { + display "STUART available as diagnostic/debug channel" + description " + The PXA2X0 chip has multiple serial channels which may be + used for different things on different platforms. This + interface allows a platform to indicate that the specified + serial port can be used as a diagnostic and/or debug channel." + } + +} + + + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_diag.h @@ -0,0 +1,77 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2002-09-03 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) +extern void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(n) hal_delay_us(n); + +#else + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +#define HAL_DIAG_INIT() hal_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif + +#endif //CYGONCE_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h @@ -0,0 +1,618 @@ +//========================================================================== +// +// hal_pxa2x0.h +// +// HAL misc board support definitions for PXA250/210 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2003-01-06 +// +//####DESCRIPTIONEND#### +// +//========================================================================== +#ifndef CYGONCE_HAL_ARM_PXA2X0_H +#define CYGONCE_HAL_ARM_PXA2X0_H + +#include <pkgconf/system.h> +#include <cyg/hal/hal_xscale.h> + +#ifdef __ASSEMBLER__ +#define PXA2X0_REGISTER(a) (a) +#else +#define PXA2X0_REGISTER(a) ((volatile unsigned long *)(a)) +#endif + +// Memory layout +#define PXA2X0_CS0_BASE (0x00000000) +#define PXA2X0_CS1_BASE (0x04000000) +#define PXA2X0_CS2_BASE (0x08000000) +#define PXA2X0_CS3_BASE (0x0c000000) +#define PXA2X0_CS4_BASE (0x10000000) +#define PXA2X0_CS5_BASE (0x14000000) + +#define PXA2X0_PCMCIA0_BASE (0x20000000) +#define PXA2X0_PCMCIA1_BASE (0x30000000) + +#define PXA2X0_PERIPHERALS_BASE (0x40000000) +#define PXA2X0_LCD_BASE (0x44000000) +#define PXA2X0_MEMORY_CTL_BASE (0x48000000) + +#define PXA2X0_RAM_BANK0_BASE (0xA0000000) +#define PXA2X0_RAM_BANK1_BASE (0xA4000000) +#define PXA2X0_RAM_BANK2_BASE (0xA8000000) +#define PXA2X0_RAM_BANK3_BASE (0xAc000000) + +#define PXA2X0_CACHE_FLUSH_BASE (0xc0000000) + +#define DCACHE_FLUSH_AREA 0xc0000000 + +// DMA Controller +#define PXA2X0_DMA_CTL_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0000000 ) +#define PXA2X0_DCSR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0000 ) +#define PXA2X0_DCSR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0004 ) +#define PXA2X0_DCSR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0008 ) +#define PXA2X0_DCSR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x000c ) +#define PXA2X0_DCSR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0010 ) +#define PXA2X0_DCSR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0014 ) +#define PXA2X0_DCSR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0018 ) +#define PXA2X0_DCSR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x001c ) +#define PXA2X0_DCSR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0020 ) +#define PXA2X0_DCSR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0024 ) +#define PXA2X0_DCSR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0028 ) +#define PXA2X0_DCSR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x002c ) +#define PXA2X0_DCSR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0030 ) +#define PXA2X0_DCSR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0034 ) +#define PXA2X0_DCSR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0038 ) +#define PXA2X0_DCSR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x003c ) +#define PXA2X0_DINT PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x00f0 ) +#define PXA2X0_DRCMR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0100 ) +#define PXA2X0_DRCMR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0104 ) +#define PXA2X0_DRCMR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0108 ) +#define PXA2X0_DRCMR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x010c ) +#define PXA2X0_DRCMR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0110 ) +#define PXA2X0_DRCMR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0114 ) +#define PXA2X0_DRCMR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0118 ) +#define PXA2X0_DRCMR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x011c ) +#define PXA2X0_DRCMR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0120 ) +#define PXA2X0_DRCMR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0124 ) +#define PXA2X0_DRCMR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0128 ) +#define PXA2X0_DRCMR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x012c ) +#define PXA2X0_DRCMR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0130 ) +#define PXA2X0_DRCMR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0134 ) +#define PXA2X0_DRCMR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0138 ) +#define PXA2X0_DRCMR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x013c ) +#define PXA2X0_DRCMR16 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0140 ) +#define PXA2X0_DRCMR17 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0144 ) +#define PXA2X0_DRCMR18 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0148 ) +#define PXA2X0_DRCMR19 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x014c ) +#define PXA2X0_DRCMR20 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0150 ) +#define PXA2X0_DRCMR21 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0154 ) +#define PXA2X0_DRCMR22 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0158 ) +#define PXA2X0_DRCMR23 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x015c ) +#define PXA2X0_DRCMR24 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0160 ) +#define PXA2X0_DRCMR25 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0164 ) +#define PXA2X0_DRCMR26 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0168 ) +#define PXA2X0_DRCMR27 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x016c ) +#define PXA2X0_DRCMR28 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0170 ) +#define PXA2X0_DRCMR29 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0174 ) +#define PXA2X0_DRCMR30 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0178 ) +#define PXA2X0_DRCMR31 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x017c ) +#define PXA2X0_DRCMR32 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0180 ) +#define PXA2X0_DRCMR33 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0184 ) +#define PXA2X0_DRCMR34 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0188 ) +#define PXA2X0_DRCMR35 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x018c ) +#define PXA2X0_DRCMR36 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0190 ) +#define PXA2X0_DRCMR37 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0194 ) +#define PXA2X0_DRCMR38 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0198 ) +#define PXA2X0_DRCMR39 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x019c ) +#define PXA2X0_DDADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0200 ) +#define PXA2X0_DSADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0204 ) +#define PXA2X0_DTADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0208 ) +#define PXA2X0_DCMD0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x020c ) +#define PXA2X0_DDADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0210 ) +#define PXA2X0_DSADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0214 ) +#define PXA2X0_DTADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0218 ) +#define PXA2X0_DCMD1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x021c ) +#define PXA2X0_DDADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0220 ) +#define PXA2X0_DSADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0224 ) +#define PXA2X0_DTADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0228 ) +#define PXA2X0_DCMD2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x022c ) +#define PXA2X0_DDADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0230 ) +#define PXA2X0_DSADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0234 ) +#define PXA2X0_DTADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0238 ) +#define PXA2X0_DCMD3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x023c ) +#define PXA2X0_DDADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0240 ) +#define PXA2X0_DSADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0244 ) +#define PXA2X0_DTADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0248 ) +#define PXA2X0_DCMD4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x024c ) +#define PXA2X0_DDADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0250 ) +#define PXA2X0_DSADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0254 ) +#define PXA2X0_DTADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0258 ) +#define PXA2X0_DCMD5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x025c ) +#define PXA2X0_DDADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0260 ) +#define PXA2X0_DSADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0264 ) +#define PXA2X0_DTADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0268 ) +#define PXA2X0_DCMD6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x026c ) +#define PXA2X0_DDADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0270 ) +#define PXA2X0_DSADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0274 ) +#define PXA2X0_DTADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0278 ) +#define PXA2X0_DCMD7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x027c ) +#define PXA2X0_DDADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0280 ) +#define PXA2X0_DSADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0284 ) +#define PXA2X0_DTADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0288 ) +#define PXA2X0_DCMD8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x028c ) +#define PXA2X0_DDADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0290 ) +#define PXA2X0_DSADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0294 ) +#define PXA2X0_DTADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0298 ) +#define PXA2X0_DCMD9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x029c ) +#define PXA2X0_DDADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a0 ) +#define PXA2X0_DSADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a4 ) +#define PXA2X0_DTADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a8 ) +#define PXA2X0_DCMD10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ac ) +#define PXA2X0_DDADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b0 ) +#define PXA2X0_DSADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b4 ) +#define PXA2X0_DTADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b8 ) +#define PXA2X0_DCMD11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02bc ) +#define PXA2X0_DDADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c0 ) +#define PXA2X0_DSADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c4 ) +#define PXA2X0_DTADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c8 ) +#define PXA2X0_DCMD12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02cc ) +#define PXA2X0_DDADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d0 ) +#define PXA2X0_DSADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d4 ) +#define PXA2X0_DTADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d8 ) +#define PXA2X0_DCMD13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02dc ) +#define PXA2X0_DDADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e0 ) +#define PXA2X0_DSADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e4 ) +#define PXA2X0_DTADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e8 ) +#define PXA2X0_DCMD14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ec ) +#define PXA2X0_DDADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f0 ) +#define PXA2X0_DSADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f4 ) +#define PXA2X0_DTADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f8 ) +#define PXA2X0_DCMD15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02fc ) + +// Full Function UART +#define PXA2X0_FFUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0100000 ) +#define PXA2X0_FFRBR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 ) +#define PXA2X0_FFTHR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 ) +#define PXA2X0_FFIER PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 ) +#define PXA2X0_FFIIR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 ) +#define PXA2X0_FFFCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 ) +#define PXA2X0_FFLCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x000c ) +#define PXA2X0_FFMCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0010 ) +#define PXA2X0_FFLSR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0014 ) +#define PXA2X0_FFMSR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0018 ) +#define PXA2X0_FFSPR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x001c ) +#define PXA2X0_FFISR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0020 ) +#define PXA2X0_FFDLL PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 ) +#define PXA2X0_FFDLH PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 ) + +// Bluetooth UART +#define PXA2X0_BTUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0200000 ) +#define PXA2X0_BTRBR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 ) +#define PXA2X0_BTTHR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 ) +#define PXA2X0_BTIER PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 ) +#define PXA2X0_BTIIR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 ) +#define PXA2X0_BTFCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 ) +#define PXA2X0_BTLCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x000c ) +#define PXA2X0_BTMCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0010 ) +#define PXA2X0_BTLSR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0014 ) +#define PXA2X0_BTMSR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0018 ) +#define PXA2X0_BTSPR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x001c ) +#define PXA2X0_BTISR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0020 ) +#define PXA2X0_BTDLL PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 ) +#define PXA2X0_BTDLH PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 ) + +// I2C +#define PXA2X0_I2C_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0300000 ) +#define PXA2X0_IBMR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1680 ) +#define PXA2X0_IDBR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1688 ) +#define PXA2X0_ICR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1690 ) +#define PXA2X0_ISR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1698 ) +#define PXA2X0_ISAR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x16a0 ) + + +// I2S +#define PXA2X0_I2S_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0400000 ) +#define PXA2X0_SACR0 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0000 ) +#define PXA2X0_SACR1 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0004 ) +#define PXA2X0_SASR0 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x000c ) +#define PXA2X0_SAIMR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0014 ) +#define PXA2X0_SAICR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0018 ) +#define PXA2X0_SADIV PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0060 ) +#define PXA2X0_SADR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0080 ) + +// AC97 +#define PXA2X0_AC97_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0500000 ) +#define PXA2X0_POCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0000 ) +#define PXA2X0_PICR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0004 ) +#define PXA2X0_MCCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0008 ) +#define PXA2X0_GCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x000c ) +#define PXA2X0_POSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0010 ) +#define PXA2X0_PISR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0014 ) +#define PXA2X0_MCSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0018 ) +#define PXA2X0_GSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x001c ) +#define PXA2X0_CAR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0020 ) +#define PXA2X0_PCDR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0040 ) +#define PXA2X0_MCDR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0060 ) +#define PXA2X0_MOCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0100 ) +#define PXA2X0_MICR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0108 ) +#define PXA2X0_MOSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0110 ) +#define PXA2X0_MISR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0118 ) +#define PXA2X0_MODR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0140 ) +#define PXA2X0_AC97_PRIM_AUDIO_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0200 ) +#define PXA2X0_AC97_SEC_AUDIO_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0300 ) +#define PXA2X0_AC97_PRIM_MODEM_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0400 ) +#define PXA2X0_AC97_SEC_MODEM_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0500 ) + +// UDC +#define PXA2X0_UDC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0600000 ) +#define PXA2X0_UDCCR PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0000 ) +#define PXA2X0_UDCCS0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0010 ) +#define PXA2X0_UDCCS1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0014 ) +#define PXA2X0_UDCCS2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0018 ) +#define PXA2X0_UDCCS3 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x001c ) +#define PXA2X0_UDCCS4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0020 ) +#define PXA2X0_UDCCS5 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0024 ) +#define PXA2X0_UDCCS6 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0028 ) +#define PXA2X0_UDCCS7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x002c ) +#define PXA2X0_UDCCS8 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0030 ) +#define PXA2X0_UDCCS9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0034 ) +#define PXA2X0_UDCCS10 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0038 ) +#define PXA2X0_UDCCS11 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x003c ) +#define PXA2X0_UDCCS12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0040 ) +#define PXA2X0_UDCCS13 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0044 ) +#define PXA2X0_UDCCS14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0048 ) +#define PXA2X0_UDCCS15 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x004c ) +#define PXA2X0_UFNRH PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0060 ) +#define PXA2X0_UFNRL PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0064 ) +#define PXA2X0_UBCR2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0068 ) +#define PXA2X0_UBCR4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x006c ) +#define PXA2X0_UBCR7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0070 ) +#define PXA2X0_UBCR9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0074 ) +#define PXA2X0_UBCR12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0078 ) +#define PXA2X0_UBCR14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x007c ) +#define PXA2X0_UDDR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0080 ) +#define PXA2X0_UDDR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0100 ) +#define PXA2X0_UDDR2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0180 ) +#define PXA2X0_UDDR3 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0200 ) +#define PXA2X0_UDDR4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0400 ) +#define PXA2X0_UDDR5 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00a0 ) +#define PXA2X0_UDDR6 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0600 ) +#define PXA2X0_UDDR7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0680 ) +#define PXA2X0_UDDR8 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0700 ) +#define PXA2X0_UDDR9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0900 ) +#define PXA2X0_UDDR10 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00c0 ) +#define PXA2X0_UDDR11 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b00 ) +#define PXA2X0_UDDR12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b80 ) +#define PXA2X0_UDDR13 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0c00 ) +#define PXA2X0_UDDR14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0e00 ) +#define PXA2X0_UDDR15 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00e0 ) +#define PXA2X0_UICR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0050 ) +#define PXA2X0_UICR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0054 ) +#define PXA2X0_USIR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0058 ) +#define PXA2X0_USIR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x005c ) + +// Standard UART +#define PXA2X0_STUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0700000 ) +#define PXA2X0_STRBR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 ) +#define PXA2X0_STTHR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 ) +#define PXA2X0_STIER PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 ) +#define PXA2X0_STIIR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 ) +#define PXA2X0_STFCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 ) +#define PXA2X0_STLCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x000c ) +#define PXA2X0_STMCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0010 ) +#define PXA2X0_STLSR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0014 ) +#define PXA2X0_STMSR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0018 ) +#define PXA2X0_STSPR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x001c ) +#define PXA2X0_STISR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0020 ) +#define PXA2X0_STDLL PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 ) +#define PXA2X0_STDLH PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 ) + +// ICP +#define PXA2X0_ICP_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0800000 ) +#define PXA2X0_ICCR0 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0000 ) +#define PXA2X0_ICCR1 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0004 ) +#define PXA2X0_ICCR2 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0008 ) +#define PXA2X0_ICDR PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x000c ) +#define PXA2X0_ICSR0 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0014 ) +#define PXA2X0_ICSR1 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0018 ) + +// RTC +#define PXA2X0_RTC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0900000 ) +#define PXA2X0_RCNR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0000 ) +#define PXA2X0_RTAR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0004 ) +#define PXA2X0_RTSR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0008 ) +#define PXA2X0_RTTR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x000c ) + +// OS Timer +#define PXA2X0_OSTIMER_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0a00000 ) +#define PXA2X0_OSMR0 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0000 ) +#define PXA2X0_OSMR1 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0004 ) +#define PXA2X0_OSMR2 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0008 ) +#define PXA2X0_OSMR3 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x000c ) +#define PXA2X0_OSCR PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0010 ) +#define PXA2X0_OSSR PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0014 ) +#define PXA2X0_OWER PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0018 ) +#define PXA2X0_OIER PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x001c ) + +#define PXA2X0_OSSR_TIMER0 (0x1 << 0) +#define PXA2X0_OSSR_TIMER1 (0x1 << 1) +#define PXA2X0_OSSR_TIMER2 (0x1 << 2) +#define PXA2X0_OSSR_TIMER3 (0x1 << 3) + +#define PXA2X0_OIER_TIMER0 (0x1 << 0) +#define PXA2X0_OIER_TIMER1 (0x1 << 1) +#define PXA2X0_OIER_TIMER2 (0x1 << 2) +#define PXA2X0_OIER_TIMER3 (0x1 << 3) + +#define PXA2X0_OWER_WME (0x1 << 0) + +// PWM 0 +#define PXA2X0_PWM0_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0b00000 ) +#define PXA2X0_PWM_CTRL0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0000 ) +#define PXA2X0_PWM_PWDUTY0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0004 ) +#define PXA2X0_PWM_PERVAL0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0008 ) + +// PWM 1 +#define PXA2X0_PWM1_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0c00000 ) +#define PXA2X0_PWM_CTRL1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0000 ) +#define PXA2X0_PWM_PWDUTY1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0004 ) +#define PXA2X0_PWM_PERVAL1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0008 ) + +// Interrupt Control +#define PXA2X0_IC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0d00000 ) +#define PXA2X0_ICIP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0000 ) +#define PXA2X0_ICMR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0004 ) +#define PXA2X0_ICLR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0008 ) +#define PXA2X0_ICFP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x000c ) +#define PXA2X0_ICPR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0010 ) +#define PXA2X0_ICCR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0014 ) + +// GPIO +#define PXA2X0_GPIO_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0e00000 ) +#define PXA2X0_GPLR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0000 ) +#define PXA2X0_GPLR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0004 ) +#define PXA2X0_GPLR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0008 ) +#define PXA2X0_GPDR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x000c ) +#define PXA2X0_GPDR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0010 ) +#define PXA2X0_GPDR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0014 ) +#define PXA2X0_GPSR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0018 ) +#define PXA2X0_GPSR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x001c ) +#define PXA2X0_GPSR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0020 ) +#define PXA2X0_GPCR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0024 ) +#define PXA2X0_GPCR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0028 ) +#define PXA2X0_GPCR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x002c ) +#define PXA2X0_GRER0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0030 ) +#define PXA2X0_GRER1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0034 ) +#define PXA2X0_GRER2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0038 ) +#define PXA2X0_GFER0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x003c ) +#define PXA2X0_GFER1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0040 ) +#define PXA2X0_GFER2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0044 ) +#define PXA2X0_GEDR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0048 ) +#define PXA2X0_GEDR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x004c ) +#define PXA2X0_GEDR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0050 ) +#define PXA2X0_GAFR0_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0054 ) +#define PXA2X0_GAFR0_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0058 ) +#define PXA2X0_GAFR1_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x005c ) +#define PXA2X0_GAFR1_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 ) +#define PXA2X0_GAFR2_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 ) +#define PXA2X0_GAFR2_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 ) + +// Power Manager and Reset Control +#define PXA2X0_PM_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0f00000 ) +#define PXA2X0_PMCR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0000 ) +#define PXA2X0_PSSR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0004 ) +#define PXA2X0_PSPR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0008 ) +#define PXA2X0_PWER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x000c ) +#define PXA2X0_PRER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0010 ) +#define PXA2X0_PFER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0014 ) +#define PXA2X0_PEDR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0018 ) +#define PXA2X0_PCFR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x001c ) +#define PXA2X0_PGSR0 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0020 ) +#define PXA2X0_PGSR1 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0024 ) +#define PXA2X0_PGSR2 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0028 ) +#define PXA2X0_RCSR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0030 ) + +// SSP +#define PXA2X0_SSP_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1000000 ) +#define PXA2X0_SSCR0 PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0000 ) +#define PXA2X0_SSCR1 PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0004 ) +#define PXA2X0_SSSR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0008 ) +#define PXA2X0_SSITR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x000c ) +#define PXA2X0_SSDR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0010 ) + +// MMC Controller +#define PXA2X0_MMC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1100000 ) +#define PXA2X0_MMC_STRPCL PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0000 ) +#define PXA2X0_MMC_STAT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0004 ) +#define PXA2X0_MMC_CLKRT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0008 ) +#define PXA2X0_MMC_SPI PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x000c ) +#define PXA2X0_MMC_CMDAT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0010 ) +#define PXA2X0_MMC_RESTO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0014 ) +#define PXA2X0_MMC_RDTO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0018 ) +#define PXA2X0_MMC_BLKLEN PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x001c ) +#define PXA2X0_MMC_NOB PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0020 ) +#define PXA2X0_MMC_PRTBUF PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0024 ) +#define PXA2X0_MMC_I_MASK PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0028 ) +#define PXA2X0_MMC_I_REG PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x002c ) +#define PXA2X0_MMC_CMD PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0030 ) +#define PXA2X0_MMC_ARGH PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0034 ) +#define PXA2X0_MMC_ARGL PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0038 ) +#define PXA2X0_MMC_RES PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x003c ) +#define PXA2X0_MMC_RXFIFO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0040 ) +#define PXA2X0_MMC_TXFIFO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0044 ) + +// Clocks Manager +#define PXA2X0_CLK_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1300000 ) +#define PXA2X0_CCCR PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0000 ) +#define PXA2X0_CKEN PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0004 ) +#define PXA2X0_CSCC PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0008 ) + // Memory Clock +#define PXA2X0_CCCR_L09 (0x1f) +#define PXA2X0_CCCR_L27 (0x01) +#define PXA2X0_CCCR_L32 (0x02) +#define PXA2X0_CCCR_L36 (0x03) +#define PXA2X0_CCCR_L40 (0x04) +#define PXA2X0_CCCR_L45 (0x05) + // Memory-to-Run-Mode multiplier +#define PXA2X0_CCCR_M1 (0x1 << 5) +#define PXA2X0_CCCR_M2 (0x2 << 5) +#define PXA2X0_CCCR_M4 (0x3 << 5) + // Run-Mode-to-Turbo-Mode multiplier +#define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0 +#define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5 +#define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0 +#define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5 +#define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0 + + +// LCD Controller +#define PXA2X0_LCCR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0000 ) +#define PXA2X0_LCCR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0004 ) +#define PXA2X0_LCCR2 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0008 ) +#define PXA2X0_LCCR3 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x000c ) +#define PXA2X0_FDADR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0200 ) +#define PXA2X0_FSADR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0204 ) +#define PXA2X0_FIDR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0208 ) +#define PXA2X0_LDCMD0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x020c ) +#define PXA2X0_FDADR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0210 ) +#define PXA2X0_FSADR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0214 ) +#define PXA2X0_FIDR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0218 ) +#define PXA2X0_LDCMD1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x021c ) +#define PXA2X0_FBR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0020 ) +#define PXA2X0_FBR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0024 ) +#define PXA2X0_LCSR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0038 ) +#define PXA2X0_LIIDR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x003c ) +#define PXA2X0_TRGBR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0040 ) +#define PXA2X0_TCR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0044 ) + +// Memory Controller +#define PXA2X0_MDCNFG PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0000 ) +#define PXA2X0_MDREFR PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0004 ) +#define PXA2X0_MSC0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0008 ) +#define PXA2X0_MSC1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x000c ) +#define PXA2X0_MSC2 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0010 ) +#define PXA2X0_MECR PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0014 ) +#define PXA2X0_SXCNFG PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x001c ) +#define PXA2X0_SXMRS PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0024 ) +#define PXA2X0_MCMEM0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0028 ) +#define PXA2X0_MCMEM1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x002c ) +#define PXA2X0_MCATT0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0030 ) +#define PXA2X0_MCATT1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0034 ) +#define PXA2X0_MCIO0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0038 ) +#define PXA2X0_MCIO1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x003c ) +#define PXA2X0_MDMRS PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0040 ) +#define PXA2X0_BOOT_DEF PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0044 ) + +// UART definitions +// Register offsets +#define PXA2X0_UART_RBR ( 0x0000 ) // Receive Buffer Register +#define PXA2X0_UART_THR ( 0x0000 ) // Transmit Hold Register +#define PXA2X0_UART_IER ( 0x0004 ) // Interrupt Enable Register +#define PXA2X0_UART_IIR ( 0x0008 ) // Interrupt ID Register +#define PXA2X0_UART_FCR ( 0x0008 ) +#define PXA2X0_UART_LCR ( 0x000c ) +#define PXA2X0_UART_MCR ( 0x0010 ) +#define PXA2X0_UART_LSR ( 0x0014 ) +#define PXA2X0_UART_MSR ( 0x0018 ) +#define PXA2X0_UART_SPR ( 0x001c ) +#define PXA2X0_UART_ISR ( 0x0020 ) +#define PXA2X0_UART_DLL ( 0x0000 ) +#define PXA2X0_UART_DLH ( 0x0004 ) + + +// The interrupt enable register bits. +#define PXA2X0_UART_IER_RAVIE 0x01 // enable received data available irq +#define PXA2X0_UART_IER_TIE 0x02 // enable transmit data request interrupt +#define PXA2X0_UART_IER_RLSE 0x04 // enable receiver line status irq +#define PXA2X0_UART_IER_MIE 0x08 // enable modem status interrupt +#define PXA2X0_UART_IER_RTOIE 0x10 // enable Rx timeout interrupt +#define PXA2X0_UART_IER_NRZE 0x20 // enable NRZ coding +#define PXA2X0_UART_IER_UUE 0x40 // enable the UART unit +#define PXA2X0_UART_IER_DMAE 0x80 // enable DMA requests + +// The interrupt identification register bits. +#define PXA2X0_UART_IIR_IP 0x01 // 0 if interrupt pending +#define PXA2X0_UART_Tx 0x02 +#define PXA2X0_UART_Rx 0x04 +#define PXA2X0_UART_IIR_ID_MASK 0xff // mask for interrupt ID bits + +// The line status register bits. +#define PXA2X0_UART_LSR_DR 0x01 // data ready +#define PXA2X0_UART_LSR_OE 0x02 // overrun error +#define PXA2X0_UART_LSR_PE 0x04 // parity error +#define PXA2X0_UART_LSR_FE 0x08 // framing error +#define PXA2X0_UART_LSR_BI 0x10 // break interrupt +#define PXA2X0_UART_LSR_THRE 0x20 // transmitter holding register empty +#define PXA2X0_UART_LSR_TEMT 0x40 // transmitter holding and Tx shift registers empty +#define PXA2X0_UART_LSR_ERR 0x80 // any error condition (FIFOE) + +// The modem status register bits. +#define PXA2X0_UART_MSR_DCTS 0x01 // delta clear to send +#define PXA2X0_UART_MSR_DDSR 0x02 // delta data set ready +#define PXA2X0_UART_MSR_TERI 0x04 // trailing edge ring indicator +#define PXA2X0_UART_MSR_DDCD 0x08 // delta data carrier detect +#define PXA2X0_UART_MSR_CTS 0x10 // clear to send +#define PXA2X0_UART_MSR_DSR 0x20 // data set ready +#define PXA2X0_UART_MSR_RI 0x40 // ring indicator +#define PXA2X0_UART_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define PXA2X0_UART_LCR_WLS0 0x01 // word length select bit 0 +#define PXA2X0_UART_LCR_WLS1 0x02 // word length select bit 1 +#define PXA2X0_UART_LCR_STB 0x04 // number of stop bits +#define PXA2X0_UART_LCR_PEN 0x08 // parity enable +#define PXA2X0_UART_LCR_EPS 0x10 // even parity select +#define PXA2X0_UART_LCR_SP 0x20 // stick parity +#define PXA2X0_UART_LCR_SB 0x40 // set break +#define PXA2X0_UART_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define PXA2X0_UART_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define PXA2X0_UART_FCR_FCR1 0x02 // clear RCVR FIFO +#define PXA2X0_UART_FCR_FCR2 0x04 // clear XMIT FIFO +#define PXA2X0_UART_FCR_ITL0 0x40 // Interrupt trigger level (ITL) bit 0 +#define PXA2X0_UART_FCR_ITL1 0x80 // Interrupt trigger level (ITL) bit 1 +#define PXA2X0_UART_FCR_ITL_1BYTE 0x00 // i byte triggers interrupt + +#define PXA2X0_UART_BAUD_RATE_DIVISOR(x) ((14745600/(16*(x)))) + +#endif // CYGONCE_HAL_ARM_PXA2X0_H +// EOF hal_pxa2x0.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_var_ints.h @@ -0,0 +1,192 @@ +#ifndef CYGONCE_HAL_VAR_INTS_H +#define CYGONCE_HAL_VAR_INTS_H +//========================================================================== +// +// hal_var_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2002-09-02 +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_pxa2x0.h> + +// 1st level +// 0-7 Reserved +#define CYGNUM_HAL_INTERRUPT_GPIO0 8 +#define CYGNUM_HAL_INTERRUPT_GPIO1 9 +#define CYGNUM_HAL_INTERRUPT_GPIO 10 +#define CYGNUM_HAL_INTERRUPT_USB 11 +#define CYGNUM_HAL_INTERRUPT_PMU 12 +#define CYGNUM_HAL_INTERRUPT_I2S 13 +#define CYGNUM_HAL_INTERRUPT_AC97 14 +// 15,16 Reserved +#define CYGNUM_HAL_INTERRUPT_LCD 17 +#define CYGNUM_HAL_INTERRUPT_I2C 18 +#define CYGNUM_HAL_INTERRUPT_ICP 19 +#define CYGNUM_HAL_INTERRUPT_STUART 20 +#define CYGNUM_HAL_INTERRUPT_BTUART 21 +#define CYGNUM_HAL_INTERRUPT_FFUART 22 +#define CYGNUM_HAL_INTERRUPT_MMC 23 +#define CYGNUM_HAL_INTERRUPT_SSP 24 +#define CYGNUM_HAL_INTERRUPT_DMA 25 +#define CYGNUM_HAL_INTERRUPT_TIMER0 26 +#define CYGNUM_HAL_INTERRUPT_TIMER1 27 +#define CYGNUM_HAL_INTERRUPT_TIMER2 28 +#define CYGNUM_HAL_INTERRUPT_TIMER3 29 +#define CYGNUM_HAL_INTERRUPT_HZ 30 +#define CYGNUM_HAL_INTERRUPT_ALARM 31 + + +// 2nd level +#define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2) +#define CYGNUM_HAL_INTERRUPT_GPIO3 (32+3) +#define CYGNUM_HAL_INTERRUPT_GPIO4 (32+4) +#define CYGNUM_HAL_INTERRUPT_GPIO5 (32+5) +#define CYGNUM_HAL_INTERRUPT_GPIO6 (32+6) +#define CYGNUM_HAL_INTERRUPT_GPIO7 (32+7) +#define CYGNUM_HAL_INTERRUPT_GPIO8 (32+8) +#define CYGNUM_HAL_INTERRUPT_GPIO9 (32+9) +#define CYGNUM_HAL_INTERRUPT_GPIO10 (32+10) +#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11) +#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12) +#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13) +#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14) +#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15) +#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16) +#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17) +#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18) +#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19) +#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20) +#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21) +#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22) +#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23) +#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24) +#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25) +#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26) +#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27) +#define CYGNUM_HAL_INTERRUPT_GPIO28 (32+28) +#define CYGNUM_HAL_INTERRUPT_GPIO29 (32+29) +#define CYGNUM_HAL_INTERRUPT_GPIO30 (32+30) +#define CYGNUM_HAL_INTERRUPT_GPIO31 (32+31) + +#define CYGNUM_HAL_INTERRUPT_GPIO32 (64+0) +#define CYGNUM_HAL_INTERRUPT_GPIO33 (64+1) +#define CYGNUM_HAL_INTERRUPT_GPIO34 (64+2) +#define CYGNUM_HAL_INTERRUPT_GPIO35 (64+3) +#define CYGNUM_HAL_INTERRUPT_GPIO36 (64+4) +#define CYGNUM_HAL_INTERRUPT_GPIO37 (64+5) +#define CYGNUM_HAL_INTERRUPT_GPIO38 (64+6) +#define CYGNUM_HAL_INTERRUPT_GPIO39 (64+7) +#define CYGNUM_HAL_INTERRUPT_GPIO40 (64+8) +#define CYGNUM_HAL_INTERRUPT_GPIO41 (64+9) +#define CYGNUM_HAL_INTERRUPT_GPIO42 (64+10) +#define CYGNUM_HAL_INTERRUPT_GPIO43 (64+11) +#define CYGNUM_HAL_INTERRUPT_GPIO44 (64+12) +#define CYGNUM_HAL_INTERRUPT_GPIO45 (64+13) +#define CYGNUM_HAL_INTERRUPT_GPIO46 (64+14) +#define CYGNUM_HAL_INTERRUPT_GPIO47 (64+15) +#define CYGNUM_HAL_INTERRUPT_GPIO48 (64+16) +#define CYGNUM_HAL_INTERRUPT_GPIO49 (64+17) +#define CYGNUM_HAL_INTERRUPT_GPIO50 (64+18) +#define CYGNUM_HAL_INTERRUPT_GPIO51 (64+19) +#define CYGNUM_HAL_INTERRUPT_GPIO52 (64+20) +#define CYGNUM_HAL_INTERRUPT_GPIO53 (64+21) +#define CYGNUM_HAL_INTERRUPT_GPIO54 (64+22) +#define CYGNUM_HAL_INTERRUPT_GPIO55 (64+23) +#define CYGNUM_HAL_INTERRUPT_GPIO56 (64+24) +#define CYGNUM_HAL_INTERRUPT_GPIO57 (64+25) +#define CYGNUM_HAL_INTERRUPT_GPIO58 (64+26) +#define CYGNUM_HAL_INTERRUPT_GPIO59 (64+27) +#define CYGNUM_HAL_INTERRUPT_GPIO60 (64+28) +#define CYGNUM_HAL_INTERRUPT_GPIO61 (64+29) +#define CYGNUM_HAL_INTERRUPT_GPIO62 (64+30) +#define CYGNUM_HAL_INTERRUPT_GPIO63 (64+31) + +#define CYGNUM_HAL_INTERRUPT_GPIO64 (96+0) +#define CYGNUM_HAL_INTERRUPT_GPIO65 (96+1) +#define CYGNUM_HAL_INTERRUPT_GPIO66 (96+2) +#define CYGNUM_HAL_INTERRUPT_GPIO67 (96+3) +#define CYGNUM_HAL_INTERRUPT_GPIO68 (96+4) +#define CYGNUM_HAL_INTERRUPT_GPIO69 (96+5) +#define CYGNUM_HAL_INTERRUPT_GPIO70 (96+6) +#define CYGNUM_HAL_INTERRUPT_GPIO71 (96+7) +#define CYGNUM_HAL_INTERRUPT_GPIO72 (96+8) +#define CYGNUM_HAL_INTERRUPT_GPIO73 (96+9) +#define CYGNUM_HAL_INTERRUPT_GPIO74 (96+10) +#define CYGNUM_HAL_INTERRUPT_GPIO75 (96+11) +#define CYGNUM_HAL_INTERRUPT_GPIO76 (96+12) +#define CYGNUM_HAL_INTERRUPT_GPIO77 (96+13) +#define CYGNUM_HAL_INTERRUPT_GPIO78 (96+14) +#define CYGNUM_HAL_INTERRUPT_GPIO79 (96+15) +#define CYGNUM_HAL_INTERRUPT_GPIO80 (96+16) + + +#define CYGNUM_HAL_INTERRUPT_NONE -1 + +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 + +#define CYGNUM_HAL_ISR_MIN 8 +#define CYGNUM_HAL_ISR_MAX (96+16) +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1) + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +externC void hal_clock_latency(cyg_uint32 *); +# define HAL_CLOCK_LATENCY( _pvalue_ ) hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) +#endif + + +// Reset +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + cyg_uint32 ctrl; \ + HAL_DISABLE_INTERRUPTS(ctrl); \ + *PXA2X0_OWER = PXA2X0_OWER_WME; \ + *PXA2X0_OSMR3 = *PXA2X0_OSCR + 1000; \ + for(;;); \ + CYG_MACRO_END + +#define HAL_PLATFORM_RESET_ENTRY 0x00000000 + +#endif // CYGONCE_HAL_VAR_INTS_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/include/var_io.h @@ -0,0 +1,58 @@ +#ifndef CYGONCE_VAR_IO_H +#define CYGONCE_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2002-09-03 +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include <cyg/hal/plf_io.h> + +// Memory mapping details +#ifndef CYGARC_PHYSICAL_ADDRESS +# define CYGARC_PHYSICAL_ADDRESS(x) (((unsigned long)x & 0x3FFFFFFF) + PXA2X0_RAM_BANK0_BASE) +#endif + +#endif //CYGONCE_VAR_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/src/hal_diag.c @@ -0,0 +1,344 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2002-09-03 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // basic machine info +#include <cyg/hal/hal_intr.h> // interrupt macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // Calling interface definitions +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/hal_pxa2x0.h> // Hardware definitions + + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; + int baud_rate; +} channel_data_t; + +/*---------------------------------------------------------------------------*/ +// PXA2X0 Serial Port (UARTx) for Debug + +static void +init_channel(channel_data_t* __ch_data) +{ + cyg_uint8* base = __ch_data->base; + cyg_uint8 lcr; + cyg_uint32 brd; + + // 8-1-no parity. + lcr = PXA2X0_UART_LCR_WLS0 | PXA2X0_UART_LCR_WLS1; + lcr |= PXA2X0_UART_LCR_DLAB; + HAL_WRITE_UINT8( base+PXA2X0_UART_LCR, lcr ); + + // Setup divisor + brd = PXA2X0_UART_BAUD_RATE_DIVISOR( __ch_data->baud_rate ); + HAL_WRITE_UINT8( base+PXA2X0_UART_DLH, (brd >> 8) & 0xff ); + HAL_WRITE_UINT8( base+PXA2X0_UART_DLL, brd & 0xff ); + + + // DLAB = 0 to allow access to FIFOs + lcr &= ~PXA2X0_UART_LCR_DLAB; + HAL_WRITE_UINT8(base+PXA2X0_UART_LCR, lcr); + + // Enable & clear FIFOs + // set Interrupt Trigger Level to be 1 byte + HAL_WRITE_UINT8(base+PXA2X0_UART_FCR, + (PXA2X0_UART_FCR_FCR0 | PXA2X0_UART_FCR_FCR1 | PXA2X0_UART_FCR_FCR2)); // Enable & clear FIFO + + // Configure NRZ, disable DMA requests and enable UART + HAL_WRITE_UINT8(base+PXA2X0_UART_IER, PXA2X0_UART_IER_UUE); +} + +static void +cyg_hal_plf_serial_putc(void *__ch_data, char c) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 lsr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(base+PXA2X0_UART_LSR, lsr); + } while ((lsr & PXA2X0_UART_LSR_THRE) == 0); + + HAL_WRITE_UINT8(base+PXA2X0_UART_THR, c); + + do { + HAL_READ_UINT8(base+PXA2X0_UART_LSR, lsr); + } while ((lsr & PXA2X0_UART_LSR_THRE) == 0); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint8 lsr; + + HAL_READ_UINT8(base+PXA2X0_UART_LSR, lsr); + if ((lsr & PXA2X0_UART_LSR_DR) == 0) + return false; + + HAL_READ_UINT8(base+PXA2X0_UART_RBR, *ch); + + return true; +} + +static cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static channel_data_t ser_channels[] = { +#if CYGHWR_HAL_ARM_PXA2X0_FFUART != 0 + { (cyg_uint8*)PXA2X0_FFUART_BASE, 1000, + CYGNUM_HAL_INTERRUPT_FFUART, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#if CYGHWR_HAL_ARM_PXA2X0_BTUART != 0 + { (cyg_uint8*)PXA2X0_BTUART_BASE, 1000, + CYGNUM_HAL_INTERRUPT_BTUART, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#if CYGHWR_HAL_ARM_PXA2X0_STUART != 0 + { (cyg_uint8*)PXA2X0_STUART_BASE, 1000, + CYGNUM_HAL_INTERRUPT_STUART, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +}; + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + int ret = -1; + cyg_uint8 ier; + va_list ap; + + CYGARC_HAL_SAVE_GP(); + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + init_channel(chan); + ret = 0; + break; + case __COMMCTL_IRQ_ENABLE: + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); + HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); + ier |= PXA2X0_UART_IER_RAVIE; + HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); + irq_state = 1; + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); + ier &= ~PXA2X0_UART_IER_RAVIE; + HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + break; + default: + break; + } + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 iir; + int res = 0; + CYGARC_HAL_SAVE_GP(); + + HAL_READ_UINT8(chan->base+PXA2X0_UART_IIR, iir); + iir &= PXA2X0_UART_IIR_ID_MASK; + + *__ctrlc = 0; + if ( iir == 0x04 ) { + cyg_uint8 c, lsr; + HAL_READ_UINT8(chan->base+PXA2X0_UART_LSR, lsr); + if (lsr & PXA2X0_UART_LSR_DR) { + + HAL_READ_UINT8(chan->base+PXA2X0_UART_RBR, c); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + } + + // Acknowledge the interrupt + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + int i; + + // Init channels +#define NUMOF(x) (sizeof(x)/sizeof(x[0])) + for (i = 0; i < NUMOF(ser_channels); i++) { + init_channel(&ser_channels[i]); + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &ser_channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c @@ -0,0 +1,399 @@ +//========================================================================== +// +// pxa2x0_misc.c +// +// HAL misc board support code for Intel PXA2X0 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): <knud.woehler@microplex.de> +// Date: 2002-09-03 +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_pxa2x0.h> +#include <cyg/hal/hal_mm.h> +#include <cyg/infra/diag.h> + + +// Initialize the interrupt environment +externC void plf_hardware_init(void); + +void hal_hardware_init(void) +{ + hal_xscale_core_init(); + + *PXA2X0_ICMR = 0; // IRQ Mask + *PXA2X0_ICLR = 0; // Route interrupts to IRQ + *PXA2X0_ICCR = 1; + + *PXA2X0_GRER0 = 0; // Disable rising edge detect + *PXA2X0_GRER1 = 0; + *PXA2X0_GRER2 = 0; + + *PXA2X0_GFER0 = 0; // Disable falling edge detect + *PXA2X0_GFER1 = 0; + *PXA2X0_GFER2 = 0; + + *PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status + *PXA2X0_GEDR1 = 0xffffffff; + *PXA2X0_GEDR2 = 0x0001ffff; + + plf_hardware_init(); // Perform any platform specific initializations + + *PXA2X0_OSCR = 0; // Let the "OS" counter run + *PXA2X0_OSMR0 = 0; + + hal_if_init(); // Set up eCos/ROM interfaces + + HAL_DCACHE_ENABLE(); // Enable caches + HAL_ICACHE_ENABLE(); +} + +// Initialize the clock +static cyg_uint32 clock_period; + +void hal_clock_initialize(cyg_uint32 period) +{ + *PXA2X0_OSMR0 = period; // Load match value + clock_period = period; + + *PXA2X0_OSCR = 0; // Start the counter + *PXA2X0_OSSR = PXA2X0_OSSR_TIMER0; // Clear any pending interrupt + *PXA2X0_OIER |= PXA2X0_OIER_TIMER0; // Enable timer 0 interrupt + + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_TIMER0 ); // Unmask timer 0 interrupt +} + +// This routine is called during a clock interrupt. +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + *PXA2X0_OSMR0 = *PXA2X0_OSCR + period; // Load new match value + *PXA2X0_OSSR = PXA2X0_OSSR_TIMER0; // Clear any pending interrupt +} + +// Read the current value of the clock, returning the number of hardware +// "ticks" that have occurred (i.e. how far away the current value is from +// the start) + +// Note: The "contract" for this function is that the value is the number +// of hardware clocks that have happened since the last interrupt (i.e. +// when it was reset). This value is used to measure interrupt latencies. +// However, since the hardware counter runs freely, this routine computes +// the difference between the current clock period and the number of hardware +// ticks left before the next timer interrupt. +void hal_clock_read(cyg_uint32 *pvalue) +{ + int orig; + HAL_DISABLE_INTERRUPTS(orig); + *pvalue = clock_period + *PXA2X0_OSCR - *PXA2X0_OSMR0; + HAL_RESTORE_INTERRUPTS(orig); +} + +// Delay for some number of micro-seconds +void hal_delay_us(cyg_int32 usecs) +{ + cyg_uint32 val = 0; + cyg_uint32 ctr = *PXA2X0_OSCR; + while (usecs-- > 0) { + do { + if (ctr != *PXA2X0_OSCR) { + val += 271267; // 271267ps (3.6865Mhz -> 271.267ns) + ++ctr; + } + } while (val < 1000000); + val -= 1000000; + } +} + + +// Interrupt handling + +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. +int hal_IRQ_handler(void) +{ + cyg_uint32 sources, index; + +#ifdef HAL_EXTENDED_IRQ_HANDLER + // Use platform specific IRQ handler, if defined + // Note: this macro should do a 'return' with the appropriate + // interrupt number if such an extended interrupt exists. The + // assumption is that the line after the macro starts 'normal' processing. + HAL_EXTENDED_IRQ_HANDLER(index); +#endif + + sources = *PXA2X0_ICIP; + + if ( sources & 0xff0000 ) + index = 16; + else if ( sources & 0xff00 ) + index = 8; + else if ( sources & 0xff ) + index = 0; + else // if ( sources & 0xff000000 ) + index = 24; + + do { + if ( (1 << index) & sources ) { + if (index == CYGNUM_HAL_INTERRUPT_GPIO) { + // Special case of GPIO cascade. Search for lowest set bit + sources = *PXA2X0_GEDR0; + index = 0; + do { + if (sources & (1 << index)) { + return index+32; + } + index++; + } while (index < 32); + sources = *PXA2X0_GEDR1; + index = 0; + do { + if (sources & (1 << index)) { + return index+64; + } + index++; + } while (index < 32); + sources = *PXA2X0_GEDR2; + index = 0; + do { + if (sources & (1 << index)) { + return index+96; + } + index++; + } while (index < 16); + + } + return index; + } + index++; + } while ( index & 7 ); + + return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen! +} + +void hal_interrupt_mask(int vector) +{ + +#ifdef HAL_EXTENDED_INTERRUPT_MASK + // Use platform specific handling, if defined + // Note: this macro should do a 'return' for "extended" values of 'vector' + // Normal vectors are handled by code subsequent to the macro call. + HAL_EXTENDED_INTERRUPT_MASK(vector); +#endif + + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { + vector = CYGNUM_HAL_INTERRUPT_GPIO; + } + *PXA2X0_ICMR &= ~(1 << vector); +} + +void hal_interrupt_unmask(int vector) +{ + +#ifdef HAL_EXTENDED_INTERRUPT_UNMASK + // Use platform specific handling, if defined + // Note: this macro should do a 'return' for "extended" values of 'vector' + // Normal vectors are handled by code subsequent to the macro call. + HAL_EXTENDED_INTERRUPT_UNMASK(vector); +#endif + + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { + vector = CYGNUM_HAL_INTERRUPT_GPIO; + } + *PXA2X0_ICMR |= (1 << vector); +} + +void hal_interrupt_acknowledge(int vector) +{ + +#ifdef HAL_EXTENDED_INTERRUPT_UNMASK + // Use platform specific handling, if defined + // Note: this macro should do a 'return' for "extended" values of 'vector' + // Normal vectors are handled by code subsequent to the macro call. + HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector); +#endif + if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) + { + *PXA2X0_GEDR0 = (1 << (vector - 8)); + }else{ + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) { + *PXA2X0_GEDR2 = (1 << (vector - 96)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) { + *PXA2X0_GEDR1 = (1 << (vector - 64)); + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { + *PXA2X0_GEDR0 = (1 << (vector - 32)); + } else { + // Not a GPIO interrupt + return; + } + } +} + +void hal_interrupt_configure(int vector, int level, int up) +{ + +#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE + // Use platform specific handling, if defined + // Note: this macro should do a 'return' for "extended" values of 'vector' + // Normal vectors are handled by code subsequent to the macro call. + HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up); +#endif + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) { + if (level) { + if (up) { + // Enable both edges + *PXA2X0_GRER2 |= (1 << (vector - 96)); + *PXA2X0_GFER2 |= (1 << (vector - 96)); + } else { + // Disable both edges + *PXA2X0_GRER2 &= ~(1 << (vector - 96)); + *PXA2X0_GFER2 &= ~(1 << (vector - 96)); + } + } else { + // Only interested in one edge + if (up) { + // Set rising edge detect and clear falling edge detect. + *PXA2X0_GRER2 |= (1 << (vector - 96)); + *PXA2X0_GFER2 &= ~(1 << (vector - 96)); + } else { + // Set falling edge detect and clear rising edge detect. + *PXA2X0_GFER2 |= (1 << (vector - 96)); + *PXA2X0_GRER2 &= ~(1 << (vector - 96)); + } + } + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) { + if (level) { + if (up) { + // Enable both edges + *PXA2X0_GRER1 |= (1 << (vector - 64)); + *PXA2X0_GFER1 |= (1 << (vector - 64)); + } else { + // Disable both edges + *PXA2X0_GRER1 &= ~(1 << (vector - 64)); + *PXA2X0_GFER1 &= ~(1 << (vector - 64)); + } + } else { + // Only interested in one edge + if (up) { + // Set rising edge detect and clear falling edge detect. + *PXA2X0_GRER1 |= (1 << (vector - 64)); + *PXA2X0_GFER1 &= ~(1 << (vector - 64)); + } else { + // Set falling edge detect and clear rising edge detect. + *PXA2X0_GFER1 |= (1 << (vector - 64)); + *PXA2X0_GRER1 &= ~(1 << (vector - 64)); + } + } + } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) { + if (level) { + if (up) { + // Enable both edges + *PXA2X0_GRER0 |= (1 << (vector - 32)); + *PXA2X0_GFER0 |= (1 << (vector - 32)); + } else { + // Disable both edges + *PXA2X0_GRER0 &= ~(1 << (vector - 32)); + *PXA2X0_GFER0 &= ~(1 << (vector - 32)); + } + } else { + // Only interested in one edge + if (up) { + // Set rising edge detect and clear falling edge detect. + *PXA2X0_GRER0 |= (1 << (vector - 32)); + *PXA2X0_GFER0 &= ~(1 << (vector - 32)); + } else { + // Set falling edge detect and clear rising edge detect. + *PXA2X0_GFER0 |= (1 << (vector - 32)); + *PXA2X0_GRER0 &= ~(1 << (vector - 32)); + } + } + } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) + { + if (level) { + if (up) { + // Enable both edges + *PXA2X0_GRER0 |= (1 << (vector - 8)); + *PXA2X0_GFER0 |= (1 << (vector - 8)); + } else { + // Disable both edges + *PXA2X0_GRER0 &= ~(1 << (vector - 8)); + *PXA2X0_GFER0 &= ~(1 << (vector - 8)); + } + } else { + // Only interested in one edge + if (up) { + // Set rising edge detect and clear falling edge detect. + *PXA2X0_GRER0 |= (1 << (vector - 8)); + *PXA2X0_GFER0 &= ~(1 << (vector - 8)); + } else { + // Set falling edge detect and clear rising edge detect. + *PXA2X0_GFER0 |= (1 << (vector - 8)); + *PXA2X0_GRER0 &= ~(1 << (vector - 8)); + } + } + } + + +} + +void hal_interrupt_set_level(int vector, int level) +{ + +#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL + // Use platform specific handling, if defined + // Note: this macro should do a 'return' for "extended" values of 'vector' + // Normal vectors are handled by code subsequent to the macro call. + HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level); +#endif +} +