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changeset 3184:bded287767e9

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Provide for cache enablement in RAM startup mode [Bugzilla 1001606]
author vae
date Wed, 06 Jun 2012 19:49:59 +0000
parents c8f21fa31800
children 543f9e6905da
files packages/hal/cortexm/kinetis/var/current/ChangeLog packages/hal/cortexm/kinetis/var/current/include/hal_cache.h packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
diffstat 3 files changed, 18 insertions(+), 10 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -1,3 +1,8 @@
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/hal_cache.h, src/kinetis_misc.c: Provide for cache
+	enablement in RAM startup mode            [Bugzilla 1001606]
+
 2012-05-19  John Dallaway  <john@dallaway.org.uk>
 
 	* doc/kinetis.sgml: Close <para> and <refsect2> blocks.
--- a/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
@@ -66,12 +66,12 @@
 // Data cache
 #define HAL_DCACHE_SIZE                 (8192*2) // Size of data cache in bytes
 #define HAL_DCACHE_LINE_SIZE            16       // Size of a data cache line
-#define HAL_DCACHE_WAYS                 2*2      // Associativity of the cache
+#define HAL_DCACHE_WAYS                 (2*2)      // Associativity of the cache
 
 // Instruction cache
-#define HAL_ICACHE_SIZE                 8192*2   // Size of cache in bytes
+#define HAL_ICACHE_SIZE                 (8192*2)   // Size of cache in bytes
 #define HAL_ICACHE_LINE_SIZE            16       // Size of a cache line
-#define HAL_ICACHE_WAYS                 2*2      // Associativity of the cache
+#define HAL_ICACHE_WAYS                 (2*2)      // Associativity of the cache
 
 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
@@ -109,8 +109,8 @@
 // Query the state of the data cache (does not affect the caching)
 #define HAL_DCACHE_IS_ENABLED(_state_)          \
     CYG_MACRO_START                             \
-    (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() && \
-                HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \
+    (_state_) = (HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() && \
+                HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED()); \
     CYG_MACRO_END
 
 // Invalidate cache lines in the given range without writing to memory.
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
@@ -111,10 +111,10 @@ hal_kinetis_flash_conf_p( void )
 
 //=== KINETIS FLASH security configuration END. ============================
 
-#if defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE
+#if defined CYGPKG_HAL_KINETIS_CACHE
 
+# ifndef CYG_HAL_STARTUP_RAM
 // Function for demotion of caching memory regions
-
 static void
 hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p,
                                       cyg_uint32 reg_n, const cyg_uint32 *reg_mode_p)
@@ -134,6 +134,7 @@ hal_cortexm_kinetis_conf_cache_regions(c
     }
     lmem_p->rmr = regval;
 }
+# endif // ndef CYG_HAL_STARTUP_RAM
 
 const cyg_uint32 cache_reg_modes[] = {
     (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) |
@@ -149,7 +150,7 @@ const cyg_uint32 cache_reg_modes[] = {
     CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M
 };
 
-#endif // defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
 
 //==========================================================================
 // Setup variant specific hardware
@@ -158,18 +159,20 @@ const cyg_uint32 cache_reg_modes[] = {
 void hal_variant_init( void )
 {
     hal_update_clock_var();
-#if defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE
+#if defined CYGPKG_HAL_KINETIS_CACHE
+# ifndef CYG_HAL_STARTUP_RAM
     hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P,
         sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
         cache_reg_modes);
     hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P,
         sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
         cache_reg_modes);
+# endif
 # ifdef ENABLE_CACHE_ON_STARTUP
     HAL_DCACHE_ENABLE();
     HAL_ICACHE_ENABLE();
 # endif
-#endif // defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
     hal_if_init();
 #endif