Mercurial > ecos
changeset 1796:bfa08c344743
* include/hal_platform_setup.h: added generation of three
different clocks for watchdog.
| author | asl |
|---|---|
| date | Tue, 05 Oct 2004 12:51:18 +0000 |
| parents | 68f7128db71e |
| children | ac3572aaf2c9 |
| files | packages/hal/arm/at91/jtst/current/ChangeLog packages/hal/arm/at91/jtst/current/include/hal_platform_setup.h |
| diffstat | 2 files changed, 17 insertions(+), 5 deletions(-) [+] |
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--- a/packages/hal/arm/at91/jtst/current/ChangeLog +++ b/packages/hal/arm/at91/jtst/current/ChangeLog @@ -1,3 +1,8 @@ +2004-10-4 Andrea Michelotti <amichelotti@atmel.com> + + * include/hal_platform_setup.h: added generation of three + different clocks for watchdog. + 2004-06-6 Andrea Michelotti <amichelotti@atmel.com> * cdl/hal_arm_at91_jtst.cdl:
--- a/packages/hal/arm/at91/jtst/current/include/hal_platform_setup.h +++ b/packages/hal/arm/at91/jtst/current/include/hal_platform_setup.h @@ -58,21 +58,28 @@ .macro __pio_clkgen_init ldr r0,=AT91_PIO - ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3 + ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27 str r1,[r0,#AT91_PIO_SODR] // set this bit must be always 1, // otherwise resets - ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3 + ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27 str r1,[r0,#AT91_PIO_OER] // set to output str r1,[r0,#AT91_PIO_PER] // software control ldr r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27 str r1,[r0,#AT91_PIO_CODR] // leds all on - ldr r1,=BIT30 - ldr r1,[r0,#AT91_PIO_PDR] // usb interrupt line in - // clockgen 1 is connected to timer ext clk 2 + ldr r1,=BIT30|BIT3 + ldr r1,[r0,#AT91_PIO_PDR] // (BIT30) usb interrupt line in + // (BIT3) active watchdog reset line ldr r0,=AT91_CLKGEN ldr r1,=32 str r1,[r0,#AT91_CLKGEN_CPTMAX0] str r1,[r0,#AT91_CLKGEN_CPTMAX1] + ldr r1,=128 + str r1,[r0,#AT91_CLKGEN_CPTMAX2] //watch dog divider1 + ldr r1,=1024 + str r1,[r0,#AT91_CLKGEN_CPTMAX3] //watch dog divider2 + ldr r1,=2046 + str r1,[r0,#AT91_CLKGEN_CPTMAX4] //watch dog divider3 (max accepted value) + ldr r1,=1 str r1,[r0,#AT91_CLKGEN_CLKENABLE]
