--- a/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
+++ b/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
@@ -1,3 +1,11 @@
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/var_io.h:
+	* src/lpc17xx_misc.c:
+	Recognize Code Read Protection FLASH field
+	Reported by Bernard Fouché [Bugzilla 1001443 ]
+
 2011-05-13  John Dallaway  <john@dallaway.org.uk>
 
 	* include/var_intr.h: Fix I2C interrupt definitions issue reported

--- a/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
+++ b/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
@@ -368,6 +368,20 @@ cdl_package CYGPKG_HAL_CORTEXM_LPC17XX {
         }
     }
 
+    cdl_option CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION {
+        display "Utilize \".lpc17xx_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+        Kinetis use FLASH location  0x2fc for FLASH Code Read Protection.
+        This leaves FLASH area below 0x2fc
+            out of standard linker sections. Special section
+            \".lpc17xx_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
     cdl_interface CYGINT_HAL_LPC17XX_UART0 {
         display      "Platform has UART0 serial port"
         description  "

--- a/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
+++ b/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
@@ -67,6 +67,18 @@
 #define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM               BIT_(28)
 #endif
 
+//---------------------------------------------------------------------------
+// Utilize LPC17xx flash between startup vectors and 0x2fc
+// for misc funtions.
+#ifdef CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".lpc17xx_misc")
+#else
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+#endif
+
+__externC const cyg_uint32* hal_lpc17xx_crp_p(void);
+
 // LPC System Control Block
 #define CYGHWR_HAL_LPC17XX_REG_SCB_BASE                 0x400FC000
 

--- a/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
+++ b/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
@@ -85,6 +85,26 @@ void            hal_lpc_clock_out(void);
 #endif
 //==========================================================================
 
+#ifdef CYG_HAL_STARTUP_ROM
+
+//===========================================================================
+// LPC17xx Code Read Protection field field
+//===========================================================================
+
+// Note: LPC17xx Code Read Protection field field must be present in
+//       LPC17xx flash image and ocupy a word at 0x000002FC
+
+// For ".lpc17xx_crp" section definition see MLT files.
+
+const cyg_uint32 LPC17XX_CRP __attribute__((section(".lpc17xxcrp"), used)) = 0xFFFFFFFF;
+
+#endif // CYG_HAL_STARTUP_ROM
+
+const cyg_uint32* hal_lpc17xx_crp_p(void)
+{
+    return &LPC17XX_CRP;
+}
+
 void
 hal_variant_init(void)
 {
@@ -104,7 +124,7 @@ hal_variant_init(void)
 // that clock rates can be changed at runtime.
 
 
-void
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
 hal_start_clocks(void)
 {
     // Main clock - for everything except USB
@@ -119,7 +139,7 @@ hal_start_clocks(void)
 }
 
 
-void
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
 hal_lpc_start_main_clock(void)
 {
     CYG_ADDRESS     scb_base_p;
@@ -193,7 +213,7 @@ hal_lpc_start_main_clock(void)
     hal_cortexm_systick_clock = hal_lpc17xx_sysclk;
 }
 
-void
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
 hal_lpc_start_usb_clock(void)
 {
     CYG_ADDRESS     scb_base_p;
@@ -233,7 +253,7 @@ hal_lpc_start_usb_clock(void)
 }
 
 #ifdef CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
-void
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
 hal_lpc_clock_out(void)
 {
     cyg_uint32      regval;