Mercurial > ecos
changeset 3005:c6285e8d86d2
* NEWS, ecos.db: Add Stellaris Cortex M3 variant HAL, support for
Stellaris Cortex M3 800 series CPUs. BSP for Stellaris EK-LM3S811
board including ADC and I2C drivers.
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,9 @@ +2011-02-09 Christophe Coutand <ccoutand@stmi.com> + + * NEWS, ecos.db: Add Stellaris Cortex M3 variant HAL, support for + Stellaris Cortex M3 800 series CPUs. BSP for Stellaris EK-LM3S811 + board including ADC and I2C drivers. + 2010-11-12 John Dallaway <john@dallaway.org.uk> * ecos.db: Add USB mass storage function driver package.
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,6 @@ +* LM3S variant HAL, generic support for the LM3S800 CPUs, and BSP for + Stellaris EK-LM3S811 board including ADC and I2C drivers by Christophe + Coutand * USB mass storage function driver by Christophe Coutand * AT91 USB slave driver halting endpoint support by Christophe Coutand * USB slave device driver for STM32 by Chris Holgate
new file mode 100644 --- /dev/null +++ b/packages/devs/adc/cortexm/lm3s/current/ChangeLog @@ -0,0 +1,31 @@ +2011-01-18 Christophe Coutand <ccoutand@stmi.com> + + * cdl/adc_lm3s.cdl: + * src/adc_lm3s.c: + * include/adc_lm3s.inl: + * tests/lm3s_adc_test.c: + New package -- Stellaris Cortex M3 ADC driver package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/adc/cortexm/lm3s/current/cdl/adc_lm3s.cdl @@ -0,0 +1,217 @@ +# ==================================================================== +# +# adc_lm3s.cdl +# +# eCos Stellaris Cortex M3 ADC configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): ccoutand +# Contributors: +# Date: 2011-01-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ADC_CORTEXM_LM3S { + display "ADC driver for Stellaris Cortex M3 microcontroller family" + + parent CYGPKG_IO_ADC_DEVICES + active_if CYGPKG_IO_ADC_DEVICES + active_if CYGPKG_HAL_CORTEXM_LM3S + include_dir cyg/io + description " + This package provides a generic ADC device driver for the on-chip + ADC peripherals in Stellaris microcontroller." + + compile -library=libextras.a adc_lm3s.c + + define_proc { + puts $::cdl_system_header "#define CYGDAT_DEVS_ADC_CORTEXM_LM3S_INL <cyg/io/adc_lm3s.inl>" + } + + # --------------------------------------------------------------------- + # Primary ADC ( ADC0 ) port + + cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0 { + display "ADC port 0" + flavor bool + default_value 1 + description " + This option includes the device driver for the on-chip ADC0 + of the Stellaris device." + + cdl_interface CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS { + display "Number of ADC0 channels" + } + + cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER { + display "ADC sampling timer" + flavor data + legal_values { 0 1 2 } + default_value 0 + description " + This option selects the timer channel generating the + ADC sampling interval." + } + + cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_INTPRIO { + display "ADC Interrupt priority" + flavor data + default_value 0x60 + description " + This option selects the interrupt priority for the ADC + interrupts." + } + + cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE { + display "Default sample rate" + flavor data + legal_values 1 to 10000 + default_value 100 + description " + The driver will be initialized with the default sample + rate. If you raise the default sample rate you might + need to increase the buffer size for each channel." + } + + cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING { + display "Sample averaging" + flavor data + legal_values { 0 2 4 8 16 32 64 } + default_value 0 + description " + Select the ADC sample averaging." + } + + cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR { + display "Internal Temperature Sensor" + flavor bool + default_value 0 + description " + Enable one ADC channel for internal temperature sensor + reading." + + cdl_option CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR_CHANNEL { + display "Select sensor channel" + flavor data + legal_values { 0 to (CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS-1) } + default_value 1 + description " + This option select ADC channel reserved for + temperature sensor reading." + } + } + + # ----------------------------------------------------------------- + # Support up to 8 ADC channels + + for { set ::channel 0 } { $::channel < 8 } { incr ::channel } { + cdl_component CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel] { + display "Access ADC channel [set ::channel]" + flavor bool + default_value [set ::channel] == 0 + implements CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS + description " + If the application needs to access the on-chip ADC0 + channel [set ::channel] via an eCos ADC driver then + this option should be enabled." + + cdl_option CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel]_NAME { + display "Device name" + flavor data + default_value [format {"\"/dev/adc0%d\""} $::channel] + description " + This option controls the name that an eCos + application should use to access this device + via cyg_io_lookup(), open(), or similar calls." + } + + cdl_option CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL[set ::channel]_BUFSIZE { + display "Size of data buffer" + flavor data + legal_values 0x01 to 0x16 + default_value 0x4 + description " + This option controls the number of samples the + buffer can store. The required RAM depends on the + sample size and on the number of samples. If the + sample size is <= 8 bit the the required RAM = + size of data buffer. If the sample size is 9 or 10 + bit then required RAM = size of data buffer * 2." + } + } + } + } + + cdl_option CYGPKG_DEVS_ADC_CORTEXM_LM3S_DEBUG_LEVEL { + display "Driver debug output level" + flavor data + legal_values { 0 1 } + default_value 0 + description " + This option specifies the level of debug data output by + the Stellaris ADC device driver. A value of 0 signifies no + debug data output; 1 signifies normal debug data output. If + an overrun occurred then this can only be detected by debug + output messages." + } + + cdl_component CYGSEM_DEVS_ADC_CORTEXM_LM3S_SAMPLE_SIZE_LIMIT { + display "Sample size limit" + flavor bool + calculated 1 + requires { ( CYGNUM_IO_ADC_SAMPLE_SIZE == 10 ) } + description " + This component forces a limit (or rounds) the sample size + for Stellaris ADC channels which in the most are 10-bit." + } + + cdl_option CYGPKG_DEVS_ADC_CORTEXM_LM3S_TESTS { + display "Tests for Stellaris 800 Series ADC driver" + flavor data + no_define + active_if CYGPKG_KERNEL + active_if CYGPKG_IO_ADC + calculated { "tests/lm3s_adc_test" } + description " + This option specifies the set of tests for the Stellaris + ADC device driver." + } +} + +# EOF adc_lm3s.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/adc/cortexm/lm3s/current/include/adc_lm3s.inl @@ -0,0 +1,140 @@ +//========================================================================== +// +// adc_lm3s.inl +// +// ADC driver for Stellaris Cortex M3 microcontroller +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// +// Contributors: +// Date: 2011-01-08 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL +#define CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL + +// Declare ADC0 +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0 + +static lm3s_adc_info lm3s_adc0_info = +{ + .timer_base = CYGHWR_HAL_LM3S_GPTIM0 + ( 0x1000 * CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER ), + .adc_intprio = CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_INTPRIO, + .adc_vector = CYGNUM_HAL_INTERRUPT_ADC0_S0, + .adc_base = CYGHWR_HAL_LM3S_ADC0, + .adc_periph = CYGHWR_HAL_LM3S_P_ADC0, + .timer_periph = (CYGHWR_HAL_LM3S_SC_RCGC1_TIMER0 << CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER), +#if CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 0 + .adc_avg = 0, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 2 + .adc_avg = 1, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 4 + .adc_avg = 2, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 8 + .adc_avg = 3, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 16 + .adc_avg = 4, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 32 + .adc_avg = 5, +#elif CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_AVERAGING == 64 + .adc_avg = 6, +#endif +#if defined(CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR) + .sensor_channel = CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_TEMP_SENSOR_CHANNEL, +#else + .sensor_channel = 0xff, +#endif + .max_channel = CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS, + .int_handle = 0, + .chan_mask = 0 +}; + +CYG_ADC_DEVICE( \ + lm3s_adc0_device, \ + &lm3s_adc_funs, \ + &lm3s_adc0_info, \ + CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE); + +#define LM3S_ADC0_CHANNEL( __chan ) \ +CYG_ADC_CHANNEL( \ + lm3s_adc0_channel##__chan, \ + __chan, \ + CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL##__chan##_BUFSIZE, \ + &lm3s_adc0_device ); \ +DEVTAB_ENTRY( \ + lm3s_adc0_channel##__chan##_device, \ + CYGDAT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL##__chan##_NAME, \ + 0, \ + &cyg_io_adc_devio, \ + lm3s_adc_init, \ + lm3s_adc_lookup, \ + &lm3s_adc0_channel##__chan ); + +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL0 +LM3S_ADC0_CHANNEL(0); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL1 +LM3S_ADC0_CHANNEL(1); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL2 +LM3S_ADC0_CHANNEL(2); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL3 +LM3S_ADC0_CHANNEL(3); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL4 +LM3S_ADC0_CHANNEL(4); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL5 +LM3S_ADC0_CHANNEL(5); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL6 +LM3S_ADC0_CHANNEL(6); +#endif +#ifdef CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNEL7 +LM3S_ADC0_CHANNEL(7); +#endif + +#endif // CYGPKG_DEVS_ADC_CORTEXM_LM3S_ADC0 + +#endif // CYGONCE_DEVS_ADC_CORTEXM_LM3S_INL
new file mode 100644 --- /dev/null +++ b/packages/devs/adc/cortexm/lm3s/current/src/adc_lm3s.c @@ -0,0 +1,489 @@ +//========================================================================== +// +// adc_lm3s.c +// +// ADC driver for Stellaris Cortex M3 microcontroller +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler <uwe_kindler@web.de> +// Updated for Stellaris device, ccoutand +// Contributors: +// Date: 2011-01-08 +// Purpose: +// Description: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +//========================================================================== +// INCLUDES +//========================================================================== +#include <pkgconf/system.h> +#include <pkgconf/devs_adc_cortexm_lm3s.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/diag.h> +#include <cyg/io/adc.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/drv_api.h> + +#if CYGPKG_DEVS_ADC_CORTEXM_LM3S_DEBUG_LEVEL > 0 +# define lm3s_adc_diag(args...) diag_printf(args) +#else +# define lm3s_adc_diag(args...) +#endif + +#define CYGHWR_HAL_LM3S_ADC_MAX_CHAN 8 + +//========================================================================== +// DATA TYPES +//========================================================================== +typedef struct lm3s_adc_info { + cyg_uint32 adc_base; // ADC base address + cyg_uint32 adc_periph; // ADC peripheral mask + cyg_vector_t adc_vector; // Interrupt vector number + cyg_priority_t adc_intprio; // Interrupt priority of ADC interrupt + cyg_uint32 timer_base; // Base address of Timer peripheral + cyg_uint32 timer_interval; // Timer value + cyg_uint32 timer_periph; // Timer peripheral mask + cyg_uint8 sensor_channel; // Temperature sensor channel if any + cyg_uint8 max_channel; // Number of ADC channel + cyg_handle_t int_handle; // For initializing the interrupt + cyg_interrupt int_data; + cyg_uint8 adc_avg; // Sample averaging + // Stores references to channel objects + struct cyg_adc_channel *channel[CYGHWR_HAL_LM3S_ADC_MAX_CHAN]; + cyg_uint8 chan_mask; // Mask that indicates channels used + // by ADC driver +} lm3s_adc_info; + + +//========================================================================== +// DECLARATIONS +//========================================================================== +static bool lm3s_adc_init(struct cyg_devtab_entry *tab); +static Cyg_ErrNo lm3s_adc_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static void lm3s_adc_enable(cyg_adc_channel * chan); +static void lm3s_adc_disable(cyg_adc_channel * chan); +static void lm3s_adc_set_rate(cyg_adc_channel * chan, cyg_uint32 rate); +static cyg_uint32 lm3s_adc_isr(cyg_vector_t vector, cyg_addrword_t data); +static void lm3s_adc_dsr(cyg_vector_t vector, + cyg_ucount32 count, cyg_addrword_t data); + +static void lm3s_adc_disable_sequencer0(cyg_uint32); +static void lm3s_adc_enable_sequencer0(cyg_uint32); +static void lm3s_adc_flush(cyg_uint32); +static void lm3s_adc_update_sequencer0(cyg_adc_channel *); + +// ------------------------------------------------------------------------- +// Driver functions: +CYG_ADC_FUNCTIONS( lm3s_adc_funs, + lm3s_adc_enable, + lm3s_adc_disable, + lm3s_adc_set_rate ); + + +#include CYGDAT_DEVS_ADC_CORTEXM_LM3S_INL // Instantiate ADCs + + +//========================================================================== +// +// The eCos Sellaris ADC drivers uses a single sequencer ( sequencer 0 ). +// The same sequencer is used to sample all channels. +// Sampling of the different channel is triggered from a timer interrupt. +// The ADC driver flexibility does not allow to trigger sampling from +// external GPIO or analog comparator event. It should be noted that enabling +// / disabling an ADC channel disturbs the sampling of other channels since it +// requires to stop sampling to re-organize the sequencer. Also the FIFO +// is flushed to ensure correct sample order out of the sequencer FIFO. +// +//========================================================================== +static bool +lm3s_adc_init(struct cyg_devtab_entry *tab) +{ + cyg_adc_channel *chan = (cyg_adc_channel *) tab->priv; + cyg_adc_device *device = chan->device; + lm3s_adc_info *info = device->dev_priv; + + lm3s_adc_diag("ADC: Init\n"); + + if (!info->int_handle) { + lm3s_adc_diag("ADC: IRQ vect %d, pri %d\n", + info->adc_vector, info->adc_intprio); + + cyg_drv_interrupt_create(info->adc_vector, + info->adc_intprio, + (cyg_addrword_t)device, + &lm3s_adc_isr, + &lm3s_adc_dsr, + &(info->int_handle), &(info->int_data)); + cyg_drv_interrupt_attach(info->int_handle); + cyg_drv_interrupt_mask(info->adc_vector); + + // Enable ADC and sampling timer peripheral + CYGHWR_HAL_LM3S_PERIPH_SET(info->adc_periph, 1); + CYGHWR_HAL_LM3S_PERIPH_SET((CYGHWR_HAL_LM3S_PERIPH_GC1 | info-> + timer_periph), 1); + + // Disable timer + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0); + + // Disable / reset sequencer + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_ACTSS, 0); + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_MUX0, 0); + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_CTL0, 0); + + // Trigger sampling from timer + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_EMUX, + CYGHWR_HAL_LM3S_ADC_EMUX_EM_TIMER(0)); + + // Set Averaging + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SAC, + info->adc_avg); + + // Setup timer + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CFG, + CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT); + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_TAMR, + CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC); + + // Setup the default sample rate + lm3s_adc_set_rate(chan, chan->device->config.rate); + + } + + // Initialize generic parts of driver + cyg_adc_device_init(device); + + return true; +} + + +//========================================================================== +// This function is called when a client looks up or opens a channel. It +// should call cyg_adc_channel_init() to initialize the generic part of +// the channel. It should also perform any operations needed to start the +// channel generating samples. +//========================================================================== +static Cyg_ErrNo +lm3s_adc_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, const char *name) +{ + cyg_adc_channel *chan = (cyg_adc_channel *) (*tab)->priv; + lm3s_adc_info *info = chan->device->dev_priv; + + lm3s_adc_diag("ADC: Opening channel %d\n", chan->channel); + + if (chan->channel > info->max_channel) + return ENOENT; + + info->channel[chan->channel] = chan; + + // Initialize generic parts of channel + cyg_adc_channel_init(chan); + + // The generic ADC manual says: When a channel is first looked up or + // opened, then it is automatically enabled and samples start to + // accumulate - so we start the channel now + chan->enabled = true; + lm3s_adc_enable(chan); + + return ENOERR; +} + + +//========================================================================== +// This function is called from the generic ADC package to enable the +// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation. +// It should take any steps needed to start the channel generating samples +//========================================================================== +static void +lm3s_adc_enable(cyg_adc_channel * chan) +{ + lm3s_adc_info *info = chan->device->dev_priv; + cyg_uint32 ctl = + CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN | CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE; + cyg_uint32 start = !info->chan_mask; + + // Disable ADC sequencer 0 and timer + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0); + lm3s_adc_disable_sequencer0(info->adc_base); + + // Update sequencer + info->chan_mask |= (1 << chan->channel); + lm3s_adc_update_sequencer0(chan); + + // Unmask interrupt as soon as 1 channel is enable + if (start) { + cyg_drv_interrupt_unmask(info->adc_vector); + } + // Enable sequencer and timer + lm3s_adc_enable_sequencer0(info->adc_base); + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, ctl); +} + + +//========================================================================== +// This function is called from the generic ADC package to enable the +// channel in response to a CYG_IO_SET_CONFIG_ADC_DISABLE config operation. +// It should take any steps needed to stop the channel generating samples. +//========================================================================== +static void +lm3s_adc_disable(cyg_adc_channel * chan) +{ + lm3s_adc_info *info = chan->device->dev_priv; + cyg_uint32 ctl = + CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN | CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE; + + // Disable ADC sequencer 0 and timer + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0); + lm3s_adc_disable_sequencer0(info->adc_base); + + // Update sequencer + info->chan_mask &= ~(1 << chan->channel); + lm3s_adc_update_sequencer0(chan); + + // Stop scanning when no channel is active + if (!info->chan_mask) { + cyg_drv_interrupt_mask(info->adc_vector); + return; + } + // Enable sequencer and timer + lm3s_adc_enable_sequencer0(info->adc_base); + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_CTL, ctl); +} + + +//========================================================================== +// This function is called from the generic ADC package to enable the +// channel in response to a CYG_IO_SET_CONFIG_ADC_RATE config operation. +// It should take any steps needed to change the sample rate of the channel, +// or of the entire device. +// We use a timer channel to generate the interrupts for sampling the +// analog channels +//========================================================================== +static void +lm3s_adc_set_rate(cyg_adc_channel * chan, cyg_uint32 rate) +{ + cyg_adc_device *device = chan->device; + lm3s_adc_info *info = (lm3s_adc_info *) device->dev_priv; + + info->timer_interval = hal_lm3s_timer_clock() / rate; + + lm3s_adc_diag("ADC: Timer interval %d\n", info->timer_interval); + + HAL_WRITE_UINT32(info->timer_base + CYGHWR_HAL_LM3S_GPTIM_TAILR, + info->timer_interval); +} + + +//========================================================================== +// This function is the ISR attached to the ADC device's interrupt vector. +// It is responsible for reading samples from the channels and passing them +// on to the generic layer. It needs to check each channel for data, and call +// cyg_adc_receive_sample() for each new sample available, and then ready the +// device for the next interrupt. +//========================================================================== +static cyg_uint32 +lm3s_adc_isr(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_adc_device *device = (cyg_adc_device *) data; + lm3s_adc_info *info = (lm3s_adc_info *) device->dev_priv; + cyg_uint32 regval; + cyg_uint32 res = 0; + cyg_adc_sample_t adcdata; + cyg_uint32 sr; + + cyg_uint8 active_channels = info->chan_mask; + cyg_uint8 channel_no = 0; + + while (active_channels) { + HAL_READ_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, sr); + // Check FIFO Full + if ((sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_FULL)) { + lm3s_adc_diag("ADC: FIFO Full\n"); + } + // Check FIFO Empty + if ((sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) { + lm3s_adc_diag("ADC: FIFO Empty\n"); + } + if (active_channels & 0x01) { + // If ADC conversion done, save sample + if (!(sr & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) { + HAL_READ_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0, + regval); + adcdata = regval & 0x3FF; + res |= CYG_ISR_HANDLED + | cyg_adc_receive_sample(info->channel[channel_no], + adcdata); + } + } + active_channels >>= 1; + channel_no++; + } + + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_ISCR, + CYGHWR_HAL_LM3S_ADC_ISCR_IN(0)); + + cyg_drv_interrupt_acknowledge(info->adc_vector); + + return res; +} + + +//========================================================================== +// This function is the DSR attached to the ADC device's interrupt vector. +// It is called by the kernel if the ISR return value contains the +// CYG_ISR_HANDLED bit. It needs to call cyg_adc_wakeup() for each channel +// that has its wakeup field set. +//========================================================================== +static void +lm3s_adc_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + cyg_adc_device *device = (cyg_adc_device *) data; + lm3s_adc_info *info = device->dev_priv; + cyg_uint8 active_channels = info->chan_mask; + cyg_uint8 chan_no = 0; + + while (active_channels) { + if (active_channels & 0x01) { + if (info->channel[chan_no]->wakeup) { + cyg_adc_wakeup(info->channel[chan_no]); + } + } + chan_no++; + active_channels >>= 1; + } +} + + +static void +lm3s_adc_disable_sequencer0(cyg_uint32 base) +{ + cyg_uint32 reg; + + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_IMR, 0); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ISCR, + CYGHWR_HAL_LM3S_ADC_ISCR_IN(0)); + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg); + reg &= ~(CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(0)); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg); +} + + +static void +lm3s_adc_enable_sequencer0(cyg_uint32 base) +{ + cyg_uint32 reg; + + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg); + reg |= (CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(0)); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_ACTSS, reg); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_ADC_IMR, + CYGHWR_HAL_LM3S_ADC_IMR_MASK(0)); +} + + +static void +lm3s_adc_flush(cyg_uint32 base) +{ + volatile cyg_uint32 d; + volatile cyg_uint32 i; + + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, i); + while (!(i & CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY)) { + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0, d); + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR, i); + } +} + + +static void +lm3s_adc_update_sequencer0(cyg_adc_channel * chan) +{ + lm3s_adc_info *info = chan->device->dev_priv; + cyg_uint8 i; + cyg_uint8 cnt = 0; + cyg_uint32 mux = 0; + cyg_uint32 ctl = 0; + + lm3s_adc_diag("ADC: Update sequencer for channel %d\n", chan->channel); + + // Update sequencer + for (i = 0; i < info->max_channel; i++) { + if (!(info->chan_mask & (1 << i))) + continue; + + // Clear and update MUX register + mux &= ~(CYGHWR_HAL_LM3S_ADC_SS_MUX0_M(cnt)); + mux |= CYGHWR_HAL_LM3S_ADC_SS_MUX0_V(i, cnt); + + // Temperature sensor channel + if (i == info->sensor_channel) { + ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS(cnt); + lm3s_adc_diag("ADC: Channel %d mapped to temperature sensor\n", + i); + } + + cnt++; + } + + lm3s_adc_diag("ADC: MUX0 Register: 0x%x\n", mux); + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_MUX0, mux); + + if (info->chan_mask) { + ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_END((cnt - 1)); + ctl |= CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE((cnt - 1)); + } + + lm3s_adc_diag("ADC: CTL0 Register: 0x%x\n", ctl); + HAL_WRITE_UINT32(info->adc_base + CYGHWR_HAL_LM3S_ADC_SS_CTL0, ctl); + + lm3s_adc_flush(info->adc_base); +} + + +//--------------------------------------------------------------------------- +// EOF adc_lm3s.c
new file mode 100644 --- /dev/null +++ b/packages/devs/adc/cortexm/lm3s/current/tests/lm3s_adc_test.c @@ -0,0 +1,256 @@ +//========================================================================== +// +// lm3s_adc_test.c +// +// ADC driver for Stellaris Cortex M3 microcontroller +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Uwe Kindler <uwe_kindler@web.de> +// Updated for Stellaris Cortex microcontroller, ccoutand +// Contributors: +// Date: 2011-01-11 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> + +#include <cyg/infra/testcase.h> // test macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL + +#include <pkgconf/kernel.h> +#include <cyg/io/io.h> +#include <cyg/io/adc.h> +#include <pkgconf/devs_adc_cortexm_lm3s.h> + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + +# include <cyg/kernel/kapi.h> + +# if CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS > 0 + +# define MAX_ADC_CHANNEL_TO_TEST 4 + +//=========================================================================== +// DATA TYPES +//=========================================================================== +typedef struct st_thread_data { + cyg_thread obj; + int stack[(CYGNUM_HAL_STACK_SIZE_MINIMUM / sizeof(int))]; + cyg_handle_t hdl; +} thread_data_t; + + +//=========================================================================== +// LOCAL DATA +//=========================================================================== +cyg_thread_entry_t adc_thread; +thread_data_t adc_thread_data; + + +//=========================================================================== +// ADC THREAD +//=========================================================================== +void +adc_thread(cyg_addrword_t data) +{ + int res; + cyg_io_handle_t handle[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + cyg_uint32 sample_cnt[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + cyg_uint32 cfg_data; + cyg_uint32 len; + cyg_uint32 start_time; + cyg_uint32 end_time; + int i; + cyg_uint8 seconds = 0; + float final_seconds; + cyg_uint32 samples_expected; + + + diag_printf("This test reads samples from all enabled ADC channels.\n" + "Each second the number of already acquired samples\n" + "will be printed. After 10 seconds all ADC channels\n" + "will be stopped and each ADC buffer will be read until\n" + "it is empty. If the number of acquired samples is much\n" + "smaller than the number of expected samples, then you\n" + "should lower the sample rate.\n\n"); + + // Get a handle for ADC device 0 channel 0 - 3 (lookup also trigger a + // channel enable) + res = cyg_io_lookup("/dev/adc00", &handle[0]); + res = cyg_io_lookup("/dev/adc01", &handle[1]); + res = cyg_io_lookup("/dev/adc02", &handle[2]); + res = cyg_io_lookup("/dev/adc03", &handle[3]); + + // Switch all channels to non blocking + for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) { + if (handle[i]) { + cfg_data = 0; + len = sizeof(cfg_data); + res = cyg_io_set_config(handle[i], + CYG_IO_SET_CONFIG_READ_BLOCKING, + &cfg_data, &len); + if (ENOERR != res) { + CYG_TEST_FAIL_FINISH + ("Error switching ADC channel to non blocking"); + } + sample_cnt[i] = 0; + } + } + + start_time = cyg_current_time(); + + do { + for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) { + if (handle[i]) { + cyg_adc_sample_t sample; + + // read a sample from the channel + do { + cyg_uint32 len = sizeof(sample); + res = cyg_io_read(handle[i], &sample, &len); + } + while (-EAGAIN == res); + if (ENOERR == res) { + sample_cnt[i]++; + } + } + } + + end_time = cyg_current_time(); + + // Print number of acquired samples - if one second is expired. + // we expect that the number of acquired samples is nearly the + // sample rate. + if ((end_time - start_time) >= 100) { + start_time = end_time; + diag_printf("%d\t %d\t %d\t %d\n", + sample_cnt[0], + sample_cnt[1], sample_cnt[2], sample_cnt[3]); + seconds++; + } + } while (seconds < 10); + + // Now stop all channels + for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) { + if (handle[i]) { + res = cyg_io_set_config(handle[i], + CYG_IO_SET_CONFIG_ADC_DISABLE, 0, 0); + if (ENOERR != res) { + CYG_TEST_FAIL_FINISH("Error disabling ADC channel"); + } + } + } + + end_time = cyg_current_time(); + end_time = seconds * 1000 + (end_time - start_time) * 10; + final_seconds = end_time / 1000.0; + + // Now read all remaining samples from buffer + for (i = 0; i < MAX_ADC_CHANNEL_TO_TEST; ++i) { + if (handle[i]) { + do { + cyg_adc_sample_t sample; + cyg_uint32 len = sizeof(sample); + res = cyg_io_read(handle[i], &sample, &len); + if (ENOERR == res) { + sample_cnt[i]++; + } + } while (ENOERR == res); + } + } + + diag_printf("\n\n----------------------------------------\n"); + samples_expected = + final_seconds * CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_DEFAULT_RATE; + diag_printf("Samples expected after %d milliseconds: %d\n", end_time, + samples_expected); + diag_printf("Samples read (per channel):\n"); + diag_printf("%d\t %d\t %d\t %d\n", + sample_cnt[0], sample_cnt[1], sample_cnt[2], sample_cnt[3]); + + CYG_TEST_PASS_FINISH("ADC test OK"); +} + + +void +cyg_start(void) +{ + CYG_TEST_INIT(); + + // Create the main ADC test thread + cyg_thread_create(4, + adc_thread, + (cyg_addrword_t)0, + "lm3s_adc_thread", + (void *)adc_thread_data.stack, + CYGNUM_HAL_STACK_SIZE_MINIMUM, + &adc_thread_data.hdl, + &adc_thread_data.obj + ); + + cyg_thread_resume(adc_thread_data.hdl); + + cyg_scheduler_start(); +} +# else// CYGINT_DEVS_ADC_CORTEXM_LM3S_ADC0_CHANNELS > 0 +# define N_A_MSG "Needs at least one enabled ADC channel" +# endif + +#else // CYGFUN_KERNEL_API_C +# define N_A_MSG "Needs kernel C API" +#endif + +#ifdef N_A_MSG +void +cyg_start(void) +{ + CYG_TEST_INIT(); + CYG_TEST_NA(N_A_MSG); +} +#endif // N_A_MSG + + +//--------------------------------------------------------------------------- +// EOF lm3s_adc_test.c
new file mode 100644 --- /dev/null +++ b/packages/devs/i2c/cortexm/lm3s/current/ChangeLog @@ -0,0 +1,30 @@ +2011-01-18 Christophe Coutand <ccoutand@stmi.com> + + * cdl/i2c_lm3s.cdl: + * include/i2c_lm3s.h: + * src/i2c_lm3s.c: + New package -- Stellaris Cortex M3 I2C driver package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/i2c/cortexm/lm3s/current/cdl/i2c_lm3s.cdl @@ -0,0 +1,113 @@ +# ==================================================================== +# +# i2c_lm3s.cdl +# +# eCos Stellaris Cortex M3 I2C configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): ccoutand +# Contributors: +# Date: 2011-01-18 +# +#####DESCRIPTIONEND#### +# ==================================================================== + +cdl_package CYGPKG_DEVS_I2C_CORTEXM_LM3S { + display "I2C driver for Stellaris Cortex M3 microcontroller family" + parent CYGPKG_IO_I2C + active_if CYGPKG_IO_I2C + active_if CYGPKG_HAL_CORTEXM_LM3S + include_dir cyg/io + description " + This package provides a generic I2C device driver for the on-chip + I2C modules in Stellaris Cortex M3 microcontroller." + + compile -library=libextras.a i2c_lm3s.c + + cdl_option CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED { + display "I2C channel clock" + flavor data + default_value { 100000 } + legal_values { 100000 400000 } + description " + Set the I2C clock speed. Slow mode (100KHz) or fast mode + (400KHz)" + } + + cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_TRACE { + display "I2C trace" + flavor bool + default_value 0 + description " + Enable I2C transaction trace. Select to debug the driver." + } + + cdl_component CYGPKG_DEVS_I2C_CORTEXM_LM3S_OPTIONS { + display "I2C driver build options" + flavor none + active_if { CYGINT_DEVS_I2C_CORTEXM_LM3S_BUS_DEVICES > 0 } + description " + Package specific build options including control over + compiler flags used only in building the Stellaris Cortex M3 + I2C bus driver." + + cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Stellaris Cortex M3 I2C bus driver. These + flags are used in addition to the set of global flags." + } + + cdl_option CYGPKG_DEVS_I2C_CORTEXM_LM3S_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Stellaris Cortex M3 I2C bus driver. These + flags are removed from the set of global flags if + present." + } + } +} + +# EOF i2c_lm3s.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/i2c/cortexm/lm3s/current/include/i2c_lm3s.h @@ -0,0 +1,124 @@ +//========================================================================== +// +// i2c_lm3s8xx.h +// +// I2C driver for Stellaris Cortex M3 microcontroller +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-01-18 +// Original: Bart Veer +// I2C driver for motorola coldfire processor +// Description: I2C driver for Stellaris Cortex M3 microcontroller +//####DESCRIPTIONEND#### +//========================================================================== + +#ifndef CYGONCE_I2C_LM3S_H +#define CYGONCE_I2C_LM3S_H + +#include <pkgconf/devs_i2c_cortexm_lm3s.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/drv_api.h> + +typedef enum lm3s_i2c_xfer_mode { + LM3S_I2C_XFER_MODE_INVALID = 0x00, + LM3S_I2C_XFER_MODE_TX = 0x01, + LM3S_I2C_XFER_MODE_RX = 0x02 +} lm3s_i2c_xfer_mode; + +typedef struct lm3s_i2c_extra { + cyg_uint32 i2c_base; // I2C base address + cyg_uint32 i2c_periph; // I2C peripheral bit mask + cyg_uint8 i2c_owner; // We have bus ownership + cyg_uint8 i2c_lost_arb; // Error condition leading to loss of + // bus ownership + cyg_uint8 i2c_send_nack; // As per rx send_nack argument + cyg_uint8 i2c_got_nack; // The last tx resulted in a nack + cyg_uint8 i2c_completed; // Set by DSR, checked by thread + + union { + const cyg_uint8 *i2c_tx_data; + cyg_uint8 *i2c_rx_data; + } i2c_data; // The current buffer for rx or tx + cyg_uint32 i2c_count; // Number of bytes left in buffer + lm3s_i2c_xfer_mode i2c_mode; // TX, RX, ... + + cyg_bool send_stop; + cyg_bool send_start; + cyg_drv_mutex_t i2c_lock; // For synchronizing between DSR and + // foreground + cyg_drv_cond_t i2c_wait; + // For initializing the interrupt + cyg_handle_t i2c_interrupt_handle; + cyg_interrupt i2c_interrupt_data; + cyg_uint32 i2c_isr_id; + cyg_uint32 i2c_isr_pri; +} lm3s_i2c_extra; + +externC void lm3s_i2c_init(struct cyg_i2c_bus *); +externC cyg_uint32 lm3s_i2c_tx(const cyg_i2c_device *, cyg_bool, + const cyg_uint8 *, cyg_uint32, cyg_bool); +externC cyg_uint32 lm3s_i2c_rx(const cyg_i2c_device *, cyg_bool, cyg_uint8 *, + cyg_uint32, cyg_bool, cyg_bool); +externC void lm3s_i2c_stop(const cyg_i2c_device *); + +#define CYG_LM3S_I2C_BUS( \ + _name_, \ + _init_fn_, \ + _base_, \ + _periph_, \ + _isr_vec_, \ + _isr_pri_, \ + _fdr_) \ + static lm3s_i2c_extra _name_ ## _extra = { \ + .i2c_base = _base_, \ + .i2c_periph = _periph_, \ + .i2c_isr_id = _isr_vec_, \ + .i2c_isr_pri= _isr_pri_ \ + }; \ + CYG_I2C_BUS(_name_, \ + _init_fn_, \ + lm3s_i2c_tx, \ + lm3s_i2c_rx, \ + lm3s_i2c_stop, \ + (void*) & ( _name_ ## _extra)) ; + +#endif // CYGONCE_I2C_LM3S_H + +// ------------------------------------------------------------------------- +// EOF i2c_lm3s.h
new file mode 100644 --- /dev/null +++ b/packages/devs/i2c/cortexm/lm3s/current/src/i2c_lm3s.c @@ -0,0 +1,389 @@ +//========================================================================== +// +// i2c_lm3s.c +// +// I2C driver for Stellaris Cortex M3 microcontroller +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-01-18 +// Original: Uwe Kindler, Bart Veer +// I2C driver for motorola coldfire processor +// Description: I2C driver for Stellaris Cortex M3 microcontroller +// The RX part of the driver has not been tested. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/system.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/diag.h> +#include <cyg/io/i2c.h> +#include <cyg/io/i2c_lm3s.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/drv_api.h> + +#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S_TRACE +# define I2C_TRACE(args...) diag_printf(args) +#else +# define I2C_TRACE(args...) +#endif + +#define I2C_DAT(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MDR) +#define I2C_ADR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MSA) +#define I2C_SR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS) +#define I2C_CR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCS) +#define I2C_MCR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR) +#define I2C_MTPR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MTPR) +#define I2C_MCR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MCR) +#define I2C_IMR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MIMR) +#define I2C_ICR(_extra_) (_extra_ + CYGHWR_HAL_LM3S_I2C_MICR) + +#define WAIT_BUS_READY( __sr__, __extra__ ) \ +{ \ + if (!__extra__->i2c_owner) { \ + __extra__->i2c_got_nack = 0; \ + __extra__->i2c_owner = 1; \ + HAL_READ_UINT32(I2C_SR(__extra__->i2c_base), __sr__); \ + while (__sr__ & CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY) { \ + HAL_READ_UINT32(I2C_SR(__extra__->i2c_base),__sr__); \ + } \ + } \ +} + + +static cyg_uint32 +lm3s_i2c_isr(cyg_vector_t vec, cyg_addrword_t data) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data; + cyg_uint32 sr, + dr; + cyg_uint32 result = CYG_ISR_HANDLED; + cyg_uint32 reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN; + cyg_uint8 tx_data = *extra->i2c_data.i2c_tx_data; + + // Read the current status, then clear the interrupt + HAL_READ_UINT32(I2C_SR(extra->i2c_base), sr); + HAL_WRITE_UINT32(I2C_ICR(extra->i2c_base), 1); + + // What to do next depends on the current transfer mode. + if (LM3S_I2C_XFER_MODE_TX == extra->i2c_mode) { + I2C_TRACE("I2C: TX IRQ handling\n"); + if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) { + // Lost the bus, abort the transfer. count has already been + // decremented. Assume the byte did not actually arrive. + extra->i2c_count += 1; + // Arbitration lost, stop + if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ARBLST) { + reg = CYGHWR_HAL_LM3S_I2C_MCS_STOP; + HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg); + } + // This byte has been sent but the device cannot accept + // any more. The nack must be remembered. Otherwise if + // we got a nack for the last byte in a tx then the + // calling code will think the entire tx succeeded, + // and there will be problems if the next call is + // another tx without a repeated start. + if ((sr & CYGHWR_HAL_LM3S_I2C_MCS_ADRACK) | + (sr & CYGHWR_HAL_LM3S_I2C_MCS_DATACK)) { + extra->i2c_got_nack = 1; + } + result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; + I2C_TRACE("I2C TX, bus arbitration error\n"); + } else if (0 == extra->i2c_count) { + // No more bytes to send. + result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; + } else { + // Send byte + HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)tx_data); + extra->i2c_data.i2c_tx_data += 1; + extra->i2c_count -= 1; + // Last byte + if ((0 == extra->i2c_count) && extra->send_stop) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP; + } + HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg); + } + } else if (LM3S_I2C_XFER_MODE_RX == extra->i2c_mode) { + I2C_TRACE("I2C: RX IRQ handling\n"); + if (sr & CYGHWR_HAL_LM3S_I2C_MCS_ERR) { + // Lost the bus? Maybe a spurious stop + result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; + } else { + if (2 == extra->i2c_count) { + // Received one, one more to go, + // and that one should be nacked. + if (!extra->i2c_send_nack) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK; + } + if (extra->send_stop) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP; + } + HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg); + } else if (1 == extra->i2c_count) { + // Received the last byte. + result = CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; + } + HAL_READ_UINT32(I2C_DAT(extra->i2c_base), dr); + *(extra->i2c_data.i2c_rx_data) = (cyg_uint8)dr; + extra->i2c_data.i2c_rx_data += 1; + extra->i2c_count -= 1; + } + } else { + // Invalid state? Some kind of spurious interrupt? + // Just ignore it. + I2C_TRACE("I2C spurious interrupt\n"); + } + + HAL_INTERRUPT_ACKNOWLEDGE(extra->i2c_isr_id); + + return result; +} + + +static void +lm3s_i2c_dsr(cyg_vector_t vec, cyg_ucount32 count, cyg_addrword_t data) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) data; + extra->i2c_completed = 1; + cyg_drv_cond_signal(&(extra->i2c_wait)); +} + + +// A transfer has been started. Wait for completion +static inline void +lm3s_i2c_doit(lm3s_i2c_extra * extra) +{ + cyg_drv_mutex_lock(&(extra->i2c_lock)); + cyg_drv_dsr_lock(); + while (!extra->i2c_completed) { + cyg_drv_cond_wait(&(extra->i2c_wait)); + } + cyg_drv_dsr_unlock(); + cyg_drv_mutex_unlock(&(extra->i2c_lock)); +} + + +static inline void +lm3s_i2c_stopit(lm3s_i2c_extra * extra) +{ + extra->i2c_lost_arb = 0; + extra->i2c_owner = 0; + extra->i2c_mode = LM3S_I2C_XFER_MODE_INVALID; +} + + +void +lm3s_i2c_stop(const cyg_i2c_device * dev) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra; + lm3s_i2c_stopit(extra); +} + + +static cyg_bool +lm3s_i2c_handle_xfer(lm3s_i2c_extra * extra, int address) +{ + cyg_uint32 sr; + cyg_uint8 data = *extra->i2c_data.i2c_tx_data; + cyg_uint32 reg = CYGHWR_HAL_LM3S_I2C_MCS_RUN; + + // Nothing to send or receive + if (extra->i2c_count == 0) + return 0; + + // Take the bus ownership + WAIT_BUS_READY(sr, extra); + + // This can be a start or repeated start + if (extra->send_start) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_START; + HAL_WRITE_UINT32(I2C_ADR(extra->i2c_base), address); + } + // TX transfer + if (extra->i2c_mode == LM3S_I2C_XFER_MODE_TX) { + extra->i2c_data.i2c_tx_data += 1; + extra->i2c_count -= 1; + HAL_WRITE_UINT32(I2C_DAT(extra->i2c_base), (cyg_uint32)data); + + // Single byte transfer + if (extra->send_stop && (extra->i2c_count == 0)) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP; + } + } else { + // Single byte transfer, set the STOP bit + if (extra->send_stop && (extra->i2c_count == 1)) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_STOP; + } + // Do not ACK last byte per user request + if (!extra->i2c_send_nack || !(extra->i2c_count == 1)) { + reg |= CYGHWR_HAL_LM3S_I2C_MCS_ACK; + } + } + + HAL_WRITE_UINT32(I2C_CR(extra->i2c_base), reg); + + return 1; +} + + +cyg_uint32 +lm3s_i2c_tx(const cyg_i2c_device * dev, cyg_bool send_start, + const cyg_uint8 *tx_data, cyg_uint32 count, cyg_bool send_stop) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra; + extra->send_stop = send_stop; + extra->send_start = send_start; + extra->i2c_count = count; + + if (!extra->i2c_lost_arb) { + extra->i2c_completed = 0; + extra->i2c_mode = LM3S_I2C_XFER_MODE_TX; + + if (send_start || !extra->i2c_got_nack) { + I2C_TRACE + ("I2C: TX to %2x, data %2x, count: %4d, START flag: %s\n", + dev->i2c_address, *tx_data, count, + (send_start == true) ? "true" : "false"); + extra->i2c_data.i2c_tx_data = tx_data; + if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x00)) { + return 0; + } + lm3s_i2c_doit(extra); + } + + } + if (send_stop) { + I2C_TRACE("I2C: TX send stop\n"); + lm3s_i2c_stopit(extra); + } + + I2C_TRACE("I2C: TX count %d\n", extra->i2c_count); + + // tx() should return the number of bytes actually transmitted. + // ISR() increments extra->count after a failure, which leads to + // an edge condition when send_start and there is no acknowledgment + // of the address byte. + if (extra->i2c_count > count) { + return 0; + } + + return count - extra->i2c_count; +} + + +cyg_uint32 +lm3s_i2c_rx(const cyg_i2c_device * dev, cyg_bool send_start, + cyg_uint8 *rx_data, cyg_uint32 count, cyg_bool send_nack, + cyg_bool send_stop) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) dev->i2c_bus->i2c_extra; + extra->i2c_count = count; + extra->i2c_send_nack = send_nack; + extra->send_stop = send_stop; + extra->send_start = send_start; + + if (!extra->i2c_lost_arb) { + extra->i2c_completed = 0; + extra->i2c_data.i2c_rx_data = rx_data; + extra->i2c_mode = LM3S_I2C_XFER_MODE_RX; + I2C_TRACE("I2C: RX to %2x, count: %4d, START flag: %s\n", + dev->i2c_address, count, + (send_start == true) ? "true" : "false"); + if (!lm3s_i2c_handle_xfer(extra, (dev->i2c_address << 1) | 0x01)) { + return 0; + } + lm3s_i2c_doit(extra); + } + + if (send_stop) { + I2C_TRACE("I2C: RX send stop\n"); + lm3s_i2c_stopit(extra); + } + + return count - extra->i2c_count; +} + + +// ---------------------------------------------------------------------------- +// The functions needed for all I2C devices. + +void +lm3s_i2c_init(struct cyg_i2c_bus *bus) +{ + lm3s_i2c_extra *extra = (lm3s_i2c_extra *) bus->i2c_extra; + cyg_uint32 tpr = + ((hal_lm3s_i2c_clock() / + (20 * CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED)) - 1); + + I2C_TRACE("I2C INIT, TPR register: %d\n", tpr); + + cyg_drv_mutex_init(&extra->i2c_lock); + cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock); + cyg_drv_interrupt_create(extra->i2c_isr_id, + extra->i2c_isr_pri, + (cyg_addrword_t)extra, + &lm3s_i2c_isr, + &lm3s_i2c_dsr, + &(extra->i2c_interrupt_handle), + &(extra->i2c_interrupt_data)); + cyg_drv_interrupt_attach(extra->i2c_interrupt_handle); + + // Enable I2C peripheral, it is left to the variant/platform HAL to + // configure the SDA and SCL IOs. + CYGHWR_HAL_LM3S_PERIPH_SET(extra->i2c_periph, 1); + + // Enable Master mode + HAL_WRITE_UINT32(I2C_MCR(extra->i2c_base), CYGHWR_HAL_LM3S_I2C_MCR_MFE); + + // Set I2C bus speed + HAL_WRITE_UINT32(I2C_MTPR(extra->i2c_base), tpr); + + // Enable Interrupt + HAL_WRITE_UINT32(I2C_IMR(extra->i2c_base), 1); + + // Interrupts can now be safely unmasked + HAL_INTERRUPT_UNMASK(extra->i2c_isr_id); +} + +//--------------------------------------------------------------------------- +// EOF i2c_lm3s.c
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -2419,6 +2419,16 @@ package CYGPKG_DEVS_I2C_ARM_LPC2XXX { controller family." } +package CYGPKG_DEVS_I2C_CORTEXM_LM3S { + alias { "Stellaris Cortex-M3 I2C driver" lm3s_i2c lm3s_i2c_driver i2c_lm3s} + hardware + directory devs/i2c/cortexm/lm3s + script i2c_lm3s.cdl + description " + This package provides a driver for the I2C unit of the Stellaris + Cortex-M3 controller family." +} + package CYGPKG_DEVS_ADC_ARM_LPC24XX { alias { "LPC24xx ADC driver" } hardware @@ -2439,6 +2449,16 @@ package CYGPKG_DEVS_ADC_ARM_AT91 { ADC provided by the Atmel AT91 processor family." } +package CYGPKG_DEVS_ADC_CORTEXM_LM3S { + alias { "Stellaris Cortex M3 ADC driver" lm3s_adc } + hardware + directory devs/adc/cortexm/lm3s + script adc_lm3s.cdl + description " + This packages provides an ADC driver for the on-chip ADC provided + by the Stellaris Cortex M3 controller family." +} + package CYGPKG_DEVS_ADC_SYNTH { alias { "Synthethic ADC driver" adc_synth } hardware @@ -6843,6 +6863,38 @@ package CYGPKG_HAL_CORTEXM { variant and platform HAL packages." } +package CYGPKG_HAL_CORTEXM_LM3S { + alias { "Stellaris Cortex M3 variant HAL" hal_cortexm_lm3s } + directory hal/cortexm/lm3s/var + script hal_cortexm_lm3s.cdl + hardware + description " + The Stellaris Cortex M3 HAL package provides the support needed + to run eCos on targets based on the Stellaris Cortex M3 family + of microcontrollers." +} + +package CYGPKG_HAL_CORTEXM_LM3S8XX { + alias { "Stellaris 800 Series variant HAL" hal_cortexm_lm3s8xx } + directory hal/cortexm/lm3s/lm3s8xx/ + script hal_cortexm_lm3s8xx.cdl + hardware + description " + The Stellaris Cortex M3 800 Series HAL package provides the + support needed to run eCos on targets based on the Stellaris + Luminary Micro 800 Series family of microcontrollers." +} + +package CYGPKG_HAL_CORTEXM_EK_LM3S811 { + alias { "Stellaris EK-LM3S811 HAL" hal_cortexm_ek_lm3s811 } + directory hal/cortexm/lm3s/ek_lm3s811 + script hal_cortexm_ek_lm3s811.cdl + hardware + description " + The ek-lm3s811 HAL package provides the support needed to run + eCos on the Stellaris EK-LM3S811 board from Luminary Micro." +} + package CYGPKG_HAL_CORTEXM_STM32 { alias { "ST STM32 variant HAL" hal_cortexm_stm32 } directory hal/cortexm/stm32/var @@ -6941,5 +6993,21 @@ target stm3210e_eval { to run eCos on the STM3210E EVAL board." } +target ek-lm3s811 { + alias { " Stellaris EK-LM3S811 board" ek-lm3s811 } + packages { CYGPKG_HAL_CORTEXM + CYGPKG_HAL_CORTEXM_LM3S + CYGPKG_HAL_CORTEXM_LM3S8XX + CYGPKG_HAL_CORTEXM_EK_LM3S811 + CYGPKG_DEVS_I2C_CORTEXM_LM3S + CYGPKG_DEVS_ADC_CORTEXM_LM3S + CYGPKG_IO_I2C + CYGPKG_IO_ADC + } + description " + EK-LM3S811 target provides the packages needed to run eCos + on the Stellaris EK-LM3S811 board from Luminary Micro." +} + # ========================================================================== # End of ecos.db
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog @@ -0,0 +1,31 @@ +2011-01-18 Christophe Coutand <ccoutand@stmi.com> + + * cdl/hal_cortexm_ek_lm3s811.cdl: + * doc/ek_lm3s811.sgml: + * src/ek_lm3s811_misc.c: + * src/platform_i2c.c: + New package -- Stellaris Cortex-M3 EK-LM3S811 platform HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl @@ -0,0 +1,78 @@ +# ==================================================================== +## +## hal_cortexm_ek_lm3s811.cdl +## +## Stellaris Cortex-M3 EK-LM3S811 board platform HAL +## +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): ccoutand +# Contributors: +# Date: 2011-01-18 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_EK_LM3S811 { + display "Stellaris EK-LM3S811 Development Board HAL" + doc ref/hal-cortexm-lm3s-ek_lm3s811.html + parent CYGPKG_HAL_CORTEXM_LM3S8XX + define_header hal_cortexm_ek_lm3s811.h + include_dir cyg/hal + hardware + + description " + The EK-LM3S811 HAL package provides the support needed to run + eCos on the Stellaris EK-LM3S811 EVAL board." + + compile ek_lm3s811_misc.c platform_i2c.c + + requires { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" } + requires { CYGHWR_HAL_CORTEXM_LM3S8XX == "LM3S811" } + requires { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ == 6000000 } + requires { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT == 1 } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_ek_lm3s811.h>" + puts $::cdl_header "#include <pkgconf/hal_cortexm_lm3s8xx.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M3 - LM3S811\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Stellaris EK-LM3S811\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } +} + +# EOF hal_cortexm_ek_lm3s811.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml @@ -0,0 +1,140 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- ek_lm3s811.sgml --> +<!-- --> +<!-- ek_lm3s811 board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2011 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): ccoutand --> +<!-- Contact(s): ccoutand --> +<!-- Date: 2011/01/18 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-cortexm-lm3s-ek_lm3s811"><title>Stellaris EKK-LM3S811 Board Support</title> + +<refentry id="lm3s-ek_lm3s811"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>eCos Support for the Stellaris EKK-LM3S811 Board</refname> + <refpurpose>Overview</refpurpose> + </refnamediv> + + <refsect1 id="lm3s-ek_lm3s811-description"><title>Description</title> + <para> +The Stellaris EKK-LM3S811 evaluation kit uses the Stellaris LM3S811 microcontroller from the +800 Series. The LM3S811 is an ARM cortex-M3 based microcontroller with 64KB of FLASH +and 8KB of SRAM. The device has various peripherals such as UART, I2C, ADC or Analog +Comparator. The kit features an OLED graphical display and UART0 is accessible via the +on-board USB to UART converter. + </para> + <para> +Due to extreme limited RAM ressources (8KB SRAM only), the eCos port targets standalone ROM +application using the eCos kernel in single user thread environment. The cortex-M architecture HAL +requires a seperate stack to handle interrupts, thus the minimum kernel enable application requires 3 +stacks. The interrupt stack, the Idle thread stack and the user stack. All stacks are set to the architecture +minimum allowed size of CYGNUM_HAL_STACK_SIZE_MINIMUM ( 1360 bytes ). + </para> + </refsect1> + + <refsect1 id="lm3s-ek_lm3s811-config"><title>Configuration</title> + <para> +The minimum board configuration includes the Microcontroller HAL alongs with the ADC and I2C device +drivers. + </para> + <variablelist> + <varlistentry> + <term><varname>LM3S811 Microcontroller</varname></term> + <listitem> + <para> +CYGPKG_HAL_CORTEXM_LM3S8XX - The microcontroller configuration +requirements are minimal. With the default setup, the microcontroller runs from the +external clock source, a crystal of 6MHz. The chip internal PLL generates a fix +200MHz clock that is divided down to the default system clock frequency of 50MHz. +In this scenario, the device uses full processing power. The system clock divider +allows down scaling of the system clock frequency to reduce the overall power +consumption of the device. The microcontroller also offers the option to run from an +internal oscillator. This option has 2 modes, 3MHz or 12MHz. When selecting the +internal oscillator, the PLL is bypassed. The system clock frequency becomes at +best 12MHz if no further clock division is applied. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term><varname>I2C Interface</varname></term> + <listitem><para> +CYGPKG_DEVS_I2C_CORTEXM_LM3S - The microcontroller uses the I2C bus +to communicate with the SD1300 controller of the OLED 96 x 16 display. The SD1300 +controller eCos driver is not currently available. +The I2C is default set to use the low frequency mode ( 100KHz bus clock ). The high +frequency mode ( 400 KHz ) is available by changing CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>ADC Interface</varname></term> + <listitem><para> +CYGPKG_DEVS_ADC_CORTEXM_LM3S - The LM3S811 includes 4 ADC channels including an +optional internal temperature probe. There are many ways to use the on-chip ADC. +The current eCos driver uses a single sequencer (sequencer 0) to schedule sampling of all +channels. This practically means that all channels are sampled from the same trigger, a periodic timer +interrupt in the current driver. The timer to use +is selected from CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER, with timer 0 as +default value. The timer is used in 32 bits periodic mode, therefore cannot be re-used +for any other user purpose. While the ADC has the possibility to trigger sampling on external +IO events, the driver does not offer that flexibility. Finally, the driver only allows measurement of +single-ended IOs. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="lm3s-ek_lm3s811-rebuild"><title>Build ROM type applications</title> + <para> +The steps needed to build the HAL library for the EKK-LM3S811 board are: + </para> + <screen> +$ mkdir ek_lm3s811 +$ cd ek_lm3s811 +$ ecosconfig new ek-lm3s811 minimal +$ ecosconfig import $ECOS_REPOSITORY/hal/cortexm/lm3s/ek_lm3s811/current/misc/default_ROM.ecm +$ ecosconfig resolve +$ ecosconfig tree +$ make + </screen> + <para> +At the end of the build the <filename +class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename +class="directory">install/include</filename> subdirectory the necessary includes to compile the application. + </para> + </refsect1> + + +</refentry> + +</part>
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c @@ -0,0 +1,163 @@ +//========================================================================== +// +// ek_lm3s811_misc.c +// +// Cortex-M3 Stellaris EK-LM3S811 HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Original for STM3210E EVAL: nickg +// Updated for EK-LM3S811: ccoutand +// Date: 2011-01-18 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + + +// On-board status LED +#define CYGHWR_HAL_EK_LM3S811_STATUS_LED \ + CYGHWR_HAL_LM3S_GPIO( C, 5, OUT, 4_MA, PULLUP, DISABLE ) + +// OLED regulator control +#define CYGHWR_HAL_EK_LM3S811_OLED_PWD \ + CYGHWR_HAL_LM3S_GPIO( D, 7, OUT, NONE, NONE, DISABLE ) + + +//========================================================================== +// Drive OLED power ON/OFF IO + +__externC void +hal_ek_lm3s811_oled_pwd( bool pwd ) +{ + cyg_uint32 oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD; + + // Power ON regulator + if ( pwd == true ) + CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 1 ); + else + CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 0 ); +} + + +//========================================================================== +// Setup platform + +__externC void +hal_platform_init( void ) +{ + cyg_uint32 led_io = CYGHWR_HAL_EK_LM3S811_STATUS_LED; + cyg_uint32 oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD; + + // OLED power switch IO is on port D and user LED on port C + CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOC, 1 ); + CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOD, 1 ); + CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_I2C0, 0 ); + + // Status LED -> ON + CYGHWR_HAL_LM3S_GPIO_SET( led_io ); + CYGHWR_HAL_LM3S_GPIO_OUT( led_io, 1 ); + + // Shutdown power regulator + CYGHWR_HAL_LM3S_GPIO_SET( oled_pwd_io ); + + hal_ek_lm3s811_oled_pwd( false ); +} + + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = { +#ifdef CYGMEM_REGION_sram // On-chip SRAM + { + CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1}, +#endif +#ifdef CYGMEM_REGION_flash // On-chip flash + { + CYGMEM_REGION_flash, + CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1}, +#endif + { + 0xE0000000, 0x00000000 - 1}, // Cortex-M peripherals + { + 0x40000000, 0x50000000 - 1}, // Stellaris peripherals +}; + +__externC int +cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof( hal_data_access ) / sizeof( hal_data_access[0] ); + i++ ) { + if( ( addr >= hal_data_access[i].start ) + && ( addr + count ) <= hal_data_access[i].end ) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + +//========================================================================== +// EOF ek_lm3s811_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c @@ -0,0 +1,178 @@ +//========================================================================== +// +// platform_i2c.c +// +// Optional I2C support for Cortex-M3 Stellaris EK-LM3S811 +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-01-18 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +//============================================================================= +// INCLUDES +//============================================================================= +#include <pkgconf/system.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_endian.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S + +#include <cyg/io/i2c.h> +#include <cyg/io/i2c_lm3s.h> + +//============================================================================= +// Setup I2C bus 0 +// +static void +lm3s8xx_i2c0_init( struct cyg_i2c_bus *bus ) +{ + cyg_uint32 scl_io = CYGHWR_HAL_LM3S_I2C_SCL; + cyg_uint32 sda_io = CYGHWR_HAL_LM3S_I2C_SDA; + + // + // We only need to setup the pins here and + // leave the I2C driver to take care of the rest. + // + CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOB, 1 ); + CYGHWR_HAL_LM3S_GPIO_SET( scl_io ); + CYGHWR_HAL_LM3S_GPIO_SET( sda_io ); + lm3s_i2c_init( bus ); +} + + +//----------------------------------------------------------------------------- +// I2C bus 0 +// +CYG_LM3S_I2C_BUS(hal_lm3s8xx_i2c0_bus, + &lm3s8xx_i2c0_init, + CYGHWR_HAL_LM3S_I2C_M0, + CYGHWR_HAL_LM3S_P_I2C0, + CYGNUM_HAL_INTERRUPT_I2C, + 0x60, + 10); + + +//----------------------------------------------------------------------------- +// OLED +// +CYG_I2C_DEVICE(i2c_lm3s8xx_oled, + &hal_lm3s8xx_i2c0_bus, + 0x3d, + 0, + CYG_I2C_DEFAULT_DELAY); + + +#define DELAY 1 + +// Wrapper to TI OLED driver + +externC cyg_uint32 +lm3s8xx_oled_write_first( cyg_uint8 byte ) +{ + cyg_uint32 result; + + cyg_i2c_transaction_begin( &i2c_lm3s8xx_oled ); + + result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled, + true, ( cyg_uint8 * )&byte, 1, false ); + +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + return result; +} + +externC cyg_uint32 +lm3s8xx_oled_write_byte( cyg_uint8 byte ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled, + false, ( cyg_uint8 * )&byte, 1, false ); + +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + return result; +} + + +externC cyg_uint32 +lm3s8xx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled, + false, array, count, false ); + + return result; +} + + +externC cyg_uint32 +lm3s8xx_oled_write_final( cyg_uint8 byte ) +{ + cyg_uint32 result; + + result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled, + false, ( cyg_uint8 * )&byte, 1, true ); +#ifdef CYGPKG_KERNEL + cyg_thread_delay( DELAY ); +#endif + + cyg_i2c_transaction_end( &i2c_lm3s8xx_oled ); + + return result; +} + +#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S + +//----------------------------------------------------------------------------- +// EOF platform_i2c.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog @@ -0,0 +1,37 @@ +2011-01-18 Christophe Coutand <ccoutand@stmi.com> + + * cdl/hal_cortexm_lm3s8xx.cdl: + * include/pkgconf/mlt_cortexm_ek_lm3s811_rom.h: + * include/pkgconf/mlt_cortexm_ek_lm3s811_rom.ldi: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * misc/default_ROM.ecm: + * src/lm3s8xx_misc.c: + * tests/timers.c: + New package -- Stellaris Cortex M3 800 Series HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl @@ -0,0 +1,390 @@ +##========================================================================== +## +## hal_cortexm_lm8xx.cdl +## +## Stellaris Cortex-M3 800 Series variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): ccoutand +## Date: 2011-01-18 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_LM3S8XX { + display "Stellaris Cortex-M3 800 Series" + parent CYGPKG_HAL_CORTEXM + include_dir cyg/hal + define_header hal_cortexm_lm3s8xx.h + hardware + description " + This package provides generic support for the Cortex-M3 based + Stellaris LM 800 Series microcontroller family. It is also + necessary to select a variant and platform HAL package." + + compile lm3s8xx_misc.c + + implements CYGINT_DEVS_I2C_LM3S8XX_BUS_DEVICES + + requires { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_lm3s.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H" + } + + cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX { + display "Stellaris LM 800 Series variant in use" + flavor data + default_value { "LM3S811" } + legal_values { "LM3S828" "LM3S818" "LM3S817" + "LM3S815" "LM3S812" "LM3S811" + "LM3S808" "LM3S801" "LM3S800" } + description " + The Stellaris 800 Series has several variants, the main + difference being the numbers of some peripherals" + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + } + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value { "ROM" } + legal_values { "ROM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + With its 8KB of SRAM, the 800 Series devices only allows + ROM startup." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "ROM") ? \ + "cortexm_lm3s8xx_rom" : "undefined" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + } + + cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK { + display "Clocking" + flavor none + requires { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT || \ + CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT } + + cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT { + display "External clock source" + active_if ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT + flavor bool + default_value 1 + + cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ { + display "Crystal frequency in Hz" + flavor data + default_value 8000000 + legal_values { 1000000 to 8192000 } + description " + Select the external crystal frequency from 1 to + 8.192 MHz. Selecting the internal PLL adds additional + constraints to the external crystal frequency setting. + Check-out CYGHWR_HAL_CORTEXM_LM3S8XX_PLL" + } + } + + cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT { + display "Internal clock source" + active_if ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT + flavor bool + default_value 0 + + cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ { + display "Internal clock source frequency in Hz" + flavor data + default_value 12000000 + legal_values { 12000000 3000000 } + description " + Select the internal clock source. The frequency of the + internal clock source can either be 12MHz or 3MHz." + } + } + + cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_PLL { + display "Enable PLL" + flavor bool + default_value 1 + active_if CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT + + cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT { + display "PLL input clock frequency" + flavor data + calculated { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ } + legal_values { 3579545 3686400 4000000 4096000 4915200 5000000 \ + 5120000 6000000 6144000 7372800 8000000 8192000 } + description " + PLL output frequency is fixed to 200 MHz. Using the + PLL puts more constraints to the external reference + clock. The PLL input clock frequency is not defined + if internal chip reference clock is used." + } + } + + cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK { + display "System Clock frequency" + flavor data + calculated { CYGHWR_HAL_CORTEXM_LM3S8XX_PLL ? ( 200000000 / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT ? ( CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : ( CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) } + legal_values { 1000000 to 50000000 } + description " + The chip system clock frequency is 200 MHz divided + by the system clock divider when the PLL is in used, + otherwise the frequency value is the chip source clock + frequency divided by the system clock divider." + } + + cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV { + display "System Clock divider" + flavor data + default_value 4 + legal_values { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 } + description " + Select the system clock divider." + } + } + + # UART0 is available for diagnostic/debug use. + implements CYGINT_HAL_CORTEXM_LM3S_UART0 + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + This option selects which port will be used to connect to + a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + This option selects which port will be used for diagnostic + output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. Note: this should match the value chosen + for the GDB port if the diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the GDB + connection. Note: this should match the value chosen for + the console port if the console and GDB port are the same." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over compiler flags, + linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which + are used to compile all packages by default. Individual + packages may define options which override these global + flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global + flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a + ROM monitor, i.e. applications will be loaded into RAM on + the board, and this ROM monitor may process exceptions or + interrupts generated from the application. This enables + features such as utilizing a separate interrupt stack when + exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM + monitor. This support changes various eCos semantics such + as the encoding of diagnostic output, or the overriding of + hardware interrupt vectors. + Firstly there is \"Generic\" support which prevents the + HAL from overriding the hardware vectors that it does not + use, to instead allow an installed ROM monitor to handle + them. This is the most basic support which is likely to be + common to most implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included + in the ROM monitor or boot ROM." + } + + cdl_component CYGBLD_HAL_CORTEXM_LM3S8XX_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + description " + This component causes the ELF image generated by the build + process to be converted to S-Record and binary files." + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + + cdl_option CYGPKG_HAL_CORTEXM_LM3S8XX_TESTS { + display "Stellaris Cortex-M3 800 Series tests" + active_if CYGPKG_KERNEL + flavor data + no_define + calculated { "tests/timers" } + description " + This option specifies the set of tests for the Stellaris + Cortex-M3 800 Series HAL." + } +} + +# EOF hal_cortex_lm3s8xx.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h @@ -0,0 +1,19 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (0x00010000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram_SIZE (0x00000000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi @@ -0,0 +1,34 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = 0x00010000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000400, FOLLOWING (.got)) + SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram)) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + 1024*8; +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Stellaris Cortex-M3 800 Series specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_lm3s8xx.h> + + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_ARCH_H +// EOF plf_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Stellaris Cortex-M3 800 Series specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_lm3s8xx.h> + +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_FMS) + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_INTR_H +// EOF plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h @@ -0,0 +1,153 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Stellaris Cortex-M3 800 Series specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include <pkgconf/hal_cortexm_lm3s8xx.h> + +// Number of IOs on port A / B and C +#define CYGHWR_HAL_LM3S_GPIOA_IOs 6 +#define CYGHWR_HAL_LM3S_GPIOB_IOs 8 +#define CYGHWR_HAL_LM3S_GPIOC_IOs 8 + +// Number of IOs on port D and E varies +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) +#define CYGHWR_HAL_LM3S_GPIOD_IOs 8 +#define CYGHWR_HAL_LM3S_GPIOE_IOs 6 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828) +#define CYGHWR_HAL_LM3S_GPIOD_IOs 4 +#define CYGHWR_HAL_LM3S_GPIOE_IOs 2 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) +#define CYGHWR_HAL_LM3S_GPIOD_IOs 8 +#define CYGHWR_HAL_LM3S_GPIOE_IOs 2 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) +#define CYGHWR_HAL_LM3S_GPIOD_IOs 8 +#define CYGHWR_HAL_LM3S_GPIOE_IOs 4 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817)|| \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818) +#define CYGHWR_HAL_LM3S_GPIOD_IOs 6 +#define CYGHWR_HAL_LM3S_GPIOE_IOs 2 +#endif + +// UART1 +#define CYGHWR_HAL_LM3S_UART1_TX CYGHWR_HAL_LM3S_GPIO( D, 2, PERIPH, NONE, NONE, DISABLE ) +#define CYGHWR_HAL_LM3S_UART1_RX CYGHWR_HAL_LM3S_GPIO( D, 3, PERIPH, NONE, NONE, DISABLE ) +#define CYGHWR_HAL_LM3S_P_UART1_GPIO CYGHWR_HAL_LM3S_P_GPIOD + +// Number of ADC channel +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) +#define CYGHWR_HAL_LM3S_ADC0_CHAN 2 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) +#define CYGHWR_HAL_LM3S_ADC0_CHAN 4 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818) +#define CYGHWR_HAL_LM3S_ADC0_CHAN 6 +#elif defined(CYGHWR_HAL_CORTEXM_CORTEXM_LM3S828) || \ + defined(CYGHWR_HAL_CORTEXM_CORTEXM_LM3S808) +#define CYGHWR_HAL_LM3S_ADC0_CHAN 8 +#endif + +// Number of PWM channel +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) +#define CYGHWR_HAL_LM3S_MAX_PWM_CHAN 2 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818) +#define CYGHWR_HAL_LM3S_PWM_CHAN 6 +#endif + +// Number of I2C channels +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828) +#define CYGHWR_HAL_LM3S_I2C_CHAN 1 +// I2C +#define CYGHWR_HAL_LM3S_I2C_SCL CYGHWR_HAL_LM3S_GPIO( B, 3, PERIPH, 2_MA, OP_PULLUP, DISABLE ) +#define CYGHWR_HAL_LM3S_I2C_SDA CYGHWR_HAL_LM3S_GPIO( B, 2, PERIPH, 2_MA, OP_PULLUP, DISABLE ) +#endif + +// Number of analog Comparator +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) +#define CYGHWR_HAL_LM3S_AC_CHAN 3 +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818) +#define CYGHWR_HAL_LM3S_AC_CHAN 1 +#endif + +// Number of Quadrature Encoder Channel +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \ + defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818) +#define CYGHWR_HAL_LM3S_QEI_CHAN 1 +#endif + +// SSI channel +#define CYGHWR_HAL_LM3S_SSI_CHAN 1 + +// Global timer channel +#define CYGHWR_HAL_LM3S_GPTIM_CHAN 3 + +//----------------------------------------------------------------------------- +#endif //CYGONCE_HAL_PLF_IO_H +// EOF plf_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm @@ -0,0 +1,22 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template minimal ; + package CYGPKG_KERNEL current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 1536 +}; + +cdl_option CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE { + user_value 1536 +}; \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c @@ -0,0 +1,246 @@ +//========================================================================== +// +// lm3s8xx_misc.c +// +// Stellaris Cortex-M3 800 Series HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2010-11-21 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header +#include <cyg/hal/var_io.h> + +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL) +#if CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3579545 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(4) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3686400 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(5) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4000000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(6) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4096000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(7) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4915200 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(8) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5000000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(9) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5120000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(10) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6000000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(11) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6144000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(12) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 7372800 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(13) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8000000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(14) +#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8192000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(15) +#endif +#endif + +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT) +#if CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ == 12000000 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC +#else +#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4 +#endif +#else +#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC +#endif + +#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1 +#define CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL \ + CYGHWR_HAL_LM3S_SC_RCC_SYSDIV( (CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV-1) ); +#endif + +//========================================================================== + +void hal_lm3s8xx_periph_set( cyg_uint32 periph, cyg_uint32 on_off ); + +__externC cyg_uint32 hal_cortexm_systick_clock; +__externC cyg_uint32 hal_lm3s_sysclk; + +//========================================================================== +// System init +// +// This code runs before the DATA is copied from ROM and the BSS cleared, +// hence it cannot make use of static variables or data tables. + +__externC void +hal_system_init( void ) +{ +} + + +//========================================================================== +// Setup up system clocks +// +void +hal_start_clocks( void ) +{ + CYG_ADDRESS sc = CYGHWR_HAL_LM3S_SC; + cyg_uint32 rcc; +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL) + cyg_uint32 plllmis = CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS; + cyg_uint32 plllris = CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS; + volatile cyg_uint16 wait; +#endif + + // At power up, the LM3S8xx is setup to use external oscillator. + // The PLL is powered down and bypass. Same goes for the system + // clock divider. + + // For JTAG cold restart, first we make sure the PLL and system + // clock divider are bypassed, enable all clock source and shutdown + // the PLL. + + HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + + rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV | + CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS | + CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS ); + + rcc |= CYGHWR_HAL_LM3S_SC_RCC_BYPASS; + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + + rcc |= ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN | CYGHWR_HAL_LM3S_SC_RCC_OEN ); + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + + // PLL is setup if in use + // + // The XTAL frequency is configured. The PLL is powered and + // its output is enable + + // Setup Clock Source + rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD; + +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL) + + // Clear PLL lock bit + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_MISC, plllmis ); + + rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK | + ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN ) | + ( CYGHWR_HAL_LM3S_SC_RCC_OEN ) ); + + rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL; + +#endif + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + + // + // Setup System Clock divider + // + +#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1 + + // Use system clock divider + rcc |= CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV; + + // Clear system clock divider bits + rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK; + + // Configure divider + rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL; + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + +#endif + + // Wait for PLL lock before feeding the clock to the + // device + +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL) + + // Wait for PLL lock, potentially a dead lock + plllris = 0; + while ( 0 == ( plllris & CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS ) ) { + // Wait + for ( wait = 0; wait < ( ( 2 ^ 16 ) - 1 ); wait++ ) + HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RIS, plllris ); + } + + // Clear bypass bit + rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_BYPASS; + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + +#endif + + // + // Disable clock source not in use + // +#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT) + + rcc |= CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS; + +#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT) + + rcc |= CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS; + +#endif + + HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc ); + + hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK; + hal_lm3s_sysclk = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK; +} + +//========================================================================== +// EOF lm3s8xx_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c @@ -0,0 +1,359 @@ +//============================================================================= +// +// timers.c +// +// Test for Stellaris Cortex-M3 Device Timers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg for STM32 +// ccoutand updated for Stellaris Cortex-M3 Devices +// Date: 2011-01-18 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#if defined(CYGPKG_KERNEL) +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/testcase.h> + +//============================================================================= +// Check all required packages and components are present + +#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API) +# define NA_MSG "Configuration insufficient" +#endif + +//============================================================================= +// If everything is present, compile the full test. + +#ifndef NA_MSG + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> + +#include <cyg/kernel/kapi.h> +#include <cyg/infra/diag.h> +#include <string.h> + +//============================================================================= + +#define LOOPS 24 // 2 minutes +#define SINGLE_TIMER 0 // Full / Single timer test + +static int test_stack[( CYGNUM_HAL_STACK_SIZE_MINIMUM / sizeof( int ) )]; +static cyg_thread test_thread; +static cyg_handle_t main_thread; + +//============================================================================= + +struct timer { + cyg_uint32 timer; + cyg_uint32 base; + cyg_uint32 periph; + cyg_uint32 vector; + cyg_uint32 priority; + cyg_uint32 interval; + + cyg_uint32 ticks; + + cyg_uint32 preempt[10]; + + cyg_uint32 preempt_dsr[10]; + cyg_uint32 dsr_count[10]; + + cyg_interrupt interrupt_object; + cyg_handle_t interrupt_handle; +}; + +struct timer timers[] = { +#if SINGLE_TIMER + {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0, + CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 1000}, +#else + {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0, + CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 127}, + {2, CYGHWR_HAL_LM3S_GPTIM1, CYGHWR_HAL_LM3S_P_TIMER1, + CYGNUM_HAL_INTERRUPT_GTIM1_A, 0x60, 355}, + {3, CYGHWR_HAL_LM3S_GPTIM2, CYGHWR_HAL_LM3S_P_TIMER2, + CYGNUM_HAL_INTERRUPT_GTIM2_A, 0x80, 731}, +#endif + {0, 0, 0, 0} +}; + + +//============================================================================= + +volatile cyg_uint32 ticks = 0; +volatile cyg_uint32 nesting = 0; +volatile cyg_uint32 max_nesting = 0; +volatile cyg_uint32 max_nesting_seen = 0; +volatile cyg_uint32 current = 0; +volatile cyg_uint32 in_dsr = 0; + + +//============================================================================= + +void +init_timer( cyg_uint32 base, cyg_uint32 periph, cyg_uint32 interval ) +{ + cyg_uint32 period = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK; + + CYGHWR_HAL_LM3S_PERIPH_SET( periph, 1 ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0x0000 ); + + period = period / 1000000; + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAPR, period ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CFG, + CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAMR, + CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAILR, interval ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_ICR, + CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_IMR, + CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM ); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL, + CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN ); +} + + +//============================================================================= + +cyg_uint32 +timer_isr( cyg_uint32 vector, CYG_ADDRWORD data ) +{ + struct timer *t = ( struct timer * )data; + cyg_uint32 preempt = current; + CYG_ADDRWORD base = t->base; + cyg_uint32 cnt; + + current = t->timer; + t->ticks++; + ticks++; + t->preempt[preempt]++; + nesting++; + + // Count only first ISR to preempt a DSR + if( preempt == 0 ) + t->preempt_dsr[in_dsr]++; + + HAL_WRITE_UINT32( t->base + CYGHWR_HAL_LM3S_GPTIM_ICR, + CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT ); + + if( nesting > max_nesting ) + max_nesting = nesting; + + // Loiter here for a proportion of the timer interval to give + // other timers the chance to preempt us. + do { + HAL_READ_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAR, cnt ); + } while( cnt < t->interval / 10 ); + + nesting--; + current = preempt; + + if( ( t->ticks % 10 ) == 0 ) + return 3; + else + return 1; +} + + +//============================================================================= + +void +timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data ) +{ + struct timer *t = ( struct timer * )data; + int i; + + in_dsr = t->timer; + + if( count >= 8 ) + count = 8; + + t->dsr_count[count]++; + + // Loiter for a while + for( i = 0; i < t->interval / 10; i++ ) + continue; + + in_dsr = 0; +} + + +//============================================================================= + +void +timers_test( cyg_addrword_t data ) +{ + int loops = LOOPS; + int i; + CYG_INTERRUPT_STATE istate; + + CYG_TEST_INIT( ); + + CYG_TEST_INFO( "Start Timers test" ); + + for( i = 0; timers[i].timer != 0; i++ ) { + struct timer *t = &timers[i]; + + init_timer( t->base, t->periph, t->interval ); + + cyg_interrupt_create( t->vector, + t->priority, + ( cyg_addrword_t )t, + timer_isr, + timer_dsr, + &t->interrupt_handle, &t->interrupt_object ); + + cyg_interrupt_attach( t->interrupt_handle ); + cyg_interrupt_unmask( t->vector ); + + } + + while( loops-- ) { + int j; + + // 5 second delay + cyg_thread_delay( 5 * 100 ); + + // Disable interrupts while we print details, otherwise it + // comes out very slowly. + HAL_DISABLE_INTERRUPTS( istate ); + + if( max_nesting > max_nesting_seen ) + max_nesting_seen = max_nesting; + + diag_printf( "\nISRs max_nesting %d max_nesting_seen %d\n", + max_nesting, max_nesting_seen ); + max_nesting = 0; + + diag_printf( " T Ticks " ); + + for( j = 0; j < 9; j++ ) + diag_printf( "%9d ", j ); + diag_printf( "\n" ); + + for( i = 0; timers[i].timer != 0; i++ ) { + struct timer *t = &timers[i]; + + diag_printf( "%2d: %9d ", t->timer, t->ticks ); + + for( j = 0; j < 9; j++ ) + diag_printf( "%9d ", t->preempt[j] ); + diag_printf( "\n" ); + + } + + diag_printf( "DSRs\n" ); + + diag_printf( " T: " ); + + for( j = 0; j < 9; j++ ) + diag_printf( "%9d ", j ); + diag_printf( "\n" ); + + for( i = 0; timers[i].timer != 0; i++ ) { + struct timer *t = &timers[i]; + + diag_printf( "%2d: preempt: ", t->timer ); + + for( j = 0; j < 9; j++ ) + diag_printf( "%9d ", t->preempt_dsr[j] ); + diag_printf( "\n" ); + + diag_printf( " count: " ); + + for( j = 0; j < 9; j++ ) + diag_printf( "%9d ", t->dsr_count[j] ); + diag_printf( "\n" ); + } + + HAL_RESTORE_INTERRUPTS( istate ); + } + + CYG_TEST_PASS_FINISH( "Timers test" ); +} + + +//============================================================================= + +void +cyg_user_start( void ) +{ + cyg_thread_create( 0, // Priority + timers_test, // + 0, // + "timers test", // Name + test_stack, // Stack + CYGNUM_HAL_STACK_SIZE_MINIMUM, // Stack size + &main_thread, // Handle + &test_thread // Thread data structure + ); + cyg_thread_resume( main_thread ); +} + +//============================================================================= + +#else // NA_MSG + +void +cyg_user_start( void ) +{ + CYG_TEST_NA( NA_MSG ); +} + +#endif // NA_MSG + +//============================================================================= +// EOF timers.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/ChangeLog @@ -0,0 +1,38 @@ +2011-01-18 Christophe Coutand <ccoutand@stmi.com> + + * cdl/hal_cortexm_lm3s.cdl + * include/hal_cache.h: + * include/hal_diag.h: + * include/plf_stub.h: + * include/var_arch.h: + * include/variant.inc: + * include/var_intr.h: + * include/var_io.h: + * src/hal_diag.c: + * src/lm3s_misc.c: + New package -- Stellaris Cortex M3 variant HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl @@ -0,0 +1,123 @@ +##========================================================================== +## +## hal_cortexm_lm3s.cdl +## +## Stellaris Cortex-M3 variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): ccoutand +## Date: 2011-01-18 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_LM3S { + display "Stellaris Cortex-M3 from Luminary Micro variant HAL" + parent CYGPKG_HAL_CORTEXM + define_header hal_cortexm_lm3s.h + include_dir cyg/hal + hardware + description " + This package provides generic support for the Cortex-M3 based + Stellaris microcontroller family. It is also necessary to select + a variant and platform HAL package." + + compile hal_diag.c lm3s_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + requires { CYGHWR_HAL_CORTEXM == "M3" } + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + + # Let the architectural HAL see this variant's files + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H" + puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_ARCH_H" + } + + cdl_option CYGHWR_HAL_CORTEXM_LM3S { + display "Stellaris Cortex-M3 variant in use" + flavor data + default_value { "LM3S8XX" } + legal_values { "LM3S8XX" } + description " + Currently only supported the Stellaris Cortex-M3 800 Series." + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU priority levels" + flavor data + calculated 3 + description " + This option defines the number of bits used to encode the + exception priority levels that this variant of the Cortex-M3 + CPU implements." + } + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + calculated 0xC0 + description " + Set clock ISR priority to lowest priority." + } + + cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART0 { + display "Platform has UART0 serial port" + description " + The platform has a socket on UART0." + } + + cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART1 { + display "Platform has UART1 serial port" + description " + The platform has a socket on UART1." + } + + cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART2 { + display "Platform has UART2 serial port" + description " + The platform has a socket on UART2." + } + +} + +# EOF hal_cortex_lm3s.cdl
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h @@ -0,0 +1,66 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Contributors: +// Date: 2011-01-18 +// Purpose: Cache control API +// Description: The Stellaris LM3S Cortex-M3 microcontroller does not require +// cache control. File is kept empty. +// +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +# define HAL_DIAG_INIT() hal_if_diag_init() +# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +# define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_lm3s_diag_init(void); +__externC void hal_lm3s_diag_putc(char); +__externC cyg_uint8 hal_lm3s_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_lm3s_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_lm3s_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_lm3s_diag_getc() +# endif + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_DIAG_H +// EOF of hal_diag.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Platform HAL stub support for Stellaris Cortex-M3 +// variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/var_arch.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Stellaris Cortex-M3 variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Stellaris Cortex-M3 variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// EOF of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/var_intr.h @@ -0,0 +1,119 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for Stellaris Cortex-M3 variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for Stellaris Cortex-M3 +// are defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_GPIOA (0+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOB (1+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOC (2+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOD (3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOE (4+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART0 (5+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART1 (6+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SSI0 (7+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C (8+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_PWM0 (10+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_PWM1 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_PWM2 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_QIE (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ADC0_S0 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ADC0_S1 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ADC0_S2 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ADC0_S3 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_WDT (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM0_A (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM0_B (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM1_A (21+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM1_B (22+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM2_A (23+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM2_B (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_AC0 (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_AC1 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_AC2 (27+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SCTL (28+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_FMS (29+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOF (30+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOG (31+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GPIOH (32+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM3_A (35+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_GTIM3_B (36+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN0 (39+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ETH0 (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_HIM (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX +# define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_HIM) +#endif + +#define CYGNUM_HAL_ISR_MIN 0 +#ifndef CYGNUM_HAL_ISR_MAX +# define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/var_io.h @@ -0,0 +1,1371 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Purpose: Stellaris Cortex-M3 variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_lm3s.h> + +#include <cyg/hal/plf_io.h> + +//============================================================================= +// Peripherals + +#define CYGHWR_HAL_LM3S_FLASH 0x00000000 +#define CYGHWR_HAL_LM3S_SRAM 0x20000000 + +#define CYGHWR_HAL_LM3S_WDT0 0x40000000 +#define CYGHWR_HAL_LM3S_GPIOA 0x40004000 +#define CYGHWR_HAL_LM3S_GPIOB 0x40005000 +#define CYGHWR_HAL_LM3S_GPIOC 0x40006000 +#define CYGHWR_HAL_LM3S_GPIOD 0x40007000 +#define CYGHWR_HAL_LM3S_SSI0 0x40008000 +#define CYGHWR_HAL_LM3S_SSI1 0x40009000 +#define CYGHWR_HAL_LM3S_UART0 0x4000C000 +#define CYGHWR_HAL_LM3S_UART1 0x4000D000 +#define CYGHWR_HAL_LM3S_UART2 0x4000E000 +#define CYGHWR_HAL_LM3S_I2C_M0 0x40020000 +#define CYGHWR_HAL_LM3S_I2C_S0 0x40020800 +#define CYGHWR_HAL_LM3S_GPIOE 0x40024000 +#define CYGHWR_HAL_LM3S_GPIOF 0x40025000 +#define CYGHWR_HAL_LM3S_GPIOG 0x40026000 +#define CYGHWR_HAL_LM3S_GPIOH 0x40027000 +#define CYGHWR_HAL_LM3S_PWM 0x40028000 +#define CYGHWR_HAL_LM3S_QEI0 0x4002C000 +#define CYGHWR_HAL_LM3S_GPTIM0 0x40030000 +#define CYGHWR_HAL_LM3S_GPTIM1 0x40031000 +#define CYGHWR_HAL_LM3S_GPTIM2 0x40032000 +#define CYGHWR_HAL_LM3S_GPTIM3 0x40033000 +#define CYGHWR_HAL_LM3S_ADC0 0x40038000 +#define CYGHWR_HAL_LM3S_AC 0x4003C000 +#define CYGHWR_HAL_LM3S_CAN0 0x40040000 +#define CYGHWR_HAL_LM3S_ETH0 0x40048000 +#define CYGHWR_HAL_LM3S_FMC 0x400FD000 +#define CYGHWR_HAL_LM3S_SC 0x400FE000 + +#define CYGHWR_HAL_LM3S_ITM 0xE0000000 +#define CYGHWR_HAL_LM3S_DWT 0xE0001000 +#define CYGHWR_HAL_LM3S_FPB 0xE0002000 +#define CYGHWR_HAL_LM3S_CORTEXM3 0xE000E000 +#define CYGHWR_HAL_LM3S_TPIU 0xE0040000 + + +//============================================================================= +// Device signature and ID registers + +#define CYGHWR_HAL_LM3S_MCU_ID (CYGHWR_HAL_LM3S_CORTEXM3 + 0xD00) +#define CYGHWR_HAL_LM3S_MCU_ID_REV(__x) ((__x)&0xF) +#define CYGHWR_HAL_LM3S_MCU_PART_NO(__x) (((__x)>>4)&0x0FFF) +#define CYGHWR_HAL_LM3S_MCU_VAR_NO(__x) (((__x)>>20)&0xF) + + +//============================================================================= +// System Control + +#define CYGHWR_HAL_LM3S_SC_DID0 0x000 +#define CYGHWR_HAL_LM3S_SC_DID1 0x004 +#define CYGHWR_HAL_LM3S_SC_DIC0 0x008 +#define CYGHWR_HAL_LM3S_SC_DIC1 0x010 +#define CYGHWR_HAL_LM3S_SC_DIC2 0x014 +#define CYGHWR_HAL_LM3S_SC_DIC3 0x018 +#define CYGHWR_HAL_LM3S_SC_DIC4 0x01c +#define CYGHWR_HAL_LM3S_SC_PBORCTL 0x030 +#define CYGHWR_HAL_LM3S_SC_LDORCTL 0x034 +#define CYGHWR_HAL_LM3S_SC_SRCR0 0x040 +#define CYGHWR_HAL_LM3S_SC_SRCR1 0x044 +#define CYGHWR_HAL_LM3S_SC_SRCR2 0x048 +#define CYGHWR_HAL_LM3S_SC_RIS 0x050 +#define CYGHWR_HAL_LM3S_SC_IMC 0x054 +#define CYGHWR_HAL_LM3S_SC_MISC 0x058 +#define CYGHWR_HAL_LM3S_SC_RESC 0x05C +#define CYGHWR_HAL_LM3S_SC_RCC 0x060 +#define CYGHWR_HAL_LM3S_SC_PLLCFG 0x064 +#define CYGHWR_HAL_LM3S_SC_RCGC0 0x100 +#define CYGHWR_HAL_LM3S_SC_RCGC1 0x104 +#define CYGHWR_HAL_LM3S_SC_RCGC2 0x108 +#define CYGHWR_HAL_LM3S_SC_SCGC0 0x110 +#define CYGHWR_HAL_LM3S_SC_SCGC1 0x114 +#define CYGHWR_HAL_LM3S_SC_SCGC2 0x118 +#define CYGHWR_HAL_LM3S_SC_DCGC0 0x120 +#define CYGHWR_HAL_LM3S_SC_DCGC1 0x124 +#define CYGHWR_HAL_LM3S_SC_DCGC2 0x128 +#define CYGHWR_HAL_LM3S_SC_FMPRE 0x130 +#define CYGHWR_HAL_LM3S_SC_FMPPE 0x134 +#define CYGHWR_HAL_LM3S_SC_USECRL 0x140 +#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG 0x144 +#define CYGHWR_HAL_LM3S_SC_CLKVCLR 0x150 +#define CYGHWR_HAL_LM3S_SC_LDOARST 0x160 + +// PBORCTL bits +#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORWT BIT_(0) +#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORIOR BIT_(1) +#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORTIM(__x) VALUE_(2,__x) + +// RIS bits +#define CYGHWR_HAL_LM3S_SC_RIS_PLLFRIS BIT_(0) +#define CYGHWR_HAL_LM3S_SC_RIS_BORRIS BIT_(1) +#define CYGHWR_HAL_LM3S_SC_RIS_LDORIS BIT_(2) +#define CYGHWR_HAL_LM3S_SC_RIS_MOFRIS BIT_(3) +#define CYGHWR_HAL_LM3S_SC_RIS_IOFRIS BIT_(4) +#define CYGHWR_HAL_LM3S_SC_RIS_CLFRIS BIT_(5) +#define CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS BIT_(6) + +// IMC bits +#define CYGHWR_HAL_LM3S_SC_IMC_PLLFIM BIT_(0) +#define CYGHWR_HAL_LM3S_SC_IMC_BORRIM BIT_(1) +#define CYGHWR_HAL_LM3S_SC_IMC_LDOIM BIT_(2) +#define CYGHWR_HAL_LM3S_SC_IMC_MOFIM BIT_(3) +#define CYGHWR_HAL_LM3S_SC_IMC_IOFIM BIT_(4) +#define CYGHWR_HAL_LM3S_SC_IMC_CLIM BIT_(5) +#define CYGHWR_HAL_LM3S_SC_IMC_PLLLFIM BIT_(6) + +// MISC bits +#define CYGHWR_HAL_LM3S_SC_MISC_BORMIS BIT_(1) +#define CYGHWR_HAL_LM3S_SC_MISC_LDOMIS BIT_(2) +#define CYGHWR_HAL_LM3S_SC_MISC_MOFMIS BIT_(3) +#define CYGHWR_HAL_LM3S_SC_MISC_IOFMIS BIT_(4) +#define CYGHWR_HAL_LM3S_SC_MISC_CLMIS BIT_(5) +#define CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS BIT_(6) + +// RESC bits +#define CYGHWR_HAL_LM3S_SC_RESC_EXT BIT_(0) +#define CYGHWR_HAL_LM3S_SC_RESC_POR BIT_(1) +#define CYGHWR_HAL_LM3S_SC_RESC_BOR BIT_(2) +#define CYGHWR_HAL_LM3S_SC_RESC_WDT BIT_(3) +#define CYGHWR_HAL_LM3S_SC_RESC_SW BIT_(4) +#define CYGHWR_HAL_LM3S_SC_RESC_LDO BIT_(5) + +// RCC bits +#define CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS BIT_(0) +#define CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS BIT_(1) +#define CYGHWR_HAL_LM3S_SC_RCC_MOSCVER BIT_(2) +#define CYGHWR_HAL_LM3S_SC_RCC_IOSCVER BIT_(3) +#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC VALUE_(4,0) +#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC VALUE_(4,1) +#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4 VALUE_(4,2) +#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MASK 0x00000030 +#define CYGHWR_HAL_LM3S_SC_RCC_XTAL(__x) VALUE_(6,__x) +#define CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK 0x000003C0 +#define CYGHWR_HAL_LM3S_SC_RCC_PLLVER BIT_(10) +#define CYGHWR_HAL_LM3S_SC_RCC_BYPASS BIT_(11) +#define CYGHWR_HAL_LM3S_SC_RCC_OEN BIT_(12) +#define CYGHWR_HAL_LM3S_SC_RCC_PWRDN BIT_(13) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV2 VALUE_(14, 0x0) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV4 VALUE_(14, 0x1) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV8 VALUE_(14, 0x2) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV16 VALUE_(14, 0x3) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV32 VALUE_(14, 0x4) +#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV64 VALUE_(14, 0x5) +#define CYGHWR_HAL_LM3S_SC_RCC_USEPWMDIV BIT_(20) +#define CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV BIT_(22) +#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV(__x) VALUE_(23, __x) +#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK 0x07800000 +#define CYGHWR_HAL_LM3S_SC_RCC_ACG BIT_(27) + +// DSLPCLKCFG bits +#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG_IOSC BIT_(0) + +// CLKVCLR bits +#define CYGHWR_HAL_LM3S_SC_CLKVCLR_VERCLR BIT_(0) + +// LDOARST bits +#define CYGHWR_HAL_LM3S_SC_LDOARST_BIT BIT_(0) + +// RCGC0 bits +#define CYGHWR_HAL_LM3S_SC_RCGC0_WDT0 BIT_(3) +#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_125K VALUE_(8, 0x0) +#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_250K VALUE_(8, 0x1) +#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_500K VALUE_(8, 0x2) +#define CYGHWR_HAL_LM3S_SC_RCGC0_ADC0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_RCGC0_PWM0 BIT_(20) + +// SCGC0 bits +#define CYGHWR_HAL_LM3S_SC_SCGC0_WDT0 BIT_(3) +#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_125K VALUE_(8, 0x0) +#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_250K VALUE_(8, 0x1) +#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_500K VALUE_(8, 0x2) +#define CYGHWR_HAL_LM3S_SC_SCGC0_ADC0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_SCGC0_PWM0 BIT_(20) + +// DCGC0 bits +#define CYGHWR_HAL_LM3S_SC_DCGC0_WDT0 BIT_(3) +#define CYGHWR_HAL_LM3S_SC_DCGC0_ADC0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_DCGC0_PWM0 BIT_(20) + +// RCGC1 bits +#define CYGHWR_HAL_LM3S_SC_RCGC1_UART0 BIT_(0) +#define CYGHWR_HAL_LM3S_SC_RCGC1_UART1 BIT_(1) +#define CYGHWR_HAL_LM3S_SC_RCGC1_SSI0 BIT_(4) +#define CYGHWR_HAL_LM3S_SC_RCGC1_I2C0 BIT_(12) +#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER1 BIT_(17) +#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER2 BIT_(18) +#define CYGHWR_HAL_LM3S_SC_RCGC1_COMP0 BIT_(24) + +// SCSG1 bits +#define CYGHWR_HAL_LM3S_SC_SCGC1_UART0 BIT_(0) +#define CYGHWR_HAL_LM3S_SC_SCGC1_UART1 BIT_(1) +#define CYGHWR_HAL_LM3S_SC_SCGC1_SSI0 BIT_(4) +#define CYGHWR_HAL_LM3S_SC_SCGC1_I2C0 BIT_(12) +#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1 BIT_(17) +#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2 BIT_(18) +#define CYGHWR_HAL_LM3S_SC_SCGC1_COMP0 BIT_(24) + +// DCSG1 bits +#define CYGHWR_HAL_LM3S_SC_DCGC1_UART0 BIT_(0) +#define CYGHWR_HAL_LM3S_SC_DCGC1_UART1 BIT_(1) +#define CYGHWR_HAL_LM3S_SC_DCGC1_SSI0 BIT_(4) +#define CYGHWR_HAL_LM3S_SC_DCGC1_I2C0 BIT_(12) +#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER0 BIT_(16) +#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER1 BIT_(17) +#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER2 BIT_(18) +#define CYGHWR_HAL_LM3S_SC_DCGC1_COMP0 BIT_(24) + +// RCGC2 bits +#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA BIT_(0) +#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB BIT_(1) +#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC BIT_(2) +#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD BIT_(3) +#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE BIT_(4) + +// SCSG2 bits +#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOA BIT_(0) +#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOB BIT_(1) +#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOC BIT_(2) +#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOD BIT_(3) +#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOE BIT_(4) + +// DCSG2 bits +#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOA BIT_(0) +#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOB BIT_(1) +#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOC BIT_(2) +#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOD BIT_(3) +#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOE BIT_(4) + +// Define peripheral +#define CYGHWR_HAL_LM3S_PERIPH_GC0 BIT_(31) +#define CYGHWR_HAL_LM3S_P_WDT0 ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_WDT0 ) +#define CYGHWR_HAL_LM3S_P_ADC0 ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_ADC0 ) +#define CYGHWR_HAL_LM3S_P_PWM ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_PWM0 ) +#define CYGHWR_HAL_LM3S_PERIPH_GC1 BIT_(30) +#define CYGHWR_HAL_LM3S_P_UART0 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART0 ) +#define CYGHWR_HAL_LM3S_P_UART1 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART1 ) +#define CYGHWR_HAL_LM3S_P_SSI0 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_SSI0 ) +#define CYGHWR_HAL_LM3S_P_I2C0 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_I2C0 ) +#define CYGHWR_HAL_LM3S_P_TIMER0 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0 ) +#define CYGHWR_HAL_LM3S_P_TIMER1 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1 ) +#define CYGHWR_HAL_LM3S_P_TIMER2 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2 ) +#define CYGHWR_HAL_LM3S_P_COMP0 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_COMP0 ) +#define CYGHWR_HAL_LM3S_PERIPH_GC2 BIT_(29) +#define CYGHWR_HAL_LM3S_P_GPIOA ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA ) +#define CYGHWR_HAL_LM3S_P_GPIOB ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB ) +#define CYGHWR_HAL_LM3S_P_GPIOC ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC ) +#define CYGHWR_HAL_LM3S_P_GPIOD ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD ) +#define CYGHWR_HAL_LM3S_P_GPIOE ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE ) + +__externC void hal_lm3s_periph_set( cyg_uint32 periph, cyg_uint32 on_off ); + +#define CYGHWR_HAL_LM3S_PERIPH_SET(__periph, __on_off ) hal_lm3s_periph_set( __periph, __on_off ) + +//============================================================================= +// Watchdog + +#define CYGHWR_HAL_LM3S_WDT_LOAD 0x000 +#define CYGHWR_HAL_LM3S_WDT_VALUE 0x004 +#define CYGHWR_HAL_LM3S_WDT_CTL 0x008 +#define CYGHWR_HAL_LM3S_WDT_ICR 0x00c +#define CYGHWR_HAL_LM3S_WDT_RIS 0x010 +#define CYGHWR_HAL_LM3S_WDT_MIS 0x014 +#define CYGHWR_HAL_LM3S_WDT_TEST 0x418 +#define CYGHWR_HAL_LM3S_WDT_LOCK 0xc00 +#define CYGHWR_HAL_LM3S_WDT_PID4 0xfd0 +#define CYGHWR_HAL_LM3S_WDT_PID5 0xfd4 +#define CYGHWR_HAL_LM3S_WDT_PID6 0xfd8 +#define CYGHWR_HAL_LM3S_WDT_PID7 0xfdc +#define CYGHWR_HAL_LM3S_WDT_PID0 0xfe0 +#define CYGHWR_HAL_LM3S_WDT_PID1 0xfe4 +#define CYGHWR_HAL_LM3S_WDT_PID2 0xfe8 +#define CYGHWR_HAL_LM3S_WDT_PID3 0xfec +#define CYGHWR_HAL_LM3S_WDT_PCID0 0xff0 +#define CYGHWR_HAL_LM3S_WDT_PCID1 0xff4 +#define CYGHWR_HAL_LM3S_WDT_PCID2 0xff8 +#define CYGHWR_HAL_LM3S_WDT_PCID3 0xffc + + +#define CYGHWR_HAL_LM3S_WDT_CTL_INTEN BIT_(0) +#define CYGHWR_HAL_LM3S_WDT_CTL_RESEN BIT_(1) + +#define CYGHWR_HAL_LM3S_WDT_RIS_RIS BIT_(0) + +#define CYGHWR_HAL_LM3S_WDT_MIS_MIS BIT_(0) + +#define CYGHWR_HAL_LM3S_WDT_TEST_STALL BIT_(8) + +#define CYGHWR_HAL_LM3S_WDT_PID(__x) ((__x)&0xFF) +#define CYGHWR_HAL_LM3S_WDT_PCID(__x) ((__x)&0xFF) + + +//============================================================================= +// GPIO ports + +#define CYGHWR_HAL_LM3S_GPIO_DATA 0x000 +#define CYGHWR_HAL_LM3S_GPIO_DIR 0x400 +#define CYGHWR_HAL_LM3S_GPIO_IS 0x404 +#define CYGHWR_HAL_LM3S_GPIO_IBE 0x408 +#define CYGHWR_HAL_LM3S_GPIO_IEV 0x40c +#define CYGHWR_HAL_LM3S_GPIO_IM 0x410 +#define CYGHWR_HAL_LM3S_GPIO_RIS 0x414 +#define CYGHWR_HAL_LM3S_GPIO_MIS 0x418 +#define CYGHWR_HAL_LM3S_GPIO_ICR 0x41c +#define CYGHWR_HAL_LM3S_GPIO_AFSEL 0x420 +#define CYGHWR_HAL_LM3S_GPIO_DR2R 0x500 +#define CYGHWR_HAL_LM3S_GPIO_DR4R 0x504 +#define CYGHWR_HAL_LM3S_GPIO_DR8R 0x508 +#define CYGHWR_HAL_LM3S_GPIO_ODR 0x50c +#define CYGHWR_HAL_LM3S_GPIO_PUR 0x510 +#define CYGHWR_HAL_LM3S_GPIO_PDR 0x514 +#define CYGHWR_HAL_LM3S_GPIO_SLR 0x518 +#define CYGHWR_HAL_LM3S_GPIO_DEN 0x51c +#define CYGHWR_HAL_LM3S_GPIO_PID4 0xfd0 +#define CYGHWR_HAL_LM3S_GPIO_PID5 0xfd4 +#define CYGHWR_HAL_LM3S_GPIO_PID6 0xfd8 +#define CYGHWR_HAL_LM3S_GPIO_PID7 0xfdc +#define CYGHWR_HAL_LM3S_GPIO_PID0 0xfe0 +#define CYGHWR_HAL_LM3S_GPIO_PID1 0xfe4 +#define CYGHWR_HAL_LM3S_GPIO_PID2 0xfe8 +#define CYGHWR_HAL_LM3S_GPIO_PID3 0xfec +#define CYGHWR_HAL_LM3S_GPIO_PCID0 0xff0 +#define CYGHWR_HAL_LM3S_GPIO_PCID1 0xff4 +#define CYGHWR_HAL_LM3S_GPIO_PCID2 0xff8 +#define CYGHWR_HAL_LM3S_GPIO_PCID3 0xffc + +#define CYGHWR_HAL_LM3S_GPIO_DIR_IN VALUE_(0,0) // Input mode +#define CYGHWR_HAL_LM3S_GPIO_DIR_OUT VALUE_(0,1) // Output mode + +#define CYGHWR_HAL_LM3S_GPIO_IS_EDGE_SENSE VALUE_(0,0) // Interrupt edge sensitive +#define CYGHWR_HAL_LM3S_GPIO_IS_LEV_SENSE VALUE_(0,1) // Interrupt level sensitive + +#define CYGHWR_HAL_LM3S_GPIO_IBE_GPIOIEV VALUE_(0,0) // Interrupt control from GPIOIEV +#define CYGHWR_HAL_LM3S_GPIO_IBE_BOTH_EDGE VALUE_(0,1) // Both edges can trigger interrupt + +#define CYGHWR_HAL_LM3S_GPIO_IEV_LOW VALUE_(0,0) // Falling edge or low triggers interrupt +#define CYGHWR_HAL_LM3S_GPIO_IEV_HIGH VALUE_(0,1) // Rising edge or low triggers interrupt + +#define CYGHWR_HAL_LM3S_GPIO_IM_MASK VALUE_(0,0) // Interrupt is masked +#define CYGHWR_HAL_LM3S_GPIO_IM_UMASK VALUE_(0,1) + +// HAL definitions +#define CYGHWR_HAL_LM3S_GPIO_MODE_IN VALUE_(0,0) // Input mode +#define CYGHWR_HAL_LM3S_GPIO_MODE_OUT VALUE_(0,1) // Output mode +#define CYGHWR_HAL_LM3S_GPIO_MODE_PERIPH VALUE_(0,2) // Peripheral function mode + +#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_NONE VALUE_(2,0) // Strength not specified +#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA VALUE_(2,1) // Strength 2 mA +#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA VALUE_(2,2) // Strength 4 mA +#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA VALUE_(2,3) // Strength 8 mA + +#define CYGHWR_HAL_LM3S_GPIO_CNF_NONE VALUE_(4,0) // Configuration not specified +#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP VALUE_(4,1) // Pull-up +#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN VALUE_(4,2) // Pull-down +#define CYGHWR_HAL_LM3S_GPIO_CNF_OP VALUE_(4,3) // Open-drain +#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP VALUE_(4,4) // Open-drain / Pull-up +#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN VALUE_(4,5) // Open-drain / Pull-down +#define CYGHWR_HAL_LM3S_GPIO_CNF_AIN VALUE_(4,6) // Analog + +#define CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE VALUE_(9,0) // Interrupt disable +#define CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE VALUE_(9,1) // Interrupt on falling edge +#define CYGHWR_HAL_LM3S_GPIO_IRQ_RISING_EDGE VALUE_(9,2) // Interrupt on rising edge +#define CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES VALUE_(9,3) // Interrupt on both edges +#define CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL VALUE_(9,4) // Interrupt on low level +#define CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL VALUE_(9,5) // Interrupt on high level + +// This macro packs the port number, bit number, mode, strength, irq and +// configuration for a GPIO pin into a single word. +// The packing puts: + +#define CYGHWR_HAL_LM3S_GPIO( \ + __port, \ + __bit, \ + __mode, \ + __strength, \ + __cnf, \ + __irq) \ +( \ + (CYGHWR_HAL_LM3S_GPIO ## __port - CYGHWR_HAL_LM3S_GPIOA) | \ + (__bit << 24) | \ + (CYGHWR_HAL_LM3S_GPIO_MODE_ ## __mode) | \ + (CYGHWR_HAL_LM3S_GPIO_STRENGTH_ ## __strength) | \ + (CYGHWR_HAL_LM3S_GPIO_IRQ_ ## __irq) | \ + (CYGHWR_HAL_LM3S_GPIO_CNF_ ## __cnf) \ +) + +// Macros to extract encoded values +#define CYGHWR_HAL_LM3S_GPIO_PORT(__pin) (CYGHWR_HAL_LM3S_GPIOA+((__pin)&0x000FF000)) +#define CYGHWR_HAL_LM3S_GPIO_BIT(__pin) (((__pin)>>24)&0x07) +#define CYGHWR_HAL_LM3S_GPIO_MODE(__pin) ((__pin)&0x0003) +#define CYGHWR_HAL_LM3S_GPIO_STRENGTH(__pin) ((__pin)&VALUE_(2,3)) +#define CYGHWR_HAL_LM3S_GPIO_CFG(__pin) ((__pin)&VALUE_(4,7)) +#define CYGHWR_HAL_LM3S_GPIO_IRQ(__pin) ((__pin)&VALUE_(9,7)) + +#define CYGHWR_HAL_LM3S_GPIO_NONE (0xFFFFFFFF) + + +// Functions and macros to configure GPIO ports. + +__externC void hal_lm3s_gpio_set( cyg_uint32 pin ); +__externC void hal_lm3s_gpio_out( cyg_uint32 pin, int val ); +__externC void hal_lm3s_gpio_in ( cyg_uint32 pin, int *val ); + +#define CYGHWR_HAL_LM3S_GPIO_SET(__pin ) hal_lm3s_gpio_set( __pin ) +#define CYGHWR_HAL_LM3S_GPIO_OUT(__pin, __val ) hal_lm3s_gpio_out( __pin, __val ) +#define CYGHWR_HAL_LM3S_GPIO_IN(__pin, __val ) hal_lm3s_gpio_in( __pin, __val ) + + +//============================================================================= +// UARTs + +#define CYGHWR_HAL_LM3S_UART_DR 0x000 +#define CYGHWR_HAL_LM3S_UART_SR 0x004 +#define CYGHWR_HAL_LM3S_UART_FR 0x018 +#define CYGHWR_HAL_LM3S_UART_IBRD 0x024 +#define CYGHWR_HAL_LM3S_UART_FBRD 0x028 +#define CYGHWR_HAL_LM3S_UART_LCRH 0x02c +#define CYGHWR_HAL_LM3S_UART_CTL 0x030 +#define CYGHWR_HAL_LM3S_UART_IFLS 0x034 +#define CYGHWR_HAL_LM3S_UART_IM 0x038 +#define CYGHWR_HAL_LM3S_UART_RIS 0x03c +#define CYGHWR_HAL_LM3S_UART_MIS 0x040 +#define CYGHWR_HAL_LM3S_UART_ICR 0x044 +#define CYGHWR_HAL_LM3S_UART_PID4 0xfd0 +#define CYGHWR_HAL_LM3S_UART_PID5 0xfd4 +#define CYGHWR_HAL_LM3S_UART_PID6 0xfd8 +#define CYGHWR_HAL_LM3S_UART_PID7 0xfdc +#define CYGHWR_HAL_LM3S_UART_PID0 0xfe0 +#define CYGHWR_HAL_LM3S_UART_PID1 0xfe4 +#define CYGHWR_HAL_LM3S_UART_PID2 0xfe8 +#define CYGHWR_HAL_LM3S_UART_PID3 0xfec +#define CYGHWR_HAL_LM3S_UART_PCID0 0xff0 +#define CYGHWR_HAL_LM3S_UART_PCID1 0xff4 +#define CYGHWR_HAL_LM3S_UART_PCID2 0xff8 +#define CYGHWR_HAL_LM3S_UART_PCID3 0xffc + + +// DR Bits +#define CYGHWR_HAL_LM3S_UART_DR_FE BIT_(8) +#define CYGHWR_HAL_LM3S_UART_DR_PE BIT_(9) +#define CYGHWR_HAL_LM3S_UART_DR_BE BIT_(10) +#define CYGHWR_HAL_LM3S_UART_DR_OE BIT_(11) + +// SR Bits +#define CYGHWR_HAL_LM3S_UART_SR_FE BIT_(0) +#define CYGHWR_HAL_LM3S_UART_SR_PE BIT_(1) +#define CYGHWR_HAL_LM3S_UART_SR_BE BIT_(2) +#define CYGHWR_HAL_LM3S_UART_SR_OE BIT_(3) + +// FR bits +#define CYGHWR_HAL_LM3S_UART_FR_BUSY BIT_(3) +#define CYGHWR_HAL_LM3S_UART_FR_RXFE BIT_(4) +#define CYGHWR_HAL_LM3S_UART_FR_TXFF BIT_(5) +#define CYGHWR_HAL_LM3S_UART_FR_RXFF BIT_(6) +#define CYGHWR_HAL_LM3S_UART_FR_TXFE BIT_(7) + +// LCRH bits +#define CYGHWR_HAL_LM3S_UART_LCRH_BRK BIT_(0) +#define CYGHWR_HAL_LM3S_UART_LCRH_PEN BIT_(1) +#define CYGHWR_HAL_LM3S_UART_LCRH_EPS BIT_(2) +#define CYGHWR_HAL_LM3S_UART_LCRH_STP2 BIT_(3) +#define CYGHWR_HAL_LM3S_UART_LCRH_FEN BIT_(4) +#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN(__x) VALUE_(5,__x) +#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN_MASK 0x00000060 +#define CYGHWR_HAL_LM3S_UART_LCRH_SPS BIT_(7) + +// CTL bits +#define CYGHWR_HAL_LM3S_UART_CTL_UARTEN BIT_(0) +#define CYGHWR_HAL_LM3S_UART_CTL_LBE BIT_(7) +#define CYGHWR_HAL_LM3S_UART_CTL_TXE BIT_(8) +#define CYGHWR_HAL_LM3S_UART_CTL_RXE BIT_(9) + +// IFLS bits +#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL(__x) VALUE_(0,__x) +#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL_MASK 0x00000007 +#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL(__x) VALUE_(3,__x) +#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL_MASK 0x00000038 + +// IM bits +#define CYGHWR_HAL_LM3S_UART_IM_RXIM BIT_(4) +#define CYGHWR_HAL_LM3S_UART_IM_TXIM BIT_(5) +#define CYGHWR_HAL_LM3S_UART_IM_RTIM BIT_(6) +#define CYGHWR_HAL_LM3S_UART_IM_FEIM BIT_(7) +#define CYGHWR_HAL_LM3S_UART_IM_PEIM BIT_(8) +#define CYGHWR_HAL_LM3S_UART_IM_BEIM BIT_(9) +#define CYGHWR_HAL_LM3S_UART_IM_OEIM BIT_(10) + +// RIS bits +#define CYGHWR_HAL_LM3S_UART_RIS_RXRIS BIT_(4) +#define CYGHWR_HAL_LM3S_UART_RIS_TXRIS BIT_(5) +#define CYGHWR_HAL_LM3S_UART_RIS_RTRIS BIT_(6) +#define CYGHWR_HAL_LM3S_UART_RIS_FERIS BIT_(7) +#define CYGHWR_HAL_LM3S_UART_RIS_PERIS BIT_(8) +#define CYGHWR_HAL_LM3S_UART_RIS_BERIS BIT_(9) +#define CYGHWR_HAL_LM3S_UART_RIS_OERIS BIT_(10) + +// MIS bits +#define CYGHWR_HAL_LM3S_UART_MIS_RXMIS BIT_(4) +#define CYGHWR_HAL_LM3S_UART_MIS_TXMIS BIT_(5) +#define CYGHWR_HAL_LM3S_UART_MIS_RTMIS BIT_(6) +#define CYGHWR_HAL_LM3S_UART_MIS_FEMIS BIT_(7) +#define CYGHWR_HAL_LM3S_UART_MIS_PEMIS BIT_(8) +#define CYGHWR_HAL_LM3S_UART_MIS_BEMIS BIT_(9) +#define CYGHWR_HAL_LM3S_UART_MIS_OEMIS BIT_(10) + +// ICR bits +#define CYGHWR_HAL_LM3S_UART_ICR_RXIC BIT_(4) +#define CYGHWR_HAL_LM3S_UART_ICR_TXIC BIT_(5) +#define CYGHWR_HAL_LM3S_UART_ICR_RTIC BIT_(6) +#define CYGHWR_HAL_LM3S_UART_ICR_FEIC BIT_(7) +#define CYGHWR_HAL_LM3S_UART_ICR_PEIC BIT_(8) +#define CYGHWR_HAL_LM3S_UART_ICR_BEIC BIT_(9) +#define CYGHWR_HAL_LM3S_UART_ICR_OEIC BIT_(10) + +// UARTO shall be connected to PortA 0/1 on all device +#ifndef CYGHWR_HAL_LM3S_UART0_TX +# define CYGHWR_HAL_LM3S_UART0_TX CYGHWR_HAL_LM3S_GPIO( A, 0, PERIPH, NONE, NONE, DISABLE ) +#endif +#ifndef CYGHWR_HAL_LM3S_UART0_RX +# define CYGHWR_HAL_LM3S_UART0_RX CYGHWR_HAL_LM3S_GPIO( A, 1, PERIPH, NONE, NONE, DISABLE ) +#endif +#ifndef CYGHWR_HAL_LM3S_P_UART0_GPIO +# define CYGHWR_HAL_LM3S_P_UART0_GPIO CYGHWR_HAL_LM3S_P_GPIOA +#endif + +#ifndef __ASSEMBLER__ + +__externC void hal_lm3s_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif + +//============================================================================= +// ADCs + +#ifdef CYGHWR_HAL_LM3S_ADC0_CHAN + +#define CYGHWR_HAL_LM3S_ADC_ACTSS 0x0 +#define CYGHWR_HAL_LM3S_ADC_RIS 0x4 +#define CYGHWR_HAL_LM3S_ADC_IMR 0x8 +#define CYGHWR_HAL_LM3S_ADC_ISCR 0xc +#define CYGHWR_HAL_LM3S_ADC_OSR 0x10 +#define CYGHWR_HAL_LM3S_ADC_EMUX 0x14 +#define CYGHWR_HAL_LM3S_ADC_USR 0x18 +#define CYGHWR_HAL_LM3S_ADC_SSPRI 0x20 +#define CYGHWR_HAL_LM3S_ADC_PSSI 0x28 +#define CYGHWR_HAL_LM3S_ADC_SAC 0x30 +#define CYGHWR_HAL_LM3S_ADC_SS_MUX0 0x40 +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0 0x44 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0 0x48 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR 0x4c +#define CYGHWR_HAL_LM3S_ADC_SS_MUX1 0x60 +#define CYGHWR_HAL_LM3S_ADC_SS_CTL1 0x64 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1 0x68 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1_SR 0x6c +#define CYGHWR_HAL_LM3S_ADC_SS_MUX2 0x80 +#define CYGHWR_HAL_LM3S_ADC_SS_CTL2 0x84 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2 0x88 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2_SR 0x8c +#define CYGHWR_HAL_LM3S_ADC_SS_MUX3 0xa0 +#define CYGHWR_HAL_LM3S_ADC_SS_CTL3 0xa4 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3 0xa8 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3_SR 0xac +#define CYGHWR_HAL_LM3S_ADC_TMLB 0x100 + +#define CYGHWR_HAL_LM3S_ADC_SAMPLE_SIZE 10 + +// Active Sample Sequencer +#define CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(__x) VALUE_(((__x)&3),1) + +// Raw Interrupt Status +#define CYGHWR_HAL_LM3S_ADC_RIS_INR(__x) VALUE_(((__x)&3),1) + +// Interrupt Mask Register +#define CYGHWR_HAL_LM3S_ADC_IMR_MASK(__x) VALUE_(((__x)&3),1) + +// Interrupt Status and Clear Register +#define CYGHWR_HAL_LM3S_ADC_ISCR_IN(__x) VALUE_(((__x)&3),1) + +// Overflow Status Register +#define CYGHWR_HAL_LM3S_ADC_OSR_OV(__x) VALUE_(((__x)&3),1) + +// Event Multiplexer Select +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_CTRL(__x) VALUE_((((__x)&3)<<2),0) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_AC0(__x) VALUE_((((__x)&3)<<2),1) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_EXT(__x) VALUE_((((__x)&3)<<2),4) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_TIMER(__x) VALUE_((((__x)&3)<<2),5) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM0(__x) VALUE_((((__x)&3)<<2),6) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM1(__x) VALUE_((((__x)&3)<<2),7) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM2(__x) VALUE_((((__x)&3)<<2),8) +#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_ALWS(__x) VALUE_((((__x)&3)<<2),15) + +// Underflow Status +#define CYGHWR_HAL_LM3S_ADC_USR_UV(__x) VALUE_(((__x)&3),1) + +// Sample Sequence Priority +#define CYGHWR_HAL_LM3S_ADC_SSPRI_SS(__x, __y) VALUE_((((__x)&3)<<2),(__y)&3) + +// Processor Sample Sequence Initiate +#define CYGHWR_HAL_LM3S_ADC_PSSI_SS(__x) VALUE_(((__x)&3),1) + +// Sample Averaging Control +#define CYGHWR_HAL_LM3S_ADC_SAC_NO_OVER 0x0 +#define CYGHWR_HAL_LM3S_ADC_SAC_2X 0x1 +#define CYGHWR_HAL_LM3S_ADC_SAC_4X 0x2 +#define CYGHWR_HAL_LM3S_ADC_SAC_8X 0x3 +#define CYGHWR_HAL_LM3S_ADC_SAC_16X 0x4 +#define CYGHWR_HAL_LM3S_ADC_SAC_32X 0x5 +#define CYGHWR_HAL_LM3S_ADC_SAC_64X 0x6 + +// Sample Sequence Input Multiplexer Select 0 +#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_V(_p_, _x_) VALUE_((((_x_)&3)<<2),_p_) +#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_M(_x_) VALUE_((((_x_)&3)<<2), 0x3) + +// Sample Sequence Control 0 +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D0 BIT_(0) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END0 BIT_(1) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE0 BIT_(2) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS0 BIT_(3) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D1 BIT_(4) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END1 BIT_(5) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE1 BIT_(6) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS1 BIT_(7) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D2 BIT_(8) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END2 BIT_(9) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE2 BIT_(10) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS2 BIT_(11) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D3 BIT_(12) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END3 BIT_(13) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE3 BIT_(14) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS3 BIT_(15) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D4 BIT_(16) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END4 BIT_(17) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE4 BIT_(18) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS4 BIT_(19) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D5 BIT_(20) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END5 BIT_(21) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE5 BIT_(22) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS5 BIT_(23) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D6 BIT_(24) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END6 BIT_(25) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE6 BIT_(26) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS6 BIT_(27) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D7 BIT_(28) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END7 BIT_(29) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE7 BIT_(30) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS7 BIT_(31) + +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_MASK(_x_) VALUE_((((_x_)&3)<<2), 0x15) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D(_x_) VALUE_((((_x_)&3)<<2), 0x1) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END(_x_) VALUE_((((_x_)&3)<<2), 0x2) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE(_x_) VALUE_((((_x_)&3)<<2), 0x4) +#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS(_x_) VALUE_((((_x_)&3)<<2), 0x8) + +// Sequence FIFO Status +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_TPTR 0x0 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_HPTR 0x0 +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY BIT_(8) +#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_FULL BIT_(12) + +#endif // CYGHWR_HAL_LM3S_ADC0_CHAN + + +//============================================================================= +// SSI interface register definitions. + +#ifdef CYGHWR_HAL_LM3S_SSI_CHAN + +#define CYGHWR_HAL_LM3S_SSI_CR0 0x000 +#define CYGHWR_HAL_LM3S_SSI_CR1 0x004 +#define CYGHWR_HAL_LM3S_SSI_DR 0x008 +#define CYGHWR_HAL_LM3S_SSI_SR 0x00C +#define CYGHWR_HAL_LM3S_SSI_CPSR 0x010 +#define CYGHWR_HAL_LM3S_SSI_IM 0x014 +#define CYGHWR_HAL_LM3S_SSI_RIS 0x018 +#define CYGHWR_HAL_LM3S_SSI_MIS 0x01c +#define CYGHWR_HAL_LM3S_SSI_ICR 0x020 +#define CYGHWR_HAL_LM3S_SSI_PID4 0xfd0 +#define CYGHWR_HAL_LM3S_SSI_PID5 0xfd4 +#define CYGHWR_HAL_LM3S_SSI_PID6 0xfd8 +#define CYGHWR_HAL_LM3S_SSI_PID7 0xfdc +#define CYGHWR_HAL_LM3S_SSI_PID0 0xfe0 +#define CYGHWR_HAL_LM3S_SSI_PID1 0xfe4 +#define CYGHWR_HAL_LM3S_SSI_PID2 0xfe8 +#define CYGHWR_HAL_LM3S_SSI_PID3 0xfec +#define CYGHWR_HAL_LM3S_SSI_PCID0 0xff0 +#define CYGHWR_HAL_LM3S_SSI_PCID1 0xff4 +#define CYGHWR_HAL_LM3S_SSI_PCID2 0xff8 +#define CYGHWR_HAL_LM3S_SSI_PCID3 0xffc + + +// CR0 bits +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_4BIT VALUE_(0, 0x3) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_5BIT VALUE_(0, 0x4) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_6BIT VALUE_(0, 0x5) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_7BIT VALUE_(0, 0x6) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_8BIT VALUE_(0, 0x7) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_9BIT VALUE_(0, 0x8) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_10BIT VALUE_(0, 0x9) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_11BIT VALUE_(0, 0xa) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_12BIT VALUE_(0, 0xb) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_13BIT VALUE_(0, 0xc) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_14BIT VALUE_(0, 0xd) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_15BIT VALUE_(0, 0xe) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_16BIT VALUE_(0, 0xf) +#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_MASK 0x0000000f +#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_FSPIFF VALUE_(4, 0x0) +#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_TISSFF VALUE_(4, 0x1) +#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MFF VALUE_(4, 0x2) +#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MASK 0x00000030 +#define CYGHWR_HAL_LM3S_SSI_CR0_SPO BIT_(6) +#define CYGHWR_HAL_LM3S_SSI_CR0_SPH BIT_(7) +#define CYGHWR_HAL_LM3S_SSI_CR0_SCR(__x) VALUE_(8, ((__x)&0xff)) + +// CR1 bits +#define CYGHWR_HAL_LM3S_SSI_CR1_LBM BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_CR1_SSE BIT_(1) +#define CYGHWR_HAL_LM3S_SSI_CR1_MS BIT_(2) +#define CYGHWR_HAL_LM3S_SSI_CR1_SOD BIT_(3) + +// SR bits +#define CYGHWR_HAL_LM3S_SSI_SR_TFE BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_SR_TNF BIT_(1) +#define CYGHWR_HAL_LM3S_SSI_SR_RNE BIT_(2) +#define CYGHWR_HAL_LM3S_SSI_SR_RFF BIT_(3) +#define CYGHWR_HAL_LM3S_SSI_SR_BSY BIT_(4) + +// IM bits +#define CYGHWR_HAL_LM3S_SSI_IM_RORIM BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_IM_RTIM BIT_(1) +#define CYGHWR_HAL_LM3S_SSI_IM_RXIM BIT_(2) +#define CYGHWR_HAL_LM3S_SSI_IM_TXIM BIT_(3) + +// RIS bits +#define CYGHWR_HAL_LM3S_SSI_RIS_RORRIS BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_RIS_RTRIS BIT_(1) +#define CYGHWR_HAL_LM3S_SSI_RIS_RXRIS BIT_(2) +#define CYGHWR_HAL_LM3S_SSI_RIS_TXRIS BIT_(3) + +// MIS bits +#define CYGHWR_HAL_LM3S_SSI_MIS_RORMIS BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_MIS_RTMIS BIT_(1) +#define CYGHWR_HAL_LM3S_SSI_MIS_RXMIS BIT_(2) +#define CYGHWR_HAL_LM3S_SSI_MIS_TXMIS BIT_(3) + +// ICR bits +#define CYGHWR_HAL_LM3S_SSI_ICR_RORIC BIT_(0) +#define CYGHWR_HAL_LM3S_SSI_ICR_RTIC BIT_(1) + +#endif // CYGHWR_HAL_LM3S_SSI_CHAN + +//============================================================================= +// PWM register definitions. + +#ifdef CYGHWR_HAL_LM3S_PWM_CHAN + +#define CYGHWR_HAL_LM3S_PWM_CTL 0x000 +#define CYGHWR_HAL_LM3S_PWM_SYNC 0x004 +#define CYGHWR_HAL_LM3S_PWM_ENABLE 0x008 +#define CYGHWR_HAL_LM3S_PWM_INVERT 0x00c +#define CYGHWR_HAL_LM3S_PWM_FAULT 0x010 +#define CYGHWR_HAL_LM3S_PWM_INTEN 0x014 +#define CYGHWR_HAL_LM3S_PWM_RIS 0x018 +#define CYGHWR_HAL_LM3S_PWM_ISC 0x01c +#define CYGHWR_HAL_LM3S_PWM_STATUS 0x020 + +#define CYGHWR_HAL_LM3S_PWM0_CTL 0x040 +#define CYGHWR_HAL_LM3S_PWM0_INTEN 0x044 +#define CYGHWR_HAL_LM3S_PWM0_RIS 0x048 +#define CYGHWR_HAL_LM3S_PWM0_ISC 0x04c +#define CYGHWR_HAL_LM3S_PWM0_LOAD 0x050 +#define CYGHWR_HAL_LM3S_PWM0_COUNT 0x054 +#define CYGHWR_HAL_LM3S_PWM0_CMPA 0x058 +#define CYGHWR_HAL_LM3S_PWM0_CMPB 0x05c +#define CYGHWR_HAL_LM3S_PWM0_GENA 0x060 +#define CYGHWR_HAL_LM3S_PWM0_GENB 0x064 +#define CYGHWR_HAL_LM3S_PWM0_DBCTL 0x068 +#define CYGHWR_HAL_LM3S_PWM0_DBRISE 0x06c +#define CYGHWR_HAL_LM3S_PWM0_DBFALL 0x070 + +#define CYGHWR_HAL_LM3S_PWM1_CTL 0x080 +#define CYGHWR_HAL_LM3S_PWM1_INTEN 0x084 +#define CYGHWR_HAL_LM3S_PWM1_RIS 0x088 +#define CYGHWR_HAL_LM3S_PWM1_ISC 0x08c +#define CYGHWR_HAL_LM3S_PWM1_LOAD 0x090 +#define CYGHWR_HAL_LM3S_PWM1_COUNT 0x094 +#define CYGHWR_HAL_LM3S_PWM1_CMPA 0x098 +#define CYGHWR_HAL_LM3S_PWM1_CMPB 0x09c +#define CYGHWR_HAL_LM3S_PWM1_GENA 0x0a0 +#define CYGHWR_HAL_LM3S_PWM1_GENB 0x0a4 +#define CYGHWR_HAL_LM3S_PWM1_DBCTL 0x0a8 +#define CYGHWR_HAL_LM3S_PWM1_DBRISE 0x0ac +#define CYGHWR_HAL_LM3S_PWM1_DBFALL 0x0b0 + +#define CYGHWR_HAL_LM3S_PWM2_CTL 0x0c0 +#define CYGHWR_HAL_LM3S_PWM2_INTEN 0x0c4 +#define CYGHWR_HAL_LM3S_PWM2_RIS 0x0c8 +#define CYGHWR_HAL_LM3S_PWM2_ISC 0x0cc +#define CYGHWR_HAL_LM3S_PWM2_LOAD 0x0d0 +#define CYGHWR_HAL_LM3S_PWM2_COUNT 0x0d4 +#define CYGHWR_HAL_LM3S_PWM2_CMPA 0x0d8 +#define CYGHWR_HAL_LM3S_PWM2_CMPB 0x0dc +#define CYGHWR_HAL_LM3S_PWM2_GENA 0x0e0 +#define CYGHWR_HAL_LM3S_PWM2_GENB 0x0e4 +#define CYGHWR_HAL_LM3S_PWM2_DBCTL 0x0e8 +#define CYGHWR_HAL_LM3S_PWM2_DBRISE 0x0ec +#define CYGHWR_HAL_LM3S_PWM2_DBFALL 0x0f0 + + +// CTL bits +#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC2 BIT_(2) + +// SYNC bits +#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC2 BIT_(2) + +// ENABLE bits +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM3 BIT_(3) +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM4 BIT_(4) +#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM5 BIT_(5) + +// INVERT bits +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM3 BIT_(3) +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM4 BIT_(4) +#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM5 BIT_(5) + +// FAULT bits +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM3 BIT_(3) +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM4 BIT_(4) +#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM5 BIT_(5) + +// INTEN bits +#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_INTEN_FAULT BIT_(16) + +// RIS bits +#define CYGHWR_HAL_LM3S_PWM_RIS_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_RIS_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_RIS_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_RIS_FAULT BIT_(16) + +// ISC bits +#define CYGHWR_HAL_LM3S_PWM_ISC_PWM0 BIT_(0) +#define CYGHWR_HAL_LM3S_PWM_ISC_PWM1 BIT_(1) +#define CYGHWR_HAL_LM3S_PWM_ISC_PWM2 BIT_(2) +#define CYGHWR_HAL_LM3S_PWM_ISC_FAULT BIT_(16) + +// STATUS bits +#define CYGHWR_HAL_LM3S_PWM_STATUS_FAULT BIT_(0) + +// PWMx CTL Bits +#define CYGHWR_HAL_LM3S_PWMx_CTL_ENABLE BIT_(0) +#define CYGHWR_HAL_LM3S_PWMx_CTL_MODE BIT_(1) +#define CYGHWR_HAL_LM3S_PWMx_CTL_DEBUG BIT_(2) +#define CYGHWR_HAL_LM3S_PWMx_CTL_LOAD_UPD BIT_(3) +#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPA_UPD BIT_(4) +#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPB_UPD BIT_(5) + +// PWMx INTEN Bits +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_ZERO BIT_(0) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_LOAD BIT_(1) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_UP BIT_(2) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_DOWN BIT_(3) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_UP BIT_(4) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_DOWN BIT_(5) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_ZERO BIT_(8) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_LOAD BIT_(9) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_UP BIT_(10) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_DOWN BIT_(11) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_UP BIT_(12) +#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_DOWN BIT_(13) + +// PWMx RIS Bits +#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_ZERO BIT_(0) +#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_LOAD BIT_(1) +#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_UP BIT_(2) +#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_DOWN BIT_(3) +#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_UP BIT_(4) +#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_DOWN BIT_(5) + +// PWMx ISC Bits +#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_ZERO BIT_(0) +#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_LOAD BIT_(1) +#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_UP BIT_(2) +#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_DOWN BIT_(3) +#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_UP BIT_(4) +#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_DOWN BIT_(5) + +// PWMx GENA Bits +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_NONE VALUE_(0, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_INVS VALUE_(0, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET0 VALUE_(0, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET1 VALUE_(0, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_MASK 0x00000003 +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_NONE VALUE_(2, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_INVS VALUE_(2, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET0 VALUE_(2, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET1 VALUE_(2, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_MASK 0x0000000c +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_NONE VALUE_(4, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_INVS VALUE_(4, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET0 VALUE_(4, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET1 VALUE_(4, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_MASK 0x00000030 +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_NONE VALUE_(6, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_INVS VALUE_(6, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET0 VALUE_(6, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET1 VALUE_(6, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_MASK 0x000000c0 +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_NONE VALUE_(8, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_INVS VALUE_(8, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET0 VALUE_(8, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET1 VALUE_(8, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_MASK 0x00000300 +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_NONE VALUE_(10, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_INVS VALUE_(10, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET0 VALUE_(10, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET1 VALUE_(10, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_MASK 0x00000c00 + +// PWMx GENB Bits +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_NONE VALUE_(0, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_INVS VALUE_(0, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET0 VALUE_(0, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET1 VALUE_(0, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_MASK 0x00000003 +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_NONE VALUE_(2, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_INVS VALUE_(2, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET0 VALUE_(2, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET1 VALUE_(2, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_MASK 0x0000000c +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_NONE VALUE_(4, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_INVS VALUE_(4, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET0 VALUE_(4, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET1 VALUE_(4, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_MASK 0x00000030 +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_NONE VALUE_(6, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_INVS VALUE_(6, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET0 VALUE_(6, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET1 VALUE_(6, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_MASK 0x000000c0 +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_NONE VALUE_(8, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_INVS VALUE_(8, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET0 VALUE_(8, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET1 VALUE_(8, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_MASK 0x00000300 +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_NONE VALUE_(10, 0x0) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_INVS VALUE_(10, 0x1) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET0 VALUE_(10, 0x2) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET1 VALUE_(10, 0x3) +#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_MASK 0x00000c00 + +// PWMx DBCTL Bits +#define CYGHWR_HAL_LM3S_PWMx_DBCTL_ENABLE BIT_(0) + +#endif // CYGHWR_HAL_LM3S_PWM_CHAN + + +//============================================================================= +// Global Timers register definitions. + +#define CYGHWR_HAL_LM3S_GPTIM_CFG 0x000 +#define CYGHWR_HAL_LM3S_GPTIM_TAMR 0x004 +#define CYGHWR_HAL_LM3S_GPTIM_TBMR 0x008 +#define CYGHWR_HAL_LM3S_GPTIM_CTL 0x00c +#define CYGHWR_HAL_LM3S_GPTIM_IMR 0x018 +#define CYGHWR_HAL_LM3S_GPTIM_RIS 0x01C +#define CYGHWR_HAL_LM3S_GPTIM_MIS 0x020 +#define CYGHWR_HAL_LM3S_GPTIM_ICR 0x024 +#define CYGHWR_HAL_LM3S_GPTIM_TAILR 0x028 +#define CYGHWR_HAL_LM3S_GPTIM_TBILR 0x02c +#define CYGHWR_HAL_LM3S_GPTIM_TAMATCHR 0x030 +#define CYGHWR_HAL_LM3S_GPTIM_TBMATCHR 0x034 +#define CYGHWR_HAL_LM3S_GPTIM_TAPR 0x038 +#define CYGHWR_HAL_LM3S_GPTIM_TBPR 0x03c +#define CYGHWR_HAL_LM3S_GPTIM_TAPMR 0x040 +#define CYGHWR_HAL_LM3S_GPTIM_TBPMR 0x044 +#define CYGHWR_HAL_LM3S_GPTIM_TAR 0x048 +#define CYGHWR_HAL_LM3S_GPTIM_TBR 0x04c + +// CFG bits +#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT VALUE_(0, 0x0) +#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT_RTC VALUE_(0, 0x1) +#define CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT VALUE_(0, 0x4) +#define CYGHWR_HAL_LM3S_GPTIM_CFG_MASK 0x00000007 + +// TAMR bits +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_ONE_SHOT VALUE_(0, 0x1) +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC VALUE_(0, 0x2) +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_CAPTURE VALUE_(0, 0x3) +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_MASK 0x00000003 +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TACMR BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TAAMS BIT_(3) + +// TBMR bits +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_ONE_SHOT VALUE_(0, 0x1) +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_PERIODIC VALUE_(0, 0x2) +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_CAPTURE VALUE_(0, 0x3) +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_MASK 0x00000003 +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBCMR BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBAMS BIT_(3) + +// CTL bits +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN BIT_(0) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TASTALL BIT_(1) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_POS VALUE_(2, 0x0) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_NEG VALUE_(2, 0x1) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_BOTH VALUE_(2, 0x3) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_RTCEN BIT_(4) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE BIT_(5) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAPWML BIT_(6) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEN BIT_(8) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBSTALL BIT_(9) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_POS VALUE_(10, 0x0) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_NEG VALUE_(10, 0x1) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_BOTH VALUE_(10, 0x3) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBOTE BIT_(13) +#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBPWML BIT_(14) + +// IMR bits +#define CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM BIT_(0) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAMIM BIT_(1) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAEIM BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_RTCIM BIT_(3) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_TBTOIM BIT_(8) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBMIM BIT_(9) +#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBEIM BIT_(10) + +// RIS bits +#define CYGHWR_HAL_LM3S_GPTIM_RIS_TATORIS BIT_(0) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAMRIS BIT_(1) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAERIS BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_RTCRIS BIT_(3) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_TBTORIS BIT_(8) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBMRIS BIT_(9) +#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBERIS BIT_(10) + +// MIS bits +#define CYGHWR_HAL_LM3S_GPTIM_MIS_TATOMIS BIT_(0) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAMMIS BIT_(1) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAEMIS BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_RTCMIS BIT_(3) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_TBTOMIS BIT_(8) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBMMIS BIT_(9) +#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBEMIS BIT_(10) + +// ICR bits +#define CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT BIT_(0) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAMCINT BIT_(1) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAECINT BIT_(2) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_RTCCINT BIT_(3) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_TBTOCINT BIT_(8) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBMCINT BIT_(9) +#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBECINT BIT_(10) + +cyg_uint32 hal_lm3s_timer_clock( void ); + +#ifndef __ASSEMBLER__ + +__externC cyg_uint32 hal_stellaris_lm3s_timer_clock( CYG_ADDRESS base ); + +#endif + + +//============================================================================= +// I2C register definitions. + +#ifdef CYGHWR_HAL_LM3S_I2C_CHAN + +#define CYGHWR_HAL_LM3S_I2C_MSA 0x000 +#define CYGHWR_HAL_LM3S_I2C_MCS 0x004 +#define CYGHWR_HAL_LM3S_I2C_MDR 0x008 +#define CYGHWR_HAL_LM3S_I2C_MTPR 0x00c +#define CYGHWR_HAL_LM3S_I2C_MIMR 0x010 +#define CYGHWR_HAL_LM3S_I2C_MRIS 0x014 +#define CYGHWR_HAL_LM3S_I2C_MMIS 0x018 +#define CYGHWR_HAL_LM3S_I2C_MICR 0x01c +#define CYGHWR_HAL_LM3S_I2C_MCR 0x020 + +#define CYGHWR_HAL_LM3S_I2C_SOAR 0x000 +#define CYGHWR_HAL_LM3S_I2C_SCSR 0x004 +#define CYGHWR_HAL_LM3S_I2C_SDR 0x008 +#define CYGHWR_HAL_LM3S_I2C_SIMR 0x00c +#define CYGHWR_HAL_LM3S_I2C_SRIS 0x010 +#define CYGHWR_HAL_LM3S_I2C_SMIS 0x014 +#define CYGHWR_HAL_LM3S_I2C_SICR 0x018 + +// MSA bits +#define CYGHWR_HAL_LM3S_I2C_MSA_RS BIT_(0) +#define CYGHWR_HAL_LM3S_I2C_MSA_SA(__x) VALUE_(1, __x) + +// MCS bits +#define CYGHWR_HAL_LM3S_I2C_MCS_BUSY BIT_(0) +#define CYGHWR_HAL_LM3S_I2C_MCS_ERR BIT_(1) +#define CYGHWR_HAL_LM3S_I2C_MCS_ADRACK BIT_(2) +#define CYGHWR_HAL_LM3S_I2C_MCS_DATACK BIT_(3) +#define CYGHWR_HAL_LM3S_I2C_MCS_ARBLST BIT_(4) +#define CYGHWR_HAL_LM3S_I2C_MCS_IDLE BIT_(5) +#define CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY BIT_(6) + +#define CYGHWR_HAL_LM3S_I2C_MCS_RUN BIT_(0) +#define CYGHWR_HAL_LM3S_I2C_MCS_START BIT_(1) +#define CYGHWR_HAL_LM3S_I2C_MCS_STOP BIT_(2) +#define CYGHWR_HAL_LM3S_I2C_MCS_ACK BIT_(3) + +// MIMR bits +#define CYGHWR_HAL_LM3S_I2C_MIMR_IM BIT_(0) + +// MRIS bits +#define CYGHWR_HAL_LM3S_I2C_MRIS_RIS BIT_(0) + +// MMIS bits +#define CYGHWR_HAL_LM3S_I2C_MMIS_MIS BIT_(0) + +// MICR bits +#define CYGHWR_HAL_LM3S_I2C_MICR_IC BIT_(0) + +// MCR bits +#define CYGHWR_HAL_LM3S_I2C_MCR_LPBK BIT_(0) +#define CYGHWR_HAL_LM3S_I2C_MCR_MFE BIT_(4) +#define CYGHWR_HAL_LM3S_I2C_MCR_SFE BIT_(5) + +// SCSR bits +#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_RREQ BIT_(0) +#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_TREQ BIT_(1) +#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_FBR BIT_(2) + +#define CYGHWR_HAL_LM3S_I2C_SCSR_WRITE_DA BIT_(0) + +// SIMR bits +#define CYGHWR_HAL_LM3S_I2C_SIMR_DATAIM BIT_(0) + +// SRIS bits +#define CYGHWR_HAL_LM3S_I2C_SRIS_DATARIS BIT_(0) + +// SMIS bits +#define CYGHWR_HAL_LM3S_I2C_SMIS_DATAMIS BIT_(0) + +// SICR bits +#define CYGHWR_HAL_LM3S_I2C_SICR_DATAMIC BIT_(0) + +__externC cyg_uint32 hal_lm3s_i2c_clock( void ); + +#endif // CYGHWR_HAL_LM3S_I2C_CHAN + + +//============================================================================= +// AC register definitions. + +#ifdef CYGHWR_HAL_LM3S_AC_CHAN + +#define CYGHWR_HAL_LM3S_AC_MIS 0x000 +#define CYGHWR_HAL_LM3S_AC_RIS 0x004 +#define CYGHWR_HAL_LM3S_AC_INTEN 0x008 +#define CYGHWR_HAL_LM3S_AC_REFCTL 0x010 +#define CYGHWR_HAL_LM3S_AC_STAT0 0x020 +#define CYGHWR_HAL_LM3S_AC_CTL0 0x024 +#define CYGHWR_HAL_LM3S_AC_STAT1 0x040 +#define CYGHWR_HAL_LM3S_AC_CTL1 0x044 +#define CYGHWR_HAL_LM3S_AC_STAT2 0x060 +#define CYGHWR_HAL_LM3S_AC_CTL2 0x064 + +// MIS bits +#define CYGHWR_HAL_LM3S_AC_MIS_IN0 BIT_(0) +#define CYGHWR_HAL_LM3S_AC_MIS_IN1 BIT_(1) +#define CYGHWR_HAL_LM3S_AC_MIS_IN2 BIT_(2) + +// RIS bits +#define CYGHWR_HAL_LM3S_AC_RIS_IN0 BIT_(0) +#define CYGHWR_HAL_LM3S_AC_RIS_IN1 BIT_(1) +#define CYGHWR_HAL_LM3S_AC_RIS_IN2 BIT_(2) + +// INTEN bits +#define CYGHWR_HAL_LM3S_AC_INTEN_IN0 BIT_(0) +#define CYGHWR_HAL_LM3S_AC_INTEN_IN1 BIT_(1) +#define CYGHWR_HAL_LM3S_AC_INTEN_IN2 BIT_(2) + +// REFCTL bits +#define CYGHWR_HAL_LM3S_AC_REFCTL_RNG BIT_(8) +#define CYGHWR_HAL_LM3S_AC_REFCTL_EN BIT_(9) + +// STAT0, STAT1 and STAT2 bits +#define CYGHWR_HAL_LM3S_AC_STATx_OVAL BIT_(1) + +// CTL0, CTL1 anf CTL2 bits +#define CYGHWR_HAL_LM3S_AC_CTLx_CINV BIT_(1) +#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_LEV_SENSE VALUE_(2, 0x0) +#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_FALL_EDGE VALUE_(2, 0x1) +#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_RISE_EDGE VALUE_(2, 0x2) +#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_BOTH_EDGE VALUE_(2, 0x3) +#define CYGHWR_HAL_LM3S_AC_CTLx_ISLVAL BIT_(4) +#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL VALUE_(9, 0x0) +#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL_C0 VALUE_(9, 0x1) +#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_IVOLTREF VALUE_(9, 0x2) + +#endif // CYGHWR_HAL_LM3S_AC_CHAN + + +//============================================================================= +// QEI register definitions. + +#ifdef CYGHWR_HAL_LM3S_QEI_CHAN + +#define CYGHWR_HAL_LM3S_QEI_CTL 0x000 +#define CYGHWR_HAL_LM3S_QEI_STAT 0x004 +#define CYGHWR_HAL_LM3S_QEI_POS 0x008 +#define CYGHWR_HAL_LM3S_QEI_MAXPOS 0x00c +#define CYGHWR_HAL_LM3S_QEI_LOAD 0x010 +#define CYGHWR_HAL_LM3S_QEI_TIME 0x014 +#define CYGHWR_HAL_LM3S_QEI_COUNT 0x018 +#define CYGHWR_HAL_LM3S_QEI_SPEED 0x01c +#define CYGHWR_HAL_LM3S_QEI_INTEN 0x020 +#define CYGHWR_HAL_LM3S_QEI_RIS 0x024 +#define CYGHWR_HAL_LM3S_QEI_ISC 0x028 + +// CTL bits +#define CYGHWR_HAL_LM3S_QEI_CTL_EN BIT_(0) +#define CYGHWR_HAL_LM3S_QEI_CTL_SWAP BIT_(1) +#define CYGHWR_HAL_LM3S_QEI_CTL_SIGMODE BIT_(2) +#define CYGHWR_HAL_LM3S_QEI_CTL_CAPMODE BIT_(3) +#define CYGHWR_HAL_LM3S_QEI_CTL_RESMODE BIT_(4) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELEN BIT_(5) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_1 VALUE_(6, 0x0) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_2 VALUE_(6, 0x1) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_4 VALUE_(6, 0x2) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_8 VALUE_(6, 0x3) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_16 VALUE_(6, 0x4) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_32 VALUE_(6, 0x5) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_64 VALUE_(6, 0x6) +#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_128 VALUE_(6, 0x7) +#define CYGHWR_HAL_LM3S_QEI_CTL_INVA BIT_(9) +#define CYGHWR_HAL_LM3S_QEI_CTL_INVB BIT_(10) +#define CYGHWR_HAL_LM3S_QEI_CTL_INVI BIT_(11) +#define CYGHWR_HAL_LM3S_QEI_CTL_SATLLEN BIT_(12) + +// STAT bits +#define CYGHWR_HAL_LM3S_QEI_STAT_ERR BIT_(0) +#define CYGHWR_HAL_LM3S_QEI_STAT_DIR BIT_(1) + +// INTEN bits +#define CYGHWR_HAL_LM3S_QEI_INTEN_INTINDEX BIT_(0) +#define CYGHWR_HAL_LM3S_QEI_INTEN_INTTIMER BIT_(1) +#define CYGHWR_HAL_LM3S_QEI_INTEN_INTDIR BIT_(2) +#define CYGHWR_HAL_LM3S_QEI_INTEN_INTERROR BIT_(3) + +// RIS bits +#define CYGHWR_HAL_LM3S_QEI_RIS_INTINDEX BIT_(0) +#define CYGHWR_HAL_LM3S_QEI_RIS_INTTIMER BIT_(1) +#define CYGHWR_HAL_LM3S_QEI_RIS_INTDIR BIT_(2) +#define CYGHWR_HAL_LM3S_QEI_RIS_INTERROR BIT_(3) + +// ISC bits +#define CYGHWR_HAL_LM3S_QEI_ISC_INTINDEX BIT_(0) +#define CYGHWR_HAL_LM3S_QEI_ISC_INTTIMER BIT_(1) +#define CYGHWR_HAL_LM3S_QEI_ISC_INTDIR BIT_(2) +#define CYGHWR_HAL_LM3S_QEI_ISC_INTERROR BIT_(3) + +#endif // CYGHWR_HAL_LM3S_QEI_CHAN + + +//============================================================================= +// Flash controller + +#define CYGHWR_HAL_LM3S_FMC_FMA 0x000 +#define CYGHWR_HAL_LM3S_FMC_FMD 0x004 +#define CYGHWR_HAL_LM3S_FMC_FMC 0x008 +#define CYGHWR_HAL_LM3S_FMC_FCRIS 0x00c +#define CYGHWR_HAL_LM3S_FMC_FCIM 0x010 +#define CYGHWR_HAL_LM3S_FMC_FCMISC 0x014 + +// Key value +#define CYGHWR_HAL_LM3S_FMC_WRKEY 0xA4420000 + +// FMC bits +#define CYGHWR_HAL_LM3S_FMC_FMC_WRITE BIT_(0) +#define CYGHWR_HAL_LM3S_FMC_FMC_ERASE BIT_(1) +#define CYGHWR_HAL_LM3S_FMC_FMC_MERASE BIT_(2) +#define CYGHWR_HAL_LM3S_FMC_FMC_COMT BIT_(3) + +// RIS bits +#define CYGHWR_HAL_LM3S_FMC_FCRIS_ARIS BIT_(0) +#define CYGHWR_HAL_LM3S_FMC_FCRIS_PRIS BIT_(1) + +// IM bits +#define CYGHWR_HAL_LM3S_FMC_FCIM_AMASK BIT_(0) +#define CYGHWR_HAL_LM3S_FMC_FCIM_PMASK BIT_(1) + +// MISC bits +#define CYGHWR_HAL_LM3S_FMC_FCMISC_AMASK BIT_(0) +#define CYGHWR_HAL_LM3S_FMC_FCMISC_PMASK BIT_(0) + + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_IO_H +// EOF of var_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/include/variant.inc @@ -0,0 +1,54 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2010-11-23 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_lm3s.h> + +//========================================================================== +// EOF variant.inc +
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c @@ -0,0 +1,406 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010 +// 2011, Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): original: nickg, ccoutand: updated for Stellaris HAL +// Date: 2011-01-18 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // Tracing + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/var_io.h> // USART registers + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + int isr_vector; + cyg_uint32 rxpin; + cyg_uint32 txpin; + cyg_uint32 baud_rate; + int irq_state; +} channel_data_t; + +static channel_data_t lm3s_ser_channels[] = { +#if CYGINT_HAL_CORTEXM_LM3S_UART0>0 + {0, CYGHWR_HAL_LM3S_UART0, 1000, CYGNUM_HAL_INTERRUPT_UART0, + CYGHWR_HAL_LM3S_UART0_RX, CYGHWR_HAL_LM3S_UART0_TX}, +#endif +#if CYGINT_HAL_CORTEXM_LM3S_UART1>0 + {1, CYGHWR_HAL_LM3S_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, + CYGHWR_HAL_LM3S_UART1_RX, CYGHWR_HAL_LM3S_UART1_TX}, +#endif +}; + +//----------------------------------------------------------------------------- + +static void +hal_lm3s_serial_init_channel(void *__ch_data) +{ + channel_data_t *chan = (channel_data_t *) __ch_data; + CYG_ADDRESS base = chan->base; + cyg_uint32 lcrh, + ctl; + + // Disable UART + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl); + ctl &= ~(CYGHWR_HAL_LM3S_UART_CTL_UARTEN | + CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl); + + // Enable the PIO lines for the serial channel + CYGHWR_HAL_LM3S_GPIO_SET(chan->rxpin); + CYGHWR_HAL_LM3S_GPIO_SET(chan->txpin); + + // Set up Baud rate + chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; + hal_lm3s_uart_setbaud(base, chan->baud_rate); + + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, 0); + + // 8 bits - 1 stop - Enable FIFO + lcrh = CYGHWR_HAL_LM3S_UART_LCRH_WLEN(3) | CYGHWR_HAL_LM3S_UART_LCRH_FEN; + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_LCRH, lcrh); + + // Enable the UART + ctl = (CYGHWR_HAL_LM3S_UART_CTL_UARTEN | + CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl); +} + +void +hal_lm3s_serial_putc(void *__ch_data, char c) +{ + CYG_ADDRESS base = ((channel_data_t *) __ch_data)->base; + cyg_uint32 sr; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, sr); + } while ((sr & CYGHWR_HAL_LM3S_UART_FR_TXFE) == 0); + + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +hal_lm3s_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch) +{ + CYG_ADDRESS base = ((channel_data_t *) __ch_data)->base; + cyg_uint32 fr; + cyg_uint32 c; + + CYGARC_HAL_SAVE_GP(); + + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, fr); + + if ((fr & CYGHWR_HAL_LM3S_UART_FR_RXFE)) + return false; + + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c); + + *ch = (cyg_uint8)c; + + CYGARC_HAL_RESTORE_GP(); + + return true; +} + +cyg_uint8 +hal_lm3s_serial_getc(void *__ch_data) +{ + cyg_uint8 ch; + + CYGARC_HAL_SAVE_GP(); + + while (!hal_lm3s_serial_getc_nonblock(__ch_data, &ch)) + continue; + + CYGARC_HAL_RESTORE_GP(); + + return ch; +} + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void +hal_lm3s_serial_write(void *__ch_data, const cyg_uint8 *__buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while (__len-- > 0) + hal_lm3s_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +hal_lm3s_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while (__len-- > 0) + *__buf++ = hal_lm3s_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +hal_lm3s_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch) +{ + int delay_count; + channel_data_t *chan = (channel_data_t *) __ch_data; + cyg_bool res; + + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 100; // delay in 10 us steps + + for (;;) { + res = hal_lm3s_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(10); + } + + CYGARC_HAL_RESTORE_GP(); + + return res; +} + +static int +hal_lm3s_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t *chan = (channel_data_t *) __ch_data; + CYG_ADDRESS base = ((channel_data_t *) __ch_data)->base; + int ret = 0; + cyg_uint32 im; + + va_list ap; + + CYGARC_HAL_SAVE_GP(); + + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im); + im |= CYGHWR_HAL_LM3S_UART_IM_RXIM; + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im); + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im); + im &= ~CYGHWR_HAL_LM3S_UART_IM_RXIM; + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + hal_lm3s_uart_setbaud(base, chan->baud_rate); + ret = 0; + break; + default: + break; + } + + va_end(ap); + + CYGARC_HAL_RESTORE_GP(); + + return ret; +} + +static int +hal_lm3s_serial_isr(void *__ch_data, int *__ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + channel_data_t *chan = (channel_data_t *) __ch_data; + cyg_uint8 ch; + + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + if (hal_lm3s_serial_getc_nonblock(__ch_data, &ch)) { + if (cyg_hal_is_break((char *)&ch, 1)) + *__ctrlc = 1; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + + return 1; +} + +static void +hal_lm3s_serial_init(void) +{ + hal_virtual_comm_table_t *comm; + int cur; + int i; + + cur = + CYGACC_CALL_IF_SET_CONSOLE_COMM + (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) { + hal_lm3s_serial_init_channel(&lm3s_ser_channels[i]); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &lm3s_ser_channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, hal_lm3s_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, hal_lm3s_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, hal_lm3s_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, hal_lm3s_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, hal_lm3s_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_lm3s_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_lm3s_serial_getc_timeout); + } + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + +# if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + // Set debug channel baud rate if different + lm3s_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate(&lm3s_ser_channels + [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]); +# endif + +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + hal_lm3s_serial_init(); +} + +#endif // ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + + +//============================================================================= +// Non-Virtual vector HAL diagnostics + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void +hal_lm3s_diag_init(void) +{ + hal_lm3s_serial_init(&lm3s_ser_channels + [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]); +} + +void +hal_lm3s_diag_putc(char c) +{ + hal_lm3s_serial_putc(&lm3s_ser_channels + [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 +hal_lm3s_diag_getc(void) +{ + return + hal_lm3s_serial_getc(&lm3s_ser_channels + [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]); +} + +#endif // ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// EOF hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c @@ -0,0 +1,328 @@ +//========================================================================== +// +// lm3s_misc.c +// +// Stellaris Cortex-M3 variant HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ccoutand +// Date: 2011-01-18 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // Tracing macros +#include <cyg/infra/cyg_ass.h> // Assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +//========================================================================== +// Initialization +// +__externC void hal_start_clocks(void); + +// Clock computation must be done per Variant basis +cyg_uint32 hal_cortexm_systick_clock; +cyg_uint32 hal_lm3s_sysclk; + + +void +hal_variant_init(void) +{ +#if !defined(CYG_HAL_STARTUP_RAM) + hal_start_clocks(); +#endif + + // All LM3S devices use PORTA 0/1 for UART0 +#if CYGINT_HAL_CORTEXM_LM3S_UART0>0 + CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0, 1); + CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0_GPIO, 1); +#endif + +#if CYGINT_HAL_CORTEXM_LM3S_UART1>0 + +# ifdef CYGHWR_HAL_LM3S_P_UART1_GPIO + CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1, 1); + CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1_GPIO, 1); +# else +# error "Variant/Platform does not specify UART1 GPIO Port" +# endif + +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +} + +//========================================================================== +// GPIO support +// +// These functions provide configuration and IO for GPIO pins. +// + +__externC void +hal_lm3s_gpio_set(cyg_uint32 pin) +{ + cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin); + cyg_uint32 bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin)); + cyg_uint32 cm = CYGHWR_HAL_LM3S_GPIO_CFG(pin); + cyg_uint32 mode = CYGHWR_HAL_LM3S_GPIO_MODE(pin); + cyg_uint32 irq = CYGHWR_HAL_LM3S_GPIO_IRQ(pin); + cyg_uint32 st = CYGHWR_HAL_LM3S_GPIO_STRENGTH(pin); + cyg_uint32 reg, + dir, + im, + dr2r, + dr4r, + dr8r; + + if (pin == CYGHWR_HAL_LM3S_GPIO_NONE) + return; + + /* + * Handle IO mode settings + */ + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, reg); + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, dir); + + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg & ~(bit))); + if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_IN) + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir & ~(bit))); + else if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_OUT) + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir | bit)); + else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg | bit)); + + /* + * Handle IO configuration + */ + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, reg); + if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP || + cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP || + cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg | bit)); + } else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg & ~(bit))); + + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, reg); + if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP || + cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg | bit)); + } else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg & ~(bit))); + + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, reg); + if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN || + cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg | bit)); + } else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg & ~(bit))); + + /* + * Handle IO strength + */ + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, dr2r); + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, dr4r); + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, dr8r); + if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r | bit)); + } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r | bit)); + } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit))); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r | bit)); + } + + /* + * Handle interrupt settings + */ + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, im); + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im & ~(bit))); + if (irq != CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE) { + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, reg); + + if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL || + irq == CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL) + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg | bit)); + else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg & ~(bit))); + + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, reg); + if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES) { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg | bit)); + } else { + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg & ~(bit))); + + HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, reg); + if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL || + irq == CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE) + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, + (reg & ~(bit))); + else + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, + (reg | bit)); + } + + HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im | bit)); + } +} + +__externC void +hal_lm3s_gpio_out(cyg_uint32 pin, int val) +{ + cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin); + int bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin)); + + port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2)); + + HAL_WRITE_UINT32(port, (val ? bit : 0)); +} + +__externC void +hal_lm3s_gpio_in(cyg_uint32 pin, int *val) +{ + cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin); + int bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin)); + cyg_uint32 pd; + + port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2)); + + HAL_READ_UINT32(port, pd); + *val = pd; +} + + +//========================================================================== +// Peripheral support +// + +__externC void +hal_lm3s_periph_set(cyg_uint32 periph, cyg_uint32 on_off) +{ + cyg_uint32 reg; + + if (CYGHWR_HAL_LM3S_PERIPH_GC0 & periph) { + HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg); + if (on_off) + reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0); + else + reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0); + HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg); + } + + if (CYGHWR_HAL_LM3S_PERIPH_GC1 & periph) { + HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg); + if (on_off) + reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1); + else + reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1); + HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg); + } + + if (CYGHWR_HAL_LM3S_PERIPH_GC2 & periph) { + HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg); + if (on_off) + reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2); + else + reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2); + HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg); + } + +} + + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current APB clock settings. +// + +__externC void +hal_lm3s_uart_setbaud(cyg_uint32 base, cyg_uint32 baud) +{ + cyg_uint32 int_div, + frac_div; + + int_div = ((((hal_cortexm_systick_clock << 3) / baud) + 1) >> 1); + + frac_div = int_div % 64; + int_div = int_div >> 6; + + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IBRD, int_div); + HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FBRD, frac_div); +} + + +//========================================================================== +// I2C clock rate +// +__externC cyg_uint32 +hal_lm3s_i2c_clock(void) +{ + return hal_lm3s_sysclk; +} + +//========================================================================== +// Timer clock rate +// +__externC cyg_uint32 +hal_lm3s_timer_clock(void) +{ + return hal_lm3s_sysclk; +} + +//========================================================================== +// EOF lm3s_misc_misc.c