Mercurial > ecos
changeset 2653:db7fabbb8c79
Contribute eCosCentric's m5272c3 platform HAL
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new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/ChangeLog @@ -0,0 +1,198 @@ +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl, doc/m5272c3.sgml, include/plf.inc, + include/plf_io.h, src/platform.c: minor clean-ups. + +2007-09-14 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl, misc/redboot_DBUG.ecm, + misc/redboot_RAM.ecm, misc/redboot_ROM.ecm, + misc/redboot_ROMFFE.ecm : the V2 AMD driver requires an erase + burst duration of at least 400 to operate reliably. + +2007-07-27 John Dallaway <jld@ecoscentric.com> + + * misc/cfpe-stub.gdb: New GDB command file for debugging via + m68k-elf-cfpe-stub. + + * cdl/hal_m68k_m5272c3.cdl: Reference per-package documentation. + +2007-07-25 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: Define CYGHWR_MEMORY_LAYOUT as + required by the eCos Configuration Tool. + +2006-09-10 Bart Veer <bartv@ecoscentric.com> + + * include/plf.inc: processor HAL now uses more verbose names in + the init macros. + + * include/plf_io.h: no need to define MBAR, the processor HAL now + has a default. + + * cdl/hal_m68k_m5272c3.cdl, include/plf_stub.h (removed): allow + the architectural HAL to provide plf_stub.h + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: lots of changes for all the reasons + below. + + * src/platform.c: eliminate nearly all initialization. Some of + this now happens higher up in the processor, variant or + architectural HAL. The processor HAL now implements a proper reset + so we can assume the on-chip devices are in a default state. + + * include/plf_io.h: diagnostics definitions now use the variant + HAL defaults. + + * include/plf_arch.h: can now be #include'd by assembler. + + * src/flash.c (was source/m5272c3_flash.c): now uses V2 flash + driver. + + * src/platform/asm.S: no longer needed. + + * include/plf_intr, include/plf.inc: stacks are now provided by + the architectural HAL. + + * include/plf.inc: Initialization uses the processor HAL macros. + + * misc/redboot_DBUG.ecm, misc/redboot_RAM.ecm, + misc/redboot_ROM.ecm, misc/redboot_ROMFFE.ecm: regenerate + + * include/pkgconf/mlt_m5272c3.h, include/pkgconf/mlt_m5272c3.ldi: + Simplified linker scripts using the new architectural support + + * include/pkgconf/mlt_m68k_m5272c3_dbug.h, + include/pkgconf/mlt_m68k_m5272c3_dbug.ldi, + include/pkgconf/mlt_m68k_m5272c3_ram.h, + include/pkgconf/mlt_m68k_m5272c3_ram.ldi, + include/pkgconf/mlt_m68k_m5272c3_rom.h, + include/pkgconf/mlt_m68k_m5272c3_rom.ldi, + include/pkgconf/mlt_m68k_m5272c3_romffe.hi, + include/pkgconf/mlt_m68k_m5272c3_romffe.ldi: + All replaced by mlt_m5272c3.h and mlt_m5272c3.ldi + +2004-08-02 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: minor change following serial driver + change, specify that RTS and CTS are connected on both UARTs + +2004-06-25 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: CYGNUM_HAL_M68K_M5272C3_SCR, ethernet + should always have priority over the cpu, in case you are + debugging over ethernet. + +2004-06-24 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: HAL_M68K_VSR_COUNT has been moved to + the processor HAL + +2004-06-22 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: increase default startup stack size. + Doing a printf() in a static constructor while debugging over + ethernet could overflow. + +2004-05-17 Bart Veer <bartv@ecoscentric.com> + + * src/platform.c (hal_m68k_m5272c3_init): set up the GPIO + directions, then the control bits, to eliminate a small window + where a GPIO pin might be incorrectly set as an output + Fix the exception handling initialization. + + * cdl/hal_m68k_m5272c3.cdl: fix default SCR value for better + performance. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml: romffe startup has now been tested + + * src/platform.c (hal_m68k_m5272c3_init): minor fix to UART + initialization code + + * cdl/hal_m68k_m5272c3.cdl: fix typo in board name. + +2004-01-07 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml, misc/redboot_ROMFFE.ecm: + Add .ecm file for building RedBoot to run from the first block of + flash. + +2003-11-13 Bart Veer <bartv@ecoscentric.com> + + * src/m5272c3_flash.c: remove spurious comment + +2003-09-14 John Dallaway <jld@ecoscentric.com> + + * misc/bdm.gdb: Add BDM macro file for use with GDB. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Use a larger denominator. Small values cause problems for + time-related calculations elsewhere. + +2003-07-21 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml: Add documentation + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Fix some mentions of mcf5272c3 to m5272c3 + +2003-07-11 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Make the default system clock configurable. + +2003-07-04 Bart Veer <bartv@ecoscentric.com> + + * src/platform_asm.S: + * include/plf_intr.h: + * include/plf.inc: + Interrupt stack is now optional and both the stack base and top + need to be exported. + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/cdl/hal_m68k_m5272c3.cdl @@ -0,0 +1,382 @@ +# ==================================================================== +# +# hal_m68k_m5272c3.cdl +# +# Freescale m5272c3 evaluation board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003,2004,2006,2007,2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with eCos; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +# +# As a special exception, if other files instantiate templates or use macros +# or inline functions from this file, or you compile this file and link it +# with other works to produce a work based on this file, this file does not +# by itself cause the resulting work to be covered by the GNU General Public +# License. However the source code for this file must still be made available +# in accordance with section (3) of the GNU General Public License. +# +# This exception does not invalidate any other reasons why a work based on +# this file might be covered by the GNU General Public License. +# ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_package CYGPKG_HAL_M68K_M5272C3 { + display "Freescale M5272C3 evaluation board" + doc ref/hal-m68k-m5272c3-part.html + parent CYGPKG_HAL_M68K_MCF5272 + include_dir cyg/hal + description "This package provides platform support for the Freescale + M5272C3 evaluation board." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_m68k_m5272c3.h>" + puts $::cdl_system_header "#define HAL_PLATFORM_CPU \"Freescale MCF5272\"" + puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"M5272C3\"" + puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\"" + } + compile platform.c + implements CYGINT_HAL_M68K_USE_STANDARD_PLATFORM_STUB_SUPPORT + + implements CYGHWR_DEVS_FLASH_AMD_AM29XXXXX_V2_CACHED_ONLY + compile -library=libextras.a flash.c + define_proc { + puts $cdl_system_header "#define CYGHWR_MEMORY_LAYOUT_LDI <pkgconf/mlt_m5272c3.ldi>" + puts $cdl_system_header "#define CYGHWR_MEMORY_LAYOUT_H <pkgconf/mlt_m5272c3.h>" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMFFE" "DBUG"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + + description " + The eCos port to the M5272C3 evaluation board can be used in four + ways. ROM startup should be used when the application will be written + into flash at location 0xFFF00000, alongside the existing dBUG ROM + monitor, and the board is made to boot from that location via + jumper 13. Typically RedBoot will use a ROM startup, and some applications + may do so as well. RAM startup should be used for application development, + if RedBoot is used as the ROM monitor. DBUG startup can be used to develop + software with the existing dBUG ROM monitor. ROMFFE is for applications + that will be written to flash at location 0xFFE00000, overwriting the + existing dBUG ROM monitor." + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + parent CYGPKG_HAL_ROM_MONITOR + default_value { is_loaded(CYGPKG_REDBOOT) } + description " + This option configures the M5272C3 platform HAL to act as a + ROM monitor." + + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Coexist with a ROM monitor" + parent CYGPKG_HAL_ROM_MONITOR + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + + description " + In a typical setup the M5272C3 boots from flash into the + RedBoot ROM monitor, which then provides support for gdb + debugging and for diagnostics. The application will leave + certain exception vectors to RedBoot, and typically the + diagnostics port will also be controlled by RedBoot rather + than directly by the application." + + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + } + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + no_define + description "Set the default system clock." + + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 10000 + description " + In most eCos configurations this option is used to control the + system clock. It specifies the number of microseconds between + clock ticks, so the default value of 10000 corresponds to + 10 milliseconds or 100 timer interrupts per second. The value + is used to program the timer reference register of the mcf5272's + timer 3." + } + + cdl_option CYGHWR_HAL_SYSTEM_CLOCK_HZ { + display "System clock speed in Hz" + flavor data + legal_values { 48000000 66000000 } + default_value 66000000 + define_proc { + puts $cdl_header "#define CYGHWR_HAL_SYSTEM_CLOCK_MHZ (CYGHWR_HAL_SYSTEM_CLOCK_HZ / 1000000)" + } + description " + This option identifies the system clock that the processor uses. + The value is used to set the system timer and calculate baud rates." + } + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated CYGNUM_HAL_RTC_DENOMINATOR * 1000 * CYGNUM_HAL_RTC_PERIOD + description " + This option is used by eCos to convert clock ticks to conventional + time units. CYGNUM_HAL_RTC_NUMERATOR divided by CYGNUM_HAL_RTC_DENOMINATOR + should be the number of nanoseconds per clock tick." + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 100 + description " + This option is used by eCos to convert clock ticks to conventional + time units. CYGNUM_HAL_RTC_NUMERATOR divided by CYGNUM_HAL_RTC_DENOMINATOR + should be the number of nanoseconds per clock tick." + } + } + + # Provide the extra information needed by the variant and processor HALs + implements CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT + requires !CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS + requires !CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD { + display "Default diagnostics baud rate" + flavor data + parent CYGPKG_HAL_M68K_MCFxxxx_DIAGNOSTICS + calculated { (CYG_HAL_STARTUP == "DBUG") ? "19200" : "38400" } + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_BOARD_PINS { + display "Board pin connectivity" + flavor data + parent CYGPKG_HAL_M68K_MCF5272_HARDWARE + + calculated { + "a0_usb_tp a1_usb_rp a2_usb_rn a3_usb_tn a4_usb_susp a5_usb_txen a6_usb_rxd a7_in " . + "a8_in a9_in a10_in a11_in a12_in a13_in a14_in a15_in " . + "b0_txd0 b1_rxd0 b2_cts0 b3_rts0 b4_in b5_in b6_in b7_in " . + "b8_etxd3 b9_etxd2 b10_etxd1 b11_erxd3 b12_erxd2 b13_erxd1 b14_erxer b15_e_mdc " . + "c0_in c1_in c2_in c3_in c4_in c5_in c6_in c7_in " . + "c8_in c9_in c10_in c11_in c12_in c13_in c14_in c15_in " . + "d0_none d1_rxd1 d2_cts1 d3_rts1 d4_txd1 d5_none d6_none d7_none" + } + } + + # Memory registers. These are all reparented below the variant HAL, but + # defined here to provide suitable defaults. + cdl_option CYGNUM_HAL_M68K_MCF5272_CACR { + display "Cache control register" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x80000100 + description " + This option specifies the initial value used for the cache control + register. Subsequently the HAL cache macros will only manipulate + the CENB cache enable bit and the CINVA cache invalidate bit." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ROMBAR { + display "ROM base address register value" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x21000034 + description " + This option is the value used to initialize the ROMBAR register + which controls the location of the on-chip ROM in the memory + map and what types of access are permitted. By default the + internal ROM is disabled since neither eCos nor RedBoot use it + and leaving it disabled reduces power consumption." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_RAMBAR { + display "RAM base address register value" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x20000001 + requires { 0x20000000 == (CYGNUM_HAL_M68K_MCF5272_RAMBAR & 0xFFFFF000) } + description " + This option is the value used to initialize the RAMBAR register + which controls the location of the on-chip SRAM in the memory + map and what types of access are permitted. By default the + internal SRAM is mapped to location 0x20000000, enabled, and + all types of access are permitted. Neither eCos nor RedBoot + use the internal SRAM, instead it is left entirely for the + application." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ACR0 { + display "Access control register 0" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x0000E020 + description " + This option is the value used to initialize the ACR0 register. + The default value controls access to SDRAM at location 0, + enabling caching and buffered writes." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ACR1 { + display "Access control register 1" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0xFF00E000 + description " + This option is the value used to initialize the ACR0 register. + The default value controls access to the external flash memory + at location 0xFFE00000, enabling caching." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_SCR { + display "System configuration register" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x0003 + description " + This option is the value used to the initialize the System + Configuration Register in the System Integration Module. + This register controls bus arbitration and the hardware + watchdog." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + parent CYGPKG_NONE + + description "Global build options including control over compiler + flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "m68k-elf" } + + description "This option specifies the command prefix used when invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=5272 -malign-int -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fomit-frame-pointer" } + description "This option controls the global compiler flags + which are used to compile all packages by default. + Individual packages may define options which + override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=5272 -g -nostdlib -Wl,--gc-sections -Wl,-static" } + + description "This option controls the global linker flags. + Individual packages may define options which + override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { "mlt_m5272c3" } + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "RedBoot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This component holds target-specific options for RedBoot, + mainly rules for generating images in the appropriate format." + + cdl_option CYGBLD_M5272C3_REDBOOT_DBUG { + display "Build an srecord file for use with the dBUG monitor" + flavor none + no_define + active_if { "DBUG" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.dbug.srec : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O srec $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_RAM { + display "Build a binary RedBoot image to run in RAM" + flavor none + no_define + active_if { "RAM" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.ram.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_ROM { + display "Build a binary RedBoot image to run in flash at 0xFFF00000" + flavor none + no_define + active_if { "ROM" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.rom.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_ROMFFE { + display "Build a binary RedBoot image to run in flash at 0xFFE00000" + flavor none + no_define + active_if { "ROMFFE" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.romffe.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/doc/m5272c3.sgml @@ -0,0 +1,808 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- m5272c3.sgml --> +<!-- --> +<!-- m5272c3 platform HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####COPYRIGHTBEGIN#### --> +<!-- --> +<!-- Copyright (C) 2003,2004,2008 --> +<!-- Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- --> +<!-- ####COPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-m5272c3-part"><title>Freescale M5272C3 Board Support</title> + +<!-- {{{ Overview --> + +<refentry id="m68k-m5272c3"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>eCos Support for the Freescale M5272C3 Board</refname> + <refpurpose>Overview</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-description"><title>Description</title> + <para> +The Freescale M5272C3 board has an MCF5272 ColdFire processor, 4MB of +external SDRAM, 2MB of external flash memory, and connectors plus +required support chips for all the on-chip peripherals. By default the +board comes with its own dBUG ROM monitor, located in the bottom half +of the flash. + </para> + <para> +For typical eCos development a RedBoot image is programmed into the +top half of the flash memory, and the board is made to boot this image +rather than the existing dBUG monitor. RedBoot provides gdb stub +functionality so it is then possible to download and debug eCos +applications via the gdb debugger. This can happen over either a +serial line or over ethernet. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-hardware"><title>Supported Hardware</title> + <para> +In a typical setup the bottom half of the flash memory is reserved for +the dBUG ROM monitor and is not accessible to eCos. That leaves four +flash blocks of 256K each. Of these one is used for the RedBoot image +and another is used for managing the flash and holding RedBoot fconfig +values. The remaining two blocks at 0xFFF40000 and 0xFFF80000 can be +used by application code. + </para> + <para> +By default eCos will only support the four megabytes of external SDRAM +present on the initial versions of the board, accessible at location +0x00000000. Later versions come with 16MB. If all 16MB of memory are +required then the ACR0 register needs to be changed. The default value +is controlled by the configuration option +<varname>CYGNUM_HAL_M68K_M5272C3_ACR0</varname>, but this option is +only used during ROM startup so in a typical setup it would be +necessary to rebuild and update RedBoot. Alternatively the register +can be updated by application code, preferably using a high priority +static constructor to ensure that the extra memory is visible before +any code tries to use that memory. It will also be necessary to change +the memory layout so that the linker knows about the additional +memory. + </para> + <para> +By default the 4K of internal SRAM is mapped to location 0x20000000 +using the RAMBAR register. This is not used by eCos or by RedBoot so +can be used by application code. The M68K architectural HAL has an +<filename>iram1.c</filename> testcase to illustrate the linker script +support for this. The internal 16K of ROM is left +disabled by default because its contents are of no use to most +applications. The on-chip peripherals are mapped at 0x10000000 via the +MBAR register. + </para> + <para> +There is a serial driver <varname>CYGPKG_DEVS_SERIAL_MCFxxxx</varname> +which supports both on-chip UARTs. One of the UARTs, usually uart0, +can be used by RedBoot for communication with the host. If this UART +is needed by the application, either directly or via the serial +driver, then it cannot also be used for RedBoot communication. Another +communication channel such as ethernet should be used instead. The +serial driver package is loaded automatically when configuring for the +M5272C3 target. + </para> + <para> +There is an ethernet driver <varname>CYGPKG_DEVS_ETH_MCFxxxx</varname> +for the on-chip ethernet device. This driver is also loaded +automatically when configuring for the M5272C3 target. The M5272C3 +board does not have a unique MAC address, so a suitable address has to +be programmed into flash via RedBoot's <command>fconfig</command> +command. + </para> + <para> +eCos manages the on-chip interrupt controller. Timer 3 is used to +implement the eCos system clock, but timers 0, 1 and 2 are unused and +left for the application. The GPIO pins are manipulated only as needed +to get the UARTs and ethernet working. eCos will reset the remaining +on-chip peripherals (DMA, USB, PLCI, QSPI and PWM) during system +startup or soft reset but will not otherwise manipulate them. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-tools"><title>Tools</title> + <para> +The M5272C3 port is intended to work with GNU tools configured for an +m68k-elf target. The original port was done using m68k-elf-gcc version +3.2.1, m68k-elf-gdb version 5.3, and binutils version 2.13.1. + </para> + <para> +By default eCos is built using the compiler flag +<option>-fomit-frame-pointer</option>. Omitting the frame pointer +eliminates some work on every function call and makes another register +available, so the code should be smaller and faster. However without a +frame pointer m68k-elf-gdb is not always able to identify stack +frames, so it may be unable to provide accurate backtrace information. +Removing this compiler flag from the configuration option +<varname>CYGBLD_GLOBAL_CFLAGS</varname> avoids such debug problems. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Hardware setup --> + +<refentry id="m68k-m5272c3-setup"> + <refmeta> + <refentrytitle>Setup</refentrytitle> + </refmeta> + <refnamediv> + <refname>Setup</refname> + <refpurpose>Preparing the M5272C3 board for eCos Development</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-setup-overview"><title>Overview</title> + <para> +In a typical development environment the M5272C3 board boots from +flash into the RedBoot ROM monitor. eCos applications are configured +for a RAM startup, and then downloaded and run on the board via the +debugger m68k-elf-gdb. Preparing the board therefore involves +programming a suitable RedBoot image into flash memory. + </para> + <para> +The following RedBoot configurations are supported: + </para> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Description</entry> + <entry>Use</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>RedBoot running from the board's flash</entry> + <entry>redboot_ROM.ecm</entry> + <entry>redboot_rom.bin</entry> + </row> + <row> + <entry>dBUG</entry> + <entry>Used for initial setup</entry> + <entry>redboot_DBUG.ecm</entry> + <entry>redboot_dbug.srec</entry> + </row> + <row> + <entry>RAM</entry> + <entry>Used for upgrading ROM version</entry> + <entry>redboot_RAM.ecm</entry> + <entry>redboot_ram.bin</entry> + </row> + <row> + <entry>ROMFFE</entry> + <entry>RedBoot running from the board's flash at 0xFFE00000</entry> + <entry>redboot_ROMFFE.ecm</entry> + <entry>redboot_romffe.bin</entry> + </row> + </tbody> + </tgroup> + </informaltable> + <para> +For serial communications all versions run with 8 bits, no parity, and +1 stop bit. The dBUG version runs at 19200 baud. The ROM and RAM +versions run at 38400 baud. These baud rates can be changed via the +configuration option +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname> and +rebuilding RedBoot. By default RedBoot will use the board's terminal +port, corresponding to uart0, but this can also be changed via the +configuration option +<varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname>. On an +M5272C3 platform RedBoot also supports ethernet communication and +flash management. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-setup-first"><title>Initial Installation</title> + <para> +This process assumes that the board still has its original dBUG ROM +monitor and does not require any special debug hardware. It leaves the +existing ROM monitor in place, allowing the setup process to be +repeated just in case that should ever prove necessary. + </para> + <para> +Programming the RedBoot rom monitor into flash memory requires an +application that can manage flash blocks. RedBoot itself has this +capability. Rather than have a separate application that is used only +for flash management during the initial installation, a special +RAM-resident version of RedBoot is loaded into memory and run. This +version can then be used to load the normal flash-resident version of +RedBoot and program it into the flash. + </para> + <para> +The first step is to connect an RS232 cable between the M5272C3 +terminal port and the host PC. A suitable cable is supplied with the +board. Next start a terminal emulation application such as +HyperTerminal or minicom on the host PC and set the serial +communication parameters to 19200 baud, 8 data bits, no parity, 1 stop +bit (8N1) and no flow control (handshaking). Make sure that the jumper +next to the flash chip is set for bootstrap from the bottom of flash, +location 0xFFE00000. The details of this jumper depend on the revision +of the board, so the supplied board documentation should be consulted +for more details. Apply power to the board and you should see a +<prompt>dBUG></prompt> prompt. + </para> + <para> +Once dBUG is up and running the RAM-resident version of RedBoot can be +downloaded: + </para> + <screen> +dBUG> dl +Escape to local host and send S-records now... + </screen> + <para> +The required S-records file is <filename>redboot_dbug.srec</filename>, +which is normally supplied with the eCos release in the <filename +class="directory">loaders</filename> directory. If it needs to be +rebuilt then instructions for this are supplied <link +linkend="m68k-m5272c3-setup-rebuild">below</link>. The file should be +sent to the target as raw text using the terminal emulator: + </para> + <screen> +S-record download successful! +dBUG> + </screen> + <para> +It is now possible to run the RAM-resident version of RedBoot: + </para> + <screen> +dBUG> go 0x20000 ++FLASH configuration checksum error or invalid key +Ethernet eth0: MAC address 00:00:00:00:00:03 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [DBUG] +Non-certified release, version v2_0_1 - built 09:55:34, Jun 24 2003 + +Platform: M5272C3 (Freescale MCF5272) +Copyright (C) 2000, 2001, 2002, Red Hat, Inc. + +RAM: 0x00000000-0x00400000, 0x0003f478-0x003bd000 available +FLASH: 0xffe00000 - 0x00000000, 8 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +At this stage the RedBoot flash management initialization has not yet +happened so the warning about the configuration checksum error is +expected. To perform this initialization use the +<command>fis init -f</command> command: + </para> + <screen> +RedBoot> fis init -f +About to initialize [format] FLASH image system - continue (y/n)? y +*** Initialize FLASH Image System +... Erase from 0xfff40000-0xfffc0000: .. +... Erase from 0x00000000-0x00000000: +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +The flash chip on the M5272C3 board is slow at erasing flash blocks so +this operation can take some time. At the end the block of flash at +location 0xFFFC0000 holds information about the various flash blocks, +allowing other flash management operations to be performed. The next +step is to set up RedBoot's non-volatile configuration values: + </para> + <screen> +RedBoot> fconfig -i +Initialize non-volatile configuration - continue (y/n)? y +Run script at boot: false +Use BOOTP for network configuration: true +DNS server IP address: +GDB connection port: 9000 +Force console for special debug messages: false +Network hardware address [MAC]: 0x00:0x00:0x00:0x00:0x00:0x03 +Network debug at boot time: false +Update RedBoot non-volatile configuration - continue (y/n)? y +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +For most of these configuration variables the default value is +correct. If there is no suitable BOOTP service running on the local +network then BOOTP should be disabled, and instead RedBoot will prompt +for a fixed IP address, netmask, and addresses for the local gateway +and DNS server. The other exception is the network hardware address, +also known as MAC address. All boards should be given a unique MAC +address, not the one in the above example. If there are two boards on +the same network trying to use the same MAC address then the resulting +behaviour is undefined. + </para> + <para> +It is now possible to load the flash-resident version of RedBoot. +Because of the way that flash chips work it is better to first load it +into RAM and then program it into flash. + </para> + <screen> +RedBoot> load -r -m ymodem -b %{freememlo} + </screen> + <para> +The file <filename>redboot_rom.bin</filename> should now be uploaded +using the terminal emulator. The file is a raw binary and should be +transferred using the Y-modem protocol. + </para> + <screen> +Raw file loaded 0x0003f800-0x000545a3, assumed entry at 0x0003f800 +xyzModem - CRC mode, 2(SOH)/84(STX)/0(CAN) packets, 5 retries +RedBoot> + </screen> + <para> +Once RedBoot has been loaded into RAM it can be programmed into flash: + </para> + <screen> +RedBoot> fis create RedBoot -b %{freememlo} +An image named 'RedBoot' exists - continue (y/n)? y +... Erase from 0xfff00000-0xfff40000: . +... Program from 0x0003f800-0x0007f800 at 0xfff00000: . +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +The flash-resident version of RedBoot has now programmed at location +0xFFF00000, and the flash info block at 0xFFFC0000 has been updated. +The initial setup is now complete. Power off the board and set the +flash jumper to boot from location 0xFFF00000 instead of 0xFFE00000. +Also set the terminal emulator to run at 38400 baud (the usual baud +rate for RedBoot), and power up the board again. + </para> + <screen> ++Ethernet eth0: MAC address 00:00:00:00:00:03 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [ROM] +Non-certified release, version v2_0_1 - built 09:57:50, Jun 24 2003 + +Platform: M5272C3 (Freescale MCF5272) +Copyright (C) 2000, 2001, 2002, Red Hat, Inc. + +RAM: 0x00000000-0x00400000, 0x0000b400-0x003bd000 available +FLASH: 0xffe00000 - 0x00000000, 8 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +When RedBoot issues its prompt it is also ready to accept connections +from m68k-elf-gdb, allowing eCos applications to be downloaded and +debugged. + </para> + <para> +Occasionally it may prove necessary to update the installed RedBoot +image. This can be done simply by repeating the above process, using +dBUG to load the dBUG version of RedBoot +<filename>redboot_dbug.srec</filename>. Alternatively the existing +RedBoot install can be used to load a RAM-resident version, +<filename>redboot_ram.bin</filename>. + </para> + <para> +The ROMFFE version of RedBoot can be installed at location 0xFFE00000, +replacing dBUG. This may be useful if the system needs more flash +blocks than are available with the usual ROM RedBoot. Installing this +RedBoot image will typically involve a BDM-based utility. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-setup-rebuild"><title>Rebuilding RedBoot</title> + <para> +Should it prove necessary to rebuild a RedBoot binary, this is done +most conveniently at the command line. The steps needed to rebuild the +dBUG version of RedBoot are: + </para> + <screen> +$ mkdir redboot_dbug +$ cd redboot_dbug +$ ecosconfig new m5272c3 redboot +$ ecosconfig import $ECOS_REPOSITORY/hal/m68k/mcf52xx/mcf5272/m5272c3/v2_0_1/misc/redboot_DBUG.ecm +$ ecosconfig resolve +$ ecosconfig tree +$ make + </screen> + <para> +At the end of the build the <filename +class="directory">install/bin</filename> subdirectory should contain +the required file <filename>redboot_dbug.srec</filename>. + </para> + <para> +Rebuilding the RAM and ROM versions involves basically the same +process. The RAM version uses the file +<filename>redboot_RAM.ecm</filename> and generates a file +<filename>redboot_ram.bin</filename>. The ROM version uses the file +<filename>redboot_ROM.ecm</filename> and generates a file +<filename>redboot_rom.bin</filename>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-bdm"><title>BDM</title> + <para> +An alternative to debugging an application on top of Redboot is to use +a BDM hardware debug solution. On the eCos side this requires building +the configuration for RAM startup and +with <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> disabled. Note that +a RAM build of RedBoot automatically has the latter configuration +option disabled, so it is possible to run a RAM RedBoot via BDM and +bypass the dBUG stages of the installation process. + </para> + <para> +On the host-side the details depend on exactly which BDM solution is +in use. Typically it will be necessary to initialize the hardware +prior to downloading the eCos application, either via a configuration +file or by using gdb macros. The +file <filename>misc/bdm.gdb</filename> in the platform HAL defines +example gdb macros. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Config --> + +<refentry id="m68k-m5272c3-config"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Configuration</refname> + <refpurpose>Platform-specific Configuration Options</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-config-overview"><title>Overview</title> + <para> +The M5272C3 platform HAL package is loaded automatically when eCos is +configured for an M5272C3 target. It should never be necessary to load +this package explicitly. Unloading the package should only happen as a +side effect of switching target hardware. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-startup"><title>Startup</title> + <para> +The M5272C3 platform HAL package supports four separate startup types: + </para> + <variablelist> + <varlistentry> + <term>RAM</term> + <listitem><para> +This is the startup type which is normally used during application +development. The board has RedBoot programmed into flash at location +0xFFF00000 and boots from that location. +<application>m68k-elf-gdb</application> is then used to load a RAM +startup application into memory and debug it. It is assumed that the +hardware has already been initialized by RedBoot. By default the +application will use eCos' virtual vectors mechanism to obtain certain +services from RedBoot, including diagnostic output. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROM</term> + <listitem><para> +This startup type can be used for finished applications which will +be programmed into flash at location 0xFFF00000. The application will +be self-contained with no dependencies on services provided by other +software. eCos startup code will perform all necessary hardware +initialization. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROMFFE</term> + <listitem><para> +This is a variant of the ROM startup type which can be used if the +application will be programmed into flash at location 0xFFE00000, +overwriting the board's dBUG ROM monitor. + </para> + </listitem> + </varlistentry> + <varlistentry> + <term>DBUG</term> + <listitem><para> +This is a variant of the RAM startup which allows applications to be +loaded via the board's dBUG ROM monitor rather than via RedBoot. It +exists mainly to support the dBUG version of RedBoot which is needed +during hardware setup. Once the application has started it will take +over all the hardware, and it will not depend on any services provided +by dBUG. This startup type does not provide gdb debug facilities. + </para></listitem> + </varlistentry> + </variablelist> + + </refsect1> + + <refsect1 id="m68k-m5272c3-config-redboot"><title>RedBoot and Virtual Vectors</title> + <para> +If the application is intended to act as a ROM monitor, providing +services for other applications, then the configuration option +<varname>CYGSEM_HAL_ROM_MONITOR</varname> should be set. Typically +this option is set only when building RedBoot. + </para> + <para> +If the application is supposed to make use of services provided by a +ROM monitor, via the eCos virtual vector mechanism, then the +configuration option <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> +should be set. By default this option is enabled when building for a +RAM startup, disabled otherwise. It can be manually disabled for a RAM +startup, making the application self-contained, as a testing step +before switching to ROM startup. + </para> + <para> +If the application does not rely on a ROM monitor for diagnostic +services then one of the serial ports will be claimed for HAL +diagnostics. By default eCos will use the terminal port, corresponding +to uart0. The auxiliary port, uart1, can be selected instead via the +configuration option +<varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname>. The baud +rate for the selected port is controlled by +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-flash"><title>Flash Driver</title> + <para> +The platform HAL package contains flash driver support. By default +this is inactive, and it can be made active by loading the generic +flash package <varname>CYGPKG_IO_FLASH</varname>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-registers"><title>Special Registers</title> + <para> +The MCF5272 processor has a number of special registers controlling +the cache, on-chip RAM and ROM, and so on. The platform HAL provides a +number of configuration options for setting these, for example +<varname>CYGNUM_HAL_M68K_M5272C3_RAMBAR</varname> controls the initial +value of the RAMBAR register. These options are only used during a ROM +or ROMFFE startup. For a RAM startup it will be RedBoot that +initializes these registers, so if the default values are not +appropriate for the target application then it will be necessary to +rebuild RedBoot with new settings for these options. Alternatively it +should be possible to reprogram some or all of the registers early on +during startup, for example by using a high-priority static +constructor. + </para> + <para> +One of the special registers, MBAR, cannot be controlled via a +configuration option. Changing the value of this register could have +drastic effects on the system, for example moving the on-chip +peripherals to a different location in memory, and it would be very +easy to end up with inconsistencies between RedBoot and the eCos +application. Instead the on-chip peripherals are always mapped to +location 0x10000000. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-clock"><title>System Clock</title> + <para> +By default the system clock interrupts once every 10ms, corresponding +to a 100Hz clock. This can be changed by the configuration option +<varname>CYGNUM_HAL_RTC_PERIOD</varname>, the number of microseconds +between clock ticks. Other clock-related settings are recalculated +automatically if the period is changed. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-flags"><title>Compiler Flags</title> + <para> +The platform HAL defines the default compiler and linker flags for all +packages, although it is possible to override these on a per-package +basis. Most of the flags used are the same as for other architectures +supported by eCos. There are three flags specific to this port: + </para> + <variablelist> + <varlistentry> + <term><option>-mcpu=5272</option></term> + <listitem><para> +The <application>m68k-elf-gcc</application> compiler supports many +variants of the M68K architecture, from the original 68000 onwards. +For an MCF5272 processor <option>-mcpu=5272</option> should be used. + </para></listitem> + </varlistentry> + <varlistentry> + <term><option>-malign-int</option></term> + <listitem><para> +This option forces <application>m68k-elf-gcc</application> to align +integer and floating point data to a 32-bit boundary rather than a +16-bit boundary. It should improve performance. However the resulting +code is incompatible with most published application binary interface +specifications for M68K processors, so it is possible that this option +causes problems with existing third-party object code. + </para></listitem> + </varlistentry> + <varlistentry> + <term><option>-fomit-frame-pointer</option></term> + <listitem><para> +Traditionally the <varname>%A6</varname> register was used as a +dedicated frame pointer, and the compiler was expected to generate +link and unlink instructions on procedure entry and exit. These days +the compiler is perfectly capable of generating working code without a +frame pointer, so omitting the frame pointer often saves some work +during procedure entry and exit and makes another register available +for optimization. However without a frame pointer register the +<application>m68k-elf-gdb</application> debugger is not always able to +interpret a thread stack, so it cannot reliably give a backtrace. +Removing <option>-fomit-frame-pointer</option> from the default flags +will make debugging easier, but the generated code may be worse. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Port --> + +<refentry id="m68k-m5272c3-port"> + <refmeta> + <refentrytitle>The HAL Port</refentrytitle> + </refmeta> + <refnamediv> + <refname>HAL Port</refname> + <refpurpose>Implementation Details</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-port-overview"><title>Overview</title> + <para> +This documentation explains how the eCos HAL specification has been +mapped onto the M5272C3 hardware, and shold be read in conjunction +with that specification. The M5272C3 platform HAL package complements +the M68K architectural HAL, the MCFxxxx variant HAL, and the MCF5272 +processor HAL. It provides functionality which is specific to the +target board. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-startup"><title>Startup</title> + <para> +Following a hard or soft reset the HAL will initialize or +reinitialize most of the on-chip peripherals. There is an exception +for RAM startup applications which depend on a ROM monitor for certain +services: the UARTs and the ethernet device will not be reinitialized +because they may be in use by RedBoot for communication with the host. + </para> + <para> +For a ROM or ROMFFE startup the HAL will perform additional +initialization, setting up the external DRAM and programming the +various internal registers. The values used for most of these +registers are <link +linkend="m68k-m5272c3-config-registers">configurable</link>. Full +details can be found in the exported headers <filename +class="headerfile">cyg/hal/plf.inc</filename> +and <filename class="headerfile">cyg/hal/proc.inc</filename>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-linker"><title>Linker Scripts and Memory Maps</title> + <para> +The platform HAL package provides the memory layout information needed +to generate the linker script. The key memory locations are as follows: + </para> + <variablelist> + <varlistentry> + <term>external SDRAM</term> + <listitem><para> +This is mapped to location 0x00000000. The first 384 bytes are used +for hardware exception vectors. The next 256 bytes are normally used +for the eCos virtual vectors, allowing RAM-based applications to use +services provided by the ROM monitor. For ROM and ROMFFE startup all +remaining SDRAM is available. For RAM and DBUG startup available SDRAM +starts at location 0x00020000, with the bottom 128K reserved for use +by either the RedBoot or dBUG ROM monitors. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip peripherals</term> + <listitem><para> +These are accessible at location 0x10000000 onwards, as per the +defined symbol <varname>HAL_MCFxxxx_MBAR</varname>. This address +cannot easily be changed during development because both the ROM +monitor and the application must use the same address. The +<varname>%mbar</varname> system register is initialized appropriately +during a ROM or ROMFFE startup. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip SRAM</term> + <listitem><para> +The 4K of internal SRAM are normally mapped at location 0x20000000. +The <varname>%rambar</varname> register is initialized +during a ROM startup using the value of the configuration +option <varname>CYGNUM_HAL_M68K_M5272C3_RAMBAR</varname>. Neither eCos +nor RedBoot use the internal SRAM so all of it is available to +application code. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip ROM</term> + <listitem><para> +Usually this is left disabled since its contents are of no interest to +most applications. If it is enabled then it is usually mapped at +location 0x21000000. The <varname>%rombar</varname> register is +initialized during a ROM startup using the value of the configuration +option <varname>CYGNUM_HAL_M68K_M5272C3_ROMBAR</varname>. + </para></listitem> + </varlistentry> + <varlistentry> + <term>off-chip Flash</term> + <listitem><para> +This is located at the top of memory, location 0xFFE00000 onwards. For +ROM and RAM startups it is assumed that a jumper is used to disable +the bottom half of the flash, so location 0xFFE00000 is actually a +mirror of 0xFFF00000. For ROMFFE and DBUG startups all of the flash is +visible. By default the flash block at location 0xFFF00000 is used to +hold RedBoot or another ROM startup application, and the block at +location 0xFFFC00000 is used to hold flash management data and the +RedBoot <command>fconfig</command> variables. The blocks at +0xFFF400000 and 0xFFF80000 can be used by application code. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-clock"><title>Clock Support</title> + <para> +The platform HAL provides configuration options for the eCos system +clock. This always uses the hardware timer 3, which should not be used +directly by application code. The gprof-based profiling code uses +timer 2, so that is only available when not profiling. Timers 0 and 1 +are never used by eCos so application code is free to manipulate these +as required. The actual HAL macros for managing the clock are provided +by the MCF5272 processor HAL. The specific numbers used are a +characteristic of the platform because they depend on the processor +speed. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-other-hal"><title>Other Issues</title> + <para> +The M5272C3 platform HAL does not affect the implementation of other +parts of the eCos HAL specification. The MCF5272 processor HAL, the +MCFxxxx variant HAL, and the M68K architectural HAL documentation +should be consulted for further details. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-other"><title>Other Functionality</title> + <para> +The platform HAL package also provides a flash driver for the off-chip +AMD AM29PL160C flash chip. This driver is inactive by default, and +only becomes active if the configuration includes the generic flash +support <varname>CYGPKG_IO_FLASH</varname>. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> + +</part>
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.h @@ -0,0 +1,20 @@ +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x00400000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0xFFE00000) +#define CYGMEM_REGION_flash_SIZE (0x00200000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) +#define CYGMEM_REGION_iram (0x20000000) +#define CYGMEM_REGION_iram_SIZE (0x00001000) +#define CYGMEM_REGION_iram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.ldi @@ -0,0 +1,40 @@ +#define __LDI__ 1 +#include <pkgconf/hal_m68k_m5272c3.h> +#include <pkgconf/mlt_m5272c3.h> + +MEMORY +{ + ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE + flash : ORIGIN = CYGMEM_REGION_flash, LENGTH = CYGMEM_REGION_flash_SIZE + iram : ORIGIN = CYGMEM_REGION_iram, LENGTH = CYGMEM_REGION_iram_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_ram_vectors( ram, 0x00000000) + +#if defined(CYG_HAL_STARTUP_ROM) + + SECTION_m68k_start ( flash, 0xFFF00000) + SECTION_code ( flash, .) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_ram_vectors_section_end, AT(_hal_iram_section_end_lma)) + +#elif defined(CYG_HAL_STARTUP_ROMFFE) + + SECTION_m68k_start ( flash, 0xFFE00000) + SECTION_code ( flash, .) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_ram_vectors_section_end, AT(_hal_iram_section_end_lma)) + +#elif defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_DBUG) + /* The first 128K of RAM are reserved for RedBoot */ + SECTION_m68k_start ( ram, 0x00020000 ) + SECTION_code ( ram, . ) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_iram_section_end_lma, LMA_EQ_VMA) +#endif + CYG_LABEL_DEFN(__heap1) = ALIGN (0x4); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf.inc @@ -0,0 +1,89 @@ +##============================================================================= +## +## plf.inc +## +## m5272c3 assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003,2006,2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_m5272c3.h> +#include <cyg/hal/var_io.h> + +// ---------------------------------------------------------------------------- +// Various constants to poke into coprocessor or SIM registers +// +// MBAR controls the location of the System Integration Module, +// i.e. all the on-chip hardware. Conventionally this is at +// location 0x10000000. Obviously it cannot contain code. + .equ _HAL_MCF5272_MBAR_VALUE_, (HAL_MCFxxxx_MBAR + HAL_MCF5272_MBAR_SC + HAL_MCF5272_MBAR_UC + HAL_MCF5272_MBAR_V) + +// Chip select 0 is connected to 2MB of flash @ 0xFFE00000. +// This chip is 16 bits wide and requires 6 wait states according +// to the docs. (dBUG uses 8 wait states initially, 5 later on). +// 5 seems to work fine. + .equ _HAL_MCF5272_CSBR0_VALUE_, (0xFFE00000 + HAL_MCF5272_CSBR_EBI_16_32 + HAL_MCF5272_CSBR_BW_16 + HAL_MCF5272_CSBR_ENABLE) + .equ _HAL_MCF5272_CSOR0_VALUE_, (0xFFE00000 + (0x05 << HAL_MCF5272_CSOR_WS_SHIFT)) + +// The board can be populated with sram on cs2, but for now assume a bare board. + +// Chip select 7 is connected to 4MB of SDRAM, which should be @ 0x0 + .equ _HAL_MCF5272_CSBR7_VALUE_, (0x00000000 + HAL_MCF5272_CSBR_EBI_SDRAM + HAL_MCF5272_CSBR_BW_CACHELINE + HAL_MCF5272_CSBR_ENABLE) + .equ _HAL_MCF5272_CSOR7_VALUE_, (0xFFC00000 + (0x1F << HAL_MCF5272_CSOR_WS_SHIFT)) + +// SDRAM control registers + .equ _HAL_MCF5272_SDCR_VALUE_, (HAL_MCF5272_SDCR_MCAS_A9 + HAL_MCF5272_SDCR_BALOC_A22_A21 + HAL_MCF5272_SDCR_REG + HAL_MCF5272_SDCR_INIT) +#if defined(CYGHWR_HAL_SYSTEM_CLOCK_HZ_66000000) + .equ _HAL_MCF5272_SDTR_VALUE_, (HAL_MCF5272_SDTR_RTP_66+HAL_MCF5272_SDTR_RC_6+HAL_MCF5272_SDTR_RP_4+HAL_MCF5272_SDTR_RCD_3+HAL_MCF5272_SDTR_CLT_2) +#elif defined(CYGHWR_HAL_SYSTEM_CLOCK_HZ_48000000) + .equ _HAL_MCF5272_SDTR_VALUE_, (HAL_MCF5272_SDTR_RTP_48+HAL_MCF5272_SDTR_RC_6+HAL_MCF5272_SDTR_RP_4+HAL_MCF5272_SDTR_RCD_3+HAL_MCF5272_SDTR_CLT_2) +#else +# error Unsupported system clock speed. +#endif + +// ---------------------------------------------------------------------------- +// Startup code. Use the processor defaults. +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMFFE) +# define _HAL_MCF5272_STANDARD_INIT_ROM_ 1 +#else +# define _HAL_MCF5272_STANDARD_INIT_RAM_ 1 +#endif + +//------------------------------------------------------------------------------ +// end of plf.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_arch.h @@ -0,0 +1,57 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H + +//============================================================================= +// +// plf_arch.h +// +// m5272c3 specific definitions. +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> + +// Platform initialization +externC void hal_m68k_m5272c3_init(void); +#define HAL_M68K_PLATFORM_INIT() hal_m68k_m5272c3_init() +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_ARCH_H
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_intr.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific interrupt and clock support +// +// +//========================================================================== +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/plf_arch.h> + +// Three of the external interrupt lines are connected to other hardware. +#define CYGNUM_HAL_VECTOR_PLI_B33 CYGNUM_HAL_VECTOR_EXTINT1 +#define CYGNUM_HAL_VECTOR_PLI_A34 CYGNUM_HAL_VECTOR_EXTINT3 +#define CYGNUM_HAL_VECTOR_ABORT CYGNUM_HAL_VECTOR_EXTINT6 + +#define CYGNUM_HAL_ISR_PLI_B33 CYGNUM_HAL_ISR_EXTINT1 +#define CYGNUM_HAL_ISR_PLI_A34 CYGNUM_HAL_ISR_EXTINT3 +#define CYGNUM_HAL_ISR_ABORT CYGNUM_HAL_ISR_EXTINT6 + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_io.h @@ -0,0 +1,51 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +# define CYGONCE_HAL_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Details of the m5272c3 platform +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2006,2007,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal_m68k_m5272c3.h> + +// ---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/bdm.gdb @@ -0,0 +1,48 @@ +define bdm_preload + set $mbar = 0x10000001 + set $SCR = $mbar - 1 + 0x0004 + set $SPR = $mbar - 1 + 0x0006 + set $CSBR0 = $mbar - 1 + 0x0040 + set $CSOR0 = $mbar - 1 + 0x0044 + set $CSBR1 = $mbar - 1 + 0x0048 + set $CSOR1 = $mbar - 1 + 0x004C + set $CSBR2 = $mbar - 1 + 0x0050 + set $CSOR2 = $mbar - 1 + 0x0054 + set $CSBR3 = $mbar - 1 + 0x0058 + set $CSOR3 = $mbar - 1 + 0x005C + set $CSBR4 = $mbar - 1 + 0x0060 + set $CSOR4 = $mbar - 1 + 0x0064 + set $CSBR5 = $mbar - 1 + 0x0068 + set $CSOR5 = $mbar - 1 + 0x006C + set $CSBR6 = $mbar - 1 + 0x0070 + set $CSOR6 = $mbar - 1 + 0x0074 + set $CSBR7 = $mbar - 1 + 0x0078 + set $CSOR7 = $mbar - 1 + 0x007C + set $SDCR = $mbar - 1 + 0x0180 + set $SDTR = $mbar - 1 + 0x0184 + set *((short*) $SCR) = 0x0083 + set *((short*) $SPR) = 0xFFFF + set *((int*) $CSBR0) = 0xFFE00201 + set *((int*) $CSOR0) = 0xFFE00014 + set *((int*) $CSBR1) = 0 + set *((int*) $CSOR1) = 0 + set *((int*) $CSBR2) = 0 + set *((int*) $CSOR2) = 0 + set *((int*) $CSBR3) = 0 + set *((int*) $CSOR3) = 0 + set *((int*) $CSBR4) = 0 + set *((int*) $CSOR4) = 0 + set *((int*) $CSBR5) = 0 + set *((int*) $CSOR5) = 0 + set *((int*) $CSBR6) = 0 + set *((int*) $CSOR6) = 0 + set *((int*) $CSBR7) = 0x00000701 + set *((int*) $CSOR7) = 0xFFC0007C + set *((int*) $SDTR) = 0x0000F539 + set *((int*) $SDCR) = 0x00004211 + set *((int*)0) = 0 +end + +define bdm_postload + set $pc=0x20000 +end
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_DBUG.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value DBUG +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_RAM.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROM.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROMFFE.ecm @@ -0,0 +1,98 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMFFE +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/flash.c @@ -0,0 +1,80 @@ +//========================================================================== +// +// m5272c3_flash.c +// +// Support for AMD Flash devices on M5272C3 evaluation board +// +//========================================================================== +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#ifdef CYGPKG_IO_FLASH +# include <cyg/io/flash.h> +# include <cyg/io/flash_dev.h> +# include <cyg/io/am29xxxxx_dev.h> + +// There is a single AM29PL160C device. +static const CYG_FLASH_FUNS(hal_m5272c3_flash_amd_funs, + &cyg_am29xxxxx_init_check_devid_16, + &cyg_flash_devfn_query_nop, + &cyg_am29xxxxx_erase_16, + &cyg_am29xxxxx_program_16, + (int (*)(struct cyg_flash_dev*, const cyg_flashaddr_t, void*, size_t))0, + &cyg_am29xxxxx_lock_nop, + &cyg_am29xxxxx_unlock_nop); + +static const cyg_am29xxxxx_dev hal_m5272c3_flash_priv = { + .devid = 0x2245, + .block_info = { + { 0x00004000, 1 }, + { 0x00002000, 2 }, + { 0x00038000, 1 }, + { 0x00040000, 7 } + } +}; + +CYG_FLASH_DRIVER(hal_m5272c3_flash, + &hal_m5272c3_flash_amd_funs, + 0, + 0xFFE00000, + 0xFFFFFFFF, + 4, + hal_m5272c3_flash_priv.block_info, + &hal_m5272c3_flash_priv +); +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/platform.c @@ -0,0 +1,84 @@ +//============================================================================= +// +// platform.c +// +// M5272C3 platform code +// +//============================================================================= +//###ECOSGPLCOPYRIGHTBEGIN#### +//------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc. +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_m5272c3.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_if.h> + +// ---------------------------------------------------------------------------- +// Platform initialization. This is called early on from +// hal_m68k_startup(), once the C environment has been set up. We are +// running on the startup stack and interrupts are disabled. It is +// assumed that the memory map is already sane - either the ROM +// monitor or the assembler startup code should have taken care of +// that. +// +// For ROM/ROMFFE startup the assumption is that we have just come +// out of reset, either because of a hard reset or because a soft +// reset activated the watchdog. Hence we can assume all peripherals +// are at their default settings. + +void +hal_m68k_m5272c3_init(void) +{ + // Start with the hardware. If this code is reached from a hard + // reset, RedBoot or dBUG then most of the hardware should be in a + // reasonable state. For a soft reset assume that the watchdog has + // been used so again everything should be in a reasonable state. + // Hence we only need to worry about registers where the default + // settings are inappropriate. + + // After a power-up the ethernet phy needs a bit of time to negotiate + // the link. Without this delay packets appear to go out but are + // just lost, which is a problem for bootp. +#if defined(CYGPKG_DEVS_ETH_MCFxxxx) && (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMFFE)) + HAL_DELAY_US(10000); +#endif +}