Mercurial > ecos
changeset 1986:e256aea3e373
* First import of an ethernet device driver for the NETARM
processors.
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,7 @@ +2005-06-12 Brandl Harald <Harald.Brandl@fh-joanneum.at> + + * ecos.db: Added a ethernet device driver for the NETARM. + 2005-04-17 Andrew Lunn <andrew.lunn@ascom.ch> * ecos.db: Added support for the AT91 based PhyCore
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,4 @@ +* Support for the Ethenet device on the NETARM devices. * Added support for the AT91 based PhyCore. * Added support for Exys XSEngine (PXA255) based system. * Port of ezXML parser added.
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/ChangeLog @@ -0,0 +1,36 @@ +2005-06-12 Brandl Harald <Harald.Brandl@fh-joanneum.at> + + * First import of an ethernet device driver for the NETARM + processors. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/cdl/netarm_eth_driver.cdl @@ -0,0 +1,136 @@ +# ==================================================================== +# +# netarm_eth_driver.cdl +# +# Ethernet driver +# NET+ARM ethernet interface +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2005 eCosCentric LTD +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +# Original data: +# Contributors: +# Date: 01.08.2004 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ARM_NETARM { + display "NetSilicon board ethernet driver" + description "Ethernet driver for NET+ARM." + + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + + + compile -library=libextras.a MII.c netarm_eth_drv.c eeprom.c + + define_proc { + puts $::cdl_system_header "/***** ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_NETARM_CFG <pkgconf/devs_eth_arm_netarm.h>" + puts $::cdl_system_header "/***** ethernet driver proc output end *****/" + } + + cdl_interface CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_ESA { + no_define + requires 1 == CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_ESA + } + + cdl_component CYGPKG_DEVS_ETH_ARM_NETARM_ETH0 { + display "Ethernet port 0 driver" + flavor bool + default_value 1 + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + + cdl_option CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_NAME { + display "Device name for the ETH0 ethernet port 0 driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the ethernet device for the + netarm ethernet port 0." + } + + cdl_component CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_SET_ESA { + display "Set the ethernet station address" + flavor bool + default_value 1 + implements CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_ESA + description "Enabling this option will allow the ethernet + station address to be forced to the value set by the + configuration. This may be required if the hardware does + not include a serial EEPROM for the ESA." + + cdl_option CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA { + display "The ethernet station address" + flavor data + default_value {"{0x00, 0x40, 0xaf, 0x77, 0xe0, 0x80}"} + description "The ethernet station address" + } + } + + cdl_option CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA_EEPROM { + display "Read ethernet station address from eeprom" + flavor bool + default_value 0 + implements CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_ESA + description "Read ethernet station address from eeprom (I2C)" + } + + cdl_component CYGPKG_DEVS_ETH_ARM_NETARM_OPTIONS { + display "NETARM ethernet driver build options" + flavor none + no_define + + cdl_option CYGPKG_DEVS_ETH_ARM_NETARM_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-D_KERNEL -D__ECOS" } + description " + This option modifies the set of compiler flags for + building the NETARM ethernet driver + package. These flags are used in addition to the set of + global flags." + } + } + } +} + +# EOF netarm_eth_driver.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/doc/netarm_hal.patch @@ -0,0 +1,467 @@ +diff -Naur orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl +--- orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2004-11-29 17:35:46.000000000 +0100 ++++ new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2005-03-10 14:54:13.903367200 +0100 +@@ -18,6 +18,26 @@ + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_netarm.h>" + } + ++ cdl_option CYGSEM_HAL_INSTRUCTION_CACHE_SETS { ++ display "Sets for Instruction Cache" ++ parent CYGPKG_HAL_CACHE_CONTROL ++ active_if CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP ++ flavor data ++ legal_values 0 to 15 ++ default_value 0xc ++ description "MSB: SET1 | SET2 | SET3 | SET4" ++ } ++ ++ cdl_option CYGSEM_HAL_DATA_CACHE_SETS { ++ display "Sets for Data Cache" ++ parent CYGPKG_HAL_CACHE_CONTROL ++ active_if CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP ++ flavor data ++ legal_values 0 to 15 ++ default_value 0x3 ++ description "MSB: SET1 | SET2 | SET3 | SET4" ++ } ++ + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data +diff -Naur orig/hal/arm/netarm/current/include/hal_cache.h new/hal/arm/netarm/current/include/hal_cache.h +--- orig/hal/arm/netarm/current/include/hal_cache.h 2004-11-29 17:35:46.000000000 +0100 ++++ new/hal/arm/netarm/current/include/hal_cache.h 2005-03-10 14:41:51.032173600 +0100 +@@ -19,25 +19,57 @@ + #define HAL_ICACHE_WAYS 4 // Associativity of the cache + #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line + +-#define HAL_ICACHE_BASE 0x08000000 +-#define HAL_ICACHE_MASK 0xfe000000 ++#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_RAM) ++ #define HAL_ICACHE_BASE 0x04000000 ++ #define HAL_DCACHE_BASE 0x08000000 ++#else ++ #define HAL_ICACHE_BASE 0x02000000 ++ #define HAL_DCACHE_BASE 0x04000000 ++#endif ++ ++#define HAL_ICACHE_MASK 0xff000000 ++#define HAL_DCACHE_MASK 0xff000000 ++ ++ ++#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP ++ #define HAL_ICACHE_ENABLE() \ ++ { \ ++ *(CCR0)=(HAL_ICACHE_BASE) | \ ++ (HAL_ICACHE_MASK >> 8) | \ ++ (CCR_ENABLE) | \ ++ (1 << 11) | \ ++ (CYGSEM_HAL_INSTRUCTION_CACHE_SETS); \ ++ } ++#else ++ #define HAL_ICACHE_ENABLE() (*(CCR0)=0) ++#endif + +-#define HAL_ICACHE_ENABLE() \ ++#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP ++ #define HAL_DCACHE_ENABLE() \ ++ { \ ++ *(CCR1)=(HAL_DCACHE_BASE) | \ ++ (HAL_DCACHE_MASK >> 8) | \ ++ (CCR_ENABLE) | \ ++ (1 << 11) | \ ++ (CYGSEM_HAL_DATA_CACHE_SETS); \ ++ } ++#else ++ #define HAL_DCACHE_ENABLE() (*(CCR1)=0) ++#endif ++ ++#define HAL_CACHE_ENABLE() \ + { \ + unsigned int *p; \ + int i; \ + \ + *(SYSCON)|=SYSCON_CINIT|SYSCON_CACHE; \ + p=(unsigned int *)0xfff00000; \ +- for(i=0;i<(0x2000/4);i++,p++) \ ++ for(i=0;i<(0x4000/4);i++,p++) \ + *p=0; \ + \ +- *(SYSCON)&=~(SYSCON_CINIT); \ +- *(CCR0)=(HAL_ICACHE_BASE) | \ +- (HAL_ICACHE_MASK >> 8) | \ +- (CCR_ENABLE) | \ +- (CCR_SET1 | CCR_SET2 | CCR_SET3 | CCR_SET4); \ +- *(CCR1)=0; \ ++ HAL_ICACHE_ENABLE(); \ ++ HAL_DCACHE_ENABLE(); \ ++ \ + *(SYSCON)|=SYSCON_CACHE; \ + *(SYSCON)&=~SYSCON_WB; \ + } +@@ -45,17 +77,25 @@ + #define HAL_ICACHE_DISABLE() \ + { \ + *(CCR0)=0; \ +- *(SYSCON)&=~SYSCON_CACHE; \ ++ if (HAL_DCACHE_IS_ENABLED == 0) \ ++ *(SYSCON)&=~SYSCON_CACHE; \ + } + +-#define HAL_ICACHE_IS_ENABLED(_state_) _state_ = ((*(CCR0) & CCR_ENABLE) >> 15) ++#define HAL_DCACHE_DISABLE() \ ++{ \ ++ *(CCR1)=0; \ ++ if (HAL_ICACHE_IS_ENABLED == 0) \ ++ *(SYSCON)&=~SYSCON_CACHE; \ ++} ++ ++#define HAL_ICACHE_IS_ENABLED ((*(CCR0) & CCR_ENABLE) >> 15) + +-#define HAL_ICACHE_INVALIDATE_ALL() \ ++#define HAL_CACHE_INVALIDATE_ALL() \ + { \ + unsigned *p; \ + *(SYSCON)|=SYSCON_CINIT; \ + for(p=(unsigned int*)0xfff00000; \ +- (unsigned int)p<0xfff02000; \ ++ (unsigned int)p<0xfff04000; \ + p++) \ + *p=0; \ + \ +@@ -64,25 +104,13 @@ + + #define HAL_ICACHE_SYNC() + +-#define HAL_ICACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL() +- +-#define HAL_DCACHE_LINE_SIZE 0 +-#define HAL_DCACHE_WAYS 0 +-#define HAL_DCACHE_SETS 0 +- +-#define HAL_DCACHE_ENABLE() ++#define HAL_CACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL() + +-#define HAL_DCACHE_DISABLE() +- +-#define HAL_DCACHE_INVALIDATE_ALL() ++#define HAL_DCACHE_LINE_SIZE 4 ++#define HAL_DCACHE_WAYS 4 + + #define HAL_DCACHE_SYNC() + +-#define HAL_DCACHE_IS_ENABLED(_state_) 0 +- +-#define HAL_DCACHE_FLUSH( _base_ , _size_ ) +- +-#define HAL_DCACHE_STORE( _base_ , _size_ ) ++#define HAL_DCACHE_IS_ENABLED ((*(CCR1) & CCR_ENABLE) >> 15) + + #endif +- +diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h +--- orig/hal/arm/netarm/current/include/hal_platform_setup.h 2004-11-29 17:35:46.000000000 +0100 ++++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-14 17:10:01.542675500 +0100 +@@ -19,7 +19,7 @@ + // Usage: #include <cyg/hal/hal_platform_setup.h> + // + //####DESCRIPTIONEND#### +-// ++// + //===========================================================================*/ + + #include <pkgconf/system.h> // System-wide configuration info +@@ -34,15 +34,31 @@ + bic r0,r0, #((\x & 3)<<1); \ + str r0,[r1] + +-#if defined(CYG_HAL_STARTUP_ROMRAM) ++#if defined(CYG_HAL_STARTUP_ROMRAM) + #define HAL_FLASH_PHYS_ADDR 0x02000000 +-#define UNMAPPED(x) ((x)-0x08000000) ++#define UNMAPPED(x) ((x)-0x04000000) + #elif defined(CYG_HAL_STARTUP_ROM) + #define HAL_FLASH_PHYS_ADDR 0x02000000 + #define UNMAPPED(x) ((x)-0x02000000) + #endif + .macro PLATFORM_SETUP1 +- ++ ++ ldr r1,=0xffb0000c // software reset ++ ldr r0,=0x00000123 ++ str r0,[r1] ++ ldr r0,=0x00000321 ++ str r0,[r1] ++ ++ mov r0,#1000 ++loop: ++ sub r0,r0,#1 ++ cmp r0,#0 ++ bne loop ++ ++ ldr r0,=0x00000123 ++ str r0,[r1] ++ ldr r0,=0x00000321 ++ str r0,[r1] + + #if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM) + mov r1,#0xff000000 +@@ -51,7 +67,11 @@ + ldr r0,=0x4004a800 /* System control register */ + str r0,[r1] + ++#ifdef CYG_HAL_STARTUP_ROM + mov r0,#0 /* PLL config */ ++#else ++ ldr r0,=0x09000e1e ++#endif + str r0,[r1,#8] + + ldr r0,=0xfff00000 /* PORT A mode & dir */ +@@ -64,7 +84,7 @@ + str r0,[r1,#0x28] + + add r1,r1,#0x100000 /* Setup MEM Module base addr */ +- ++ + ldr r0,=0x148C0000 /* Memory Module Config register */ + str r0,[r1] + +@@ -79,7 +99,7 @@ + ldr r0,=0xf3f00304 /* CS0 Option register */ + str r0,[r1,#0x14] + +- ldr r0,=0x02000001 /* CS0 Base Address register */ ++ ldr r0,=0x02000001 /* CS0 Base Address register */ + str r0,[r1,#0x10] + + mov pc,r2 /* Jump to new flash base */ +@@ -92,7 +112,7 @@ + + /* Configure SDRAM */ + +- ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */ ++ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 (0xf38000b0)*/ + str r0,[r1,#0x24] + + ldr r0,=0x0000022d /* CS1 Base Address register */ +@@ -110,7 +130,7 @@ + #if defined(CYG_HAL_STARTUP_ROMRAM) + mov r1,#0 + mov r2,#HAL_FLASH_PHYS_ADDR +- ldr r3,=(__heap1 - 0x04000000 + HAL_FLASH_PHYS_ADDR) ++ ldr r3,=(__heap1 - 0x08000000 + HAL_FLASH_PHYS_ADDR) + + mov r4,#0 + mov r6,#0 +@@ -129,11 +149,11 @@ + nop + nop + nop +-30: ++30: + #endif + + #endif + .endm +- ++ + #endif + +diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi +--- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 2004-11-29 17:35:46.000000000 +0100 ++++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 2005-03-10 14:56:07.137708600 +0100 +@@ -3,34 +3,32 @@ + MEMORY + { + noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024 +- dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024 +- codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024 ++ codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024 ++ datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024 + } + + SECTIONS + { + SECTIONS_BEGIN +- _dataram = 0x4000000; ++ _dataram = 0x8000000; + SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA) + SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA) +- code_start = . + 0x8000000; +- SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000)) ++ code_start = . + 0x4000000; ++ SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000)) + fini = .; +- SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000)) ++ SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000)) + rodata = .; +- SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000)) ++ SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000)) + rodata1 = .; +- SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000)) ++ SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000)) + fixup = .; +- SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000)) ++ SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000)) + gcc_except_table =.; +- SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000)) +- data_start = ALIGN(0x4) - 0x4000000; +- SECTION_data (dataram, data_start, AT (data_start - 0x4000000)) ++ SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000)) ++ data_start = ALIGN(0x4) + 0x4000000; ++ SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000)) + bss = .; +- SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000)) ++ SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000)) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END + } +- +- +diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi +--- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 2004-11-29 17:35:46.000000000 +0100 ++++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 2005-03-10 14:56:18.184583600 +0100 +@@ -3,34 +3,32 @@ + MEMORY + { + noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024 +- dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024 +- codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024 ++ codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024 ++ datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024 + } + + SECTIONS + { + SECTIONS_BEGIN +- _dataram = 0x4000000; ++ _dataram = 0x8000000; + SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA) + SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA) +- code_start = . + 0x8000000; +- SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000)) ++ code_start = . + 0x4000000; ++ SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000)) + fini = .; +- SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000)) ++ SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000)) + rodata = .; +- SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000)) ++ SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000)) + rodata1 = .; +- SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000)) ++ SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000)) + fixup = .; +- SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000)) +- gcc_except_table = .; +- SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000)) +- data_start = . - 0x4000000; +- SECTION_data (dataram, data_start, AT (data_start - 0x4000000)) ++ SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000)) ++ gcc_except_table =.; ++ SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000)) ++ data_start = ALIGN(0x4) + 0x4000000; ++ SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000)) + bss = .; +- SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000)) ++ SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000)) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END + } +- +- +diff -Naur orig/hal/arm/netarm/current/src/netarm_misc.c new/hal/arm/netarm/current/src/netarm_misc.c +--- orig/hal/arm/netarm/current/src/netarm_misc.c 2004-11-29 17:35:48.000000000 +0100 ++++ new/hal/arm/netarm/current/src/netarm_misc.c 2005-02-22 11:57:58.296703200 +0100 +@@ -7,15 +7,15 @@ + //========================================================================== + //========================================================================== + //#####DESCRIPTIONBEGIN#### +-// ++// + // Author(s): Peter De Schrijver (p2@mind.be) + // Contributors: Peter De Schrijver (p2@mind.be) + // Date: 2002-10-25 + // Purpose: HAL board support + // Description: Implementations of HAL board interfaces +-// ++// + //####DESCRIPTIONEND#### +-// ++// + //========================================================================*/ + + #include <pkgconf/hal.h> +@@ -29,7 +29,7 @@ + #include <cyg/hal/hal_io.h> // IO macros + #include <cyg/hal/hal_arch.h> // Register state info + #include <cyg/hal/hal_diag.h> +-#include <cyg/hal/hal_intr.h> // Interrupt names ++#include <cyg/hal/hal_intr.h> // Interrupt names + #include <cyg/hal/hal_cache.h> + #include <cyg/hal/hal_netarm.h> // Hardware definitions + #include <cyg/hal/hal_if.h> // calling interface API +@@ -74,9 +74,9 @@ + void hal_clock_read(cyg_uint32 *pvalue) { + + static cyg_uint32 clock_val; +- +- clock_val=*TIMERSTAT1 & 0x1ff; +- *pvalue = (cyg_uint32)(_period - clock_val); ++ ++ clock_val=*TIMERSTAT1 & 0x1ff; ++ *pvalue = (cyg_uint32)(_period - clock_val); + + } + +@@ -97,24 +97,19 @@ + + void hal_hardware_init(void) { + ++#if defined (CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP) || \ ++ defined (CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP) + +-#ifdef ENABLECACHE +- /* CS1 BSIZE = 4 */ +- *OR1&=~(3 << 4); +- *OR1|=1 << 4; +- +- HAL_ICACHE_ENABLE(); +-#endif /* ENABLECACHE */ ++ HAL_CACHE_ENABLE(); + ++#endif /* ENABLECACHE */ + + *INTENABLE_CLR=0xffffffff; +- ++ + hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD); + + hal_if_init(); + +-// HAL_ICACHE_DISABLE(); +- + } + + int hal_spurious_ints; +@@ -125,8 +120,8 @@ + int i; + + stat=*INTSTATUS; +- +- for(i=0;i<CYGNUM_HAL_ISR_MAX;i++) ++ ++ for(i=0;i<CYGNUM_HAL_ISR_MAX;i++) + if(stat & (1<<i)) + return i+1; + +@@ -154,7 +149,7 @@ + + if((vector>=CYGNUM_HAL_INTERRUPT_C0) && (vector<=CYGNUM_HAL_INTERRUPT_C3)) { + *PORTC|=1<< (vector+23); +- if(up) ++ if(up) + *PORTC|=1<< (vector+15); + else + *PORTC&=~(1<< (vector+15));
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/doc/readme @@ -0,0 +1,6 @@ +The HAL for the ARM NET+50 can be downloaded at ftp.mind.be + +To support data and instruction caching I made some modification to +the HAL that are available as a patch to be found in this +directory. Applying this patch is optional, but should improve +performance.
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/MII.c @@ -0,0 +1,218 @@ +//========================================================================== +// +// MII.c +// +// NetSilion NET+ARM PHY chip configuration +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: PHY chip configuration +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <stdio.h> +#include <pkgconf/devs_eth_arm_netarm.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_io.h> +#include "eth_regs.h" + +#define PHYS(_i_) (0x800 | _i_) + +#define SysReg (unsigned int*)0xffb00004 // System Status Register + +/* Function: void mii_poll_busy (void) + * + * Description: + * This routine is responsible for waiting for the current PHY + * operation to complete. + * + * Parameters: + * none + */ + +void mii_poll_busy(void) +{ + /* check to see if PHY is busy with read or write */ + while (MIIIR & 1) + HAL_DELAY_US(1); +} + +/* Function: void mii_reset (void) + * + * Description: + * + * This routine resets the PHY. + * + * Return Values: + * none + */ + +void mii_reset(void) +{ + MIIAR = PHYS(0); // select command register + MIIWDR = 0x8000; // reset + mii_poll_busy(); +} + +/* Function: cyg_bool mii_negotiate (void) + * + * Description: + * This routine is responsible for causing the external Ethernet PHY + * to begin the negotatiation process. + * + * Parameters: + * none + * + * Return Value: + * 0: SUCCESS + * 1: ERROR + */ + +cyg_bool mii_negotiate(void) +{ + int timeout = 100000; + + MIIAR = PHYS(4); + + mii_poll_busy(); + + MIIAR = PHYS(0); + MIIWDR |= 0x1200; + + mii_poll_busy(); + + while(timeout) + { + MIIAR = PHYS(1); + MIICR = 1; + + mii_poll_busy(); + + if(0x24 == (MIIRDR & 0x24)) + return 0; + else + timeout--; + } + + return 1; +} + + +/* Function: void mii_set_speed (cyg_bool speed, cyg_bool duplex) + * + * Description: + * + * This routine will set the speed and duplex of the external PHY. + * + * Parameters: + * Speed + * 0: 10Mbit + * 1: 100Mbit + * Duplex + * 0: Half + * 1: Full + * + * Return Values: + * none + */ + +void mii_set_speed(cyg_bool speed, cyg_bool duplex) +{ + unsigned long int timeout = 1000000; + + MIIAR = PHYS(0); // select command register + MIIWDR = (speed << 13) | (duplex << 8); // set speed and duplex + mii_poll_busy(); + + + while(timeout) + { + MIIAR = PHYS(1); // select status register + MIICR = 1; + mii_poll_busy(); + if((MIIRDR) & 0x4) + break; + timeout--; + } +} + +/* Function: cyg_bool mii_check_speed + * + * Description: + * + * This routine will check the operating speed of the ethernet + * interface. + * + * Parameters: + * none + * + * Return Values: + * 0: 10Mbit Speed + * 1: 100Mbit Speed + */ + +cyg_bool mii_check_speed(void) +{ + MIIAR = PHYS(17); + MIICR = 1; + mii_poll_busy(); + return (MIIRDR >> 14) & 1; +} + +/* Function: void mii_check_duplex + * + * Description: + * + * This routine will check the operating duplex of the ethernet + * interface. + * + * Parameters: + * none + * + * Return Values: + * 0: Half Duplex + * 1: Full Duplex + */ + +cyg_bool mii_check_duplex(void) +{ + MIIAR = PHYS(17); + MIICR = 1; + mii_poll_busy(); + return (MIIRDR >> 9) & 1; +}
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/MII.h @@ -0,0 +1,56 @@ +#ifndef _NETARM_MII_ +#define _NETARM_MII_ +// ==================================================================== +// +// MII.h +// +// PHY chip configuration +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: Functions for PHY control +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +void mii_reset(void); +void mii_set_speed (cyg_bool speed, cyg_bool duplex); +cyg_bool mii_check_speed(void); +cyg_bool mii_check_duplex(void); +cyg_bool mii_negotiate(void); + +#endif
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/eeprom.c @@ -0,0 +1,204 @@ +// ==================================================================== +// +// eeprom.c +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 10.03.2005 +// Purpose: EEPROM I/O +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#include <cyg/hal/hal_netarm.h> +#include <sys/types.h> + +static void wait(int time) +{ + int i; + + for(i=0; i < time; i++); +} + +static void i2cStop(void) +{ + *PORTC |= 0x00c00000; + *PORTC &= ~0x000000c0; // SDA = 0, SLK = 0 + wait(5); + *PORTC |= 0x00000040; // SLK = 1 + wait(5); + *PORTC |= 0x00000080; // SDA = 1 +} + +static void i2cStart(void) +{ + *PORTC |= 0x00c000c0; // SDA = 1, SLK = 1 + wait(5); + *PORTC &= ~0x00000080; // SDA = 0 + wait(5); + *PORTC &= ~0x00000040; // SLK = 0 +} + +static void i2cPutByte(char byte) +{ + int i, bit; + + *PORTC |= 0x00c00000; + + for(i=7; i >= 0; i--) + { + bit = (byte >> i) & 1; + *PORTC = (*PORTC & ~0x80) | (bit << 7); // SDA = data + *PORTC |= 0x00000040; // SLK = 1 + wait(5); + *PORTC &= ~0x00000040; // SLK = 0 + wait(5); + } + *PORTC |= 0x00000080; // SDA = 1 +} + +static char i2cGetByte(void) +{ + int i; + char byte = 0; + + *PORTC &= ~0x00800000; + for(i=7; i >= 0; i--) + { + *PORTC |= 0x00000040; // SLK = 1 + byte |= ((*PORTC & 0x80) >> 7) << i; // data = SDA + wait(5); + *PORTC &= ~0x00000040; // SLK = 0 + wait(5); + } + *PORTC |= 0x00800080; // SDA = 1 + return byte; +} + +static void i2cGiveAck(void) +{ + *PORTC |= 0x00c00000; + *PORTC &= ~0x00000080; // SDA = 0 + wait(5); + *PORTC |= 0x00000040; // SLK = 1 + wait(5); + *PORTC &= ~0x00000040; // SLK = 0 + wait(5); + *PORTC |= 0x00000080; // SDA = 1 + wait(5); +} + +static void i2cGetAck(void) +{ + *PORTC &= ~0x00800000; // SDA in + *PORTC |= 0x00400040; // SLK = 1 + while(*PORTC & 0x80); // wait for SDA = 1 + *PORTC &= ~0x00000040; // SLK = 0 +} + +void initI2C(void) +{ + *PORTC &= ~0xc0000000; // mode GPIO + i2cStop(); +} + +void eepromPollAck(int deviceAddr) +{ + deviceAddr <<= 1; + + *PORTC |= 0x00400040; // SLK = 1 + while(1) + { + i2cStart(); + i2cPutByte(deviceAddr); + *PORTC &= ~0x00800000; // SDA in + *PORTC |= 0x00400040; // SLK = 1 + if((*PORTC & 0x80) == 0) + { + *PORTC &= ~0x00000040; // SLK = 0 + break; + } + *PORTC &= ~0x00000040; // SLK = 0 + } +} + +void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes) +{ + int i; + + deviceAddr <<= 1; + i2cStart(); + i2cPutByte(deviceAddr); + i2cGetAck(); + i2cPutByte(readAddr >> 8); + i2cGetAck(); + i2cPutByte(readAddr & 0xff); + i2cGetAck(); + i2cStart(); + i2cPutByte(deviceAddr | 1); // set read flag + i2cGetAck(); + + for(i=0;i<numBytes;i++) + { + buf[i] = i2cGetByte(); + if(i < numBytes - 1) + i2cGiveAck(); + } + + i2cStop(); +} + +void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes) +{ + int i; + + deviceAddr <<= 1; + i2cStart(); + i2cPutByte(deviceAddr); + i2cGetAck(); + i2cPutByte(writeAddr >> 8); + i2cGetAck(); + i2cPutByte(writeAddr & 0xff); + i2cGetAck(); + + for(i=0; i<numBytes; i++) + { + i2cPutByte(buf[i]); + i2cGetAck(); + } + + i2cStop(); +}
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/eeprom.h @@ -0,0 +1,58 @@ +#ifndef _NETARM_EEPROM__ +#define _NETARM_EEPROM__ + +// ==================================================================== +// +// eeprom.h +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 10.03.2005 +// Purpose: EEPROM interface +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +/* a block of max. 32 bytes can be written at once */ +void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes); +/* reads out as many bytes as desired */ +void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes); +/* blocks until the internal write cycle, initiated after eepromWrite, + completes */ +void eepromPollAck(int deviceAddr); +void initI2C(void); + +#endif
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/eth_regs.h @@ -0,0 +1,120 @@ +#ifndef _NETARM_ethregs_ +#define _NETARM_ethregs_ +// ==================================================================== +// +// eth_regs.h +// +// Address mappings for ethernet and DMA controller registers +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: Ethernet and DMA controller registers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Ethernet + +#define EthGenCR *(volatile unsigned *)0xff800000 +#define EthGenSR *(volatile unsigned *)0xff800004 +#define EthFIFODR *(volatile unsigned *)0xff800008 +#define EthFIFODRkickoff *(volatile unsigned *)0xff80000c +#define EthTxSR *(volatile unsigned *)0xff800010 +#define EthRxSR *(volatile unsigned *)0xff800014 +#define MACCR *(volatile unsigned *)0xff800400 +#define MACTR *(volatile unsigned *)0xff800404 +#define PCSCR *(volatile unsigned *)0xff800408 +#define PCSTR *(volatile unsigned *)0xff80040c +#define STLCR *(volatile unsigned *)0xff800410 +#define STLTR *(volatile unsigned *)0xff800414 +#define BtBIPGGapTimerR *(volatile unsigned *)0xff800440 +#define NonBtBIPGGapTimerR *(volatile unsigned *)0xff800444 +#define CollWinR *(volatile unsigned *)0xff800448 +#define TxPNCR *(volatile unsigned *)0xff800460 +#define TxBCR *(volatile unsigned *)0xff800464 +#define ReTxBCR *(volatile unsigned *)0xff800468 +#define TxRNG *(volatile unsigned *)0xff80046c +#define TxMRN *(volatile unsigned *)0xff800470 +#define TxCDec *(volatile unsigned *)0xff800474 +#define TOTxC *(volatile unsigned *)0xff800478 +#define RxBC *(volatile unsigned *)0xff800480 +#define RxCDec *(volatile unsigned *)0xff800484 +#define TORxC *(volatile unsigned *)0xff800488 +#define LnFC *(volatile unsigned *)0xff8004c0 +#define JC10M *(volatile unsigned *)0xff800500 +#define LoCC10M *(volatile unsigned *)0xff800504 +#define MIICR *(volatile unsigned *)0xff800540 +#define MIIAR *(volatile unsigned *)0xff800544 +#define MIIWDR *(volatile unsigned *)0xff800548 +#define MIIRDR *(volatile unsigned *)0xff80054c +#define MIIIR *(volatile unsigned *)0xff800550 +#define CRCEC *(volatile unsigned *)0xff800580 +#define AEC *(volatile unsigned *)0xff800584 +#define CEC *(volatile unsigned *)0xff800588 +#define LFC *(volatile unsigned *)0xff80058c +#define SFC *(volatile unsigned *)0xff800590 +#define LCC *(volatile unsigned *)0xff800594 +#define EDC *(volatile unsigned *)0xff800598 +#define MCC *(volatile unsigned *)0xff80059c +#define SAFR *(volatile unsigned *)0xff8005c0 +#define SAR1 *(volatile unsigned *)0xff8005c4 +#define SAR2 *(volatile unsigned *)0xff8005c8 +#define SAR3 *(volatile unsigned *)0xff8005cc +#define SAMHT1 *(volatile unsigned *)0xff8005d0 +#define SAMHT2 *(volatile unsigned *)0xff8005d4 +#define SAMHT3 *(volatile unsigned *)0xff8005d8 +#define SAMHT4 *(volatile unsigned *)0xff8005dc + +// DMA + +#define DMA1A_BDP *(volatile unsigned *)0xff900000 +#define DMA1A_CR *(volatile unsigned *)0xff900010 +#define DMA1A_SR *(volatile unsigned *)0xff900014 +#define DMA1B_BDP *(volatile unsigned *)0xff900020 +#define DMA1B_CR *(volatile unsigned *)0xff900030 +#define DMA1B_SR *(volatile unsigned *)0xff900034 +#define DMA1C_BDP *(volatile unsigned *)0xff900040 +#define DMA1C_CR *(volatile unsigned *)0xff900050 +#define DMA1C_SR *(volatile unsigned *)0xff900054 +#define DMA1D_BDP *(volatile unsigned *)0xff900060 +#define DMA1D_CR *(volatile unsigned *)0xff900070 +#define DMA1D_SR *(volatile unsigned *)0xff900074 +#define DMA2_BDP *(volatile unsigned *)0xff900080 +#define DMA2_CR *(volatile unsigned *)0xff900090 +#define DMA2_SR *(volatile unsigned *)0xff900094 + +#endif
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.c @@ -0,0 +1,715 @@ +//========================================================================== +// +// netarm_eth_drv.c +// +// NetSilion NET+ARM Ethernet Driver (DMA driven) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: NET+ARM Ethernet Driver (DMA driven) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/drv_api.h> +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> + +#include <pkgconf/devs_eth_arm_netarm.h> +#include <cyg/hal/hal_platform_ints.h> +#include "eth_regs.h" +#include "MII.h" +#include "netarm_eth_drv.h" +#include "eeprom.h" + +#include <cyg/hal/hal_io.h> + +// FIXME: The HAL should provide this +#define CYGNUM_HAL_INTERRUPT_DMA2 31 +#define CYGNUM_HAL_INTERRUPT_DMA1 32 + +// FIXME: The HAL should provide this and it should handle more than +// RAM addresses +#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr ) (unsigned char *)vaddr - 0x8000000 + +#define BufferSizeA 128 +#define BufferSizeB 512 +#define BufferSizeC 1524 + +#define NumA 16 +#define NumB 8 +#define NumC 8 + +#define EEPROM_MAC 0 // location of MAC address inside eeprom + +static cyg_mutex_t Key_Mutex; +static private_data_t driver_private; + +static volatile unsigned char RxBufferA[NumA][BufferSizeA]; +static volatile unsigned char RxBufferB[NumB][BufferSizeB]; +static volatile unsigned char RxBufferC[NumC][BufferSizeC]; + +static volatile unsigned char TxBuffer[1500]; +static volatile unsigned char TxHeader[14]; + +static volatile BDP_t RxBDP_A[NumA]; +static volatile BDP_t RxBDP_B[NumB]; +static volatile BDP_t RxBDP_C[NumC]; + +static volatile BDP_t TxBDP[2]; + +// relocation pointer for data accessed by DMA to enable caching +static volatile unsigned char *pRxBufferA, *pRxBufferB, *pRxBufferC; +static volatile unsigned char *pTxHeader, *pTxBuffer; +static volatile BDP_t *pRxBDP_A, *pRxBDP_B, *pRxBDP_C; +static volatile BDP_t *pTxBDP; + +ETH_DRV_SC(netarm_sc, + (void *)&driver_private, // driver specific data + "eth0", // Name for this interface + netarm_start, + netarm_stop, + netarm_control, + netarm_can_send, + netarm_send, + netarm_recv, + netarm_deliver, + netarm_poll, + netarm_int_vector); + +NETDEVTAB_ENTRY(netarm_netdev, + "ETH_DRV", + netarm_init, + &netarm_sc); + +static void +fastcopy(void *buf, void *data, unsigned long len) +{ + asm volatile( + + "STMDB SP!, {R11};" + + "TST R1, #2;" // test if aligned + "LDRNEH R3, [R1], #2;" + "STRNEH R3, [R0], #2;" + "SUBNE R2, R2, #2;" + "TST R1, #1;" + "LDRNEB R3, [R1], #1;" + "STRNEB R3, [R0], #1;" + "SUBNE R2, R2, #1;" + + ".START:" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "BGE .START;" + + + ".LASTBYTES:" + + "AND R14, R2, #0xfffffffc;" + "LDR PC, [PC, R14];" + "NOP;" + + ".SWITCH:" + ".word .CASE0;" + ".word .CASE1;" + ".word .CASE2;" + ".word .CASE3;" + ".word .CASE4;" + ".word .CASE5;" + ".word .CASE6;" + ".word .CASE7;" + ".word .CASE8;" + ".word .CASE9;" + ".word .CASE10;" + + ".CASE0:" + "B .END;" + + ".CASE1:" + "LDR R3, [R1]!;" + "STR R3, [R0]!;" + "B .END;" + + ".CASE2:" + "LDMIA R1!, {R3, R4};" + "STMIA R0!, {R3, R4};" + "B .END;" + + ".CASE3:" + "LDMIA R1!, {R3 - R5};" + "STMIA R0!, {R3 - R5};" + "B .END;" + + ".CASE4:" + "LDMIA R1!, {R3 - R6};" + "STMIA R0!, {R3 - R6};" + "B .END;" + + ".CASE5:" + "LDMIA R1!, {R3 - R7};" + "STMIA R0!, {R3 - R7};" + "B .END;" + + ".CASE6:" + "LDMIA R1!, {R3 - R8};" + "STMIA R0!, {R3 - R8};" + "B .END;" + + ".CASE7:" + "LDMIA R1!, {R3 - R9};" + "STMIA R0!, {R3 - R9};" + "B .END;" + + ".CASE8:" + "LDMIA R1!, {R3 - R10};" + "STMIA R0!, {R3 - R10};" + "B .END;" + + ".CASE9:" + "LDMIA R1!, {R3 - R11};" + "STMIA R0!, {R3 - R11};" + "B .END;" + + ".CASE10:" + "LDMIA R1!, {R3 - R12};" + "STMIA R0!, {R3 - R12};" + + ".END:" + "TST R2, #2;" + "LDRNEH R3, [R1], #2;" + "STRNEH R3, [R0], #2;" + "TST R2, #1;" + "LDRNEB R3, [R1], #1;" + "STRNEB R3, [R0], #1;" + + "LDMIA SP!, {R11};" + + : + : "r" (buf), "r" (data), "r" (len) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14" + ); +} + +static bool +KeyBufferFull(private_data_t *pd) +{ + int tmp = 0; + + cyg_drv_mutex_lock(&Key_Mutex); + + if((pd->key_head + 1) % MaxKeys == pd->key_tail) + { + tmp = 1; + } + + cyg_drv_mutex_unlock(&Key_Mutex); + + return tmp; +} + +static void +AddKey(unsigned long key, private_data_t *pd) +{ + + cyg_drv_mutex_lock(&Key_Mutex); + + pd->KeyBuffer[pd->key_head] = key; + pd->key_head = (pd->key_head + 1) % MaxKeys; + + cyg_drv_mutex_unlock(&Key_Mutex); +} + +static unsigned +GetKey(private_data_t *pd) +{ + unsigned key = 0; + + cyg_drv_mutex_lock(&Key_Mutex); + + if(pd->key_tail != pd->key_head) + { + key = pd->KeyBuffer[pd->key_tail]; + pd->key_tail = (pd->key_tail + 1) % MaxKeys; + } + + cyg_drv_mutex_unlock(&Key_Mutex); + + return key; +} + +static cyg_uint32 +dma_rx_isr(cyg_vector_t vector, cyg_addrword_t data) +{ + + // block this interrupt until the dsr completes + cyg_drv_interrupt_mask(vector); + + // tell ecos to allow further interrupt processing + cyg_drv_interrupt_acknowledge(vector); + + return CYG_ISR_CALL_DSR; // call the dsr +} + +static void +dma_rx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + + eth_drv_dsr( vector, count, data ); + + DMA1A_SR = 0x80000000; // acknowledge and mask interrupts + DMA1B_SR = 0x80000000; + DMA1C_SR = 0x80000000; + + cyg_drv_interrupt_unmask(vector); +} + +static cyg_uint32 +dma_tx_isr(cyg_vector_t vector, cyg_addrword_t data) +{ + + // block this interrupt until the dsr completes + cyg_drv_interrupt_mask(vector); + + // tell ecos to allow further interrupt processing + cyg_drv_interrupt_acknowledge(vector); + + return CYG_ISR_CALL_DSR; // invoke the dsr +} + +static void +dma_tx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + + eth_drv_dsr( vector, count, data ); + + DMA2_SR |= 0x80000000; // acknowledge interrupt + + cyg_drv_interrupt_unmask(vector); +} + +static void +SetupDMA(void) +{ + int i; + + pRxBufferA = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferA); + pRxBufferB = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferB); + pRxBufferC = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferC); + + pTxBuffer = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxBuffer); + pTxHeader = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxHeader); + + pRxBDP_A = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_A); + pRxBDP_B = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_B); + pRxBDP_C = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_C); + + pTxBDP = (BDP_t *)((unsigned char *)TxBDP); + + *SYSCON |= 0x40; // reset DMA module + + for(i = 0; i < NumA; i++) + { + pRxBDP_A[i].lo = ((unsigned)(pRxBufferA+i*BufferSizeA)) & 0x3fffffff; + pRxBDP_A[i].hi = BufferSizeA; + } + + pRxBDP_A[i - 1].lo |= 0x80000000; // set W bit + + for(i = 0; i < NumB; i++) + { + pRxBDP_B[i].lo = ((unsigned)(pRxBufferB+i*BufferSizeB)) & 0x3fffffff; + pRxBDP_B[i].hi = BufferSizeB; + } + + pRxBDP_B[i - 1].lo |= 0x80000000; + + for(i = 0; i < NumC; i++) + { + pRxBDP_C[i].lo = ((unsigned)(pRxBufferC+i*BufferSizeC)) & 0x3fffffff; + pRxBDP_C[i].hi = BufferSizeC; + } + + pRxBDP_C[i - 1].lo |= 0x80000000; + + *SYSCON &= ~0x40; + + DMA1A_BDP = (unsigned)pRxBDP_A; + DMA1A_CR = 0x82000000; //burst transfer + DMA1A_SR = 0xa00000; + + DMA1B_BDP = (unsigned)pRxBDP_B; + DMA1B_CR = 0x82000000; //burst transfer + DMA1B_SR = 0xa00000; + + DMA1C_BDP = (unsigned)pRxBDP_C; + DMA1C_CR = 0x82000000; //burst transfer + DMA1C_SR = 0xa00000; + + + pTxBDP[0].lo = ((unsigned)pTxHeader) & 0x3fffffff; + pTxBDP[1].lo = ((unsigned)pTxBuffer) & 0x3fffffff; + pTxBDP[1].lo |= 0xa0000000; // set W and L bit + + DMA2_BDP = (unsigned)pTxBDP; + DMA2_CR = 0x86000000; //burst transfer + DMA2_SR = 0x800000; + +} + +static bool +netarm_init(struct cyg_netdevtab_entry *tab) +{ + struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; + cyg_bool duplex; + static cyg_interrupt dma_rx_int_object, dma_tx_int_object; + static cyg_handle_t dma_rx_int_handle, dma_tx_int_handle; + +#ifdef CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_SET_ESA + + unsigned char esa[6] = CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA; +#else + unsigned char esa[6]; + + initI2C(); + eepromRead(0x50, EEPROM_MAC, esa, 6); +#endif + + // setup dma receiver + SetupDMA(); + + mii_reset(); + mii_negotiate(); // initialize PHY + duplex = mii_check_duplex(); + + // Ethernet Controller Initializatition + + MACCR = (0x1c | (duplex << 1)); // auto CRC, late collision retry + STLCR = 0x3; // insert MAC source address + // into ethernet frame + BtBIPGGapTimerR = 0x14; // standard values + NonBtBIPGGapTimerR = ((0x9 << 7) | 0x11); // standard values + CollWinR = ((0x37 << 8) | 0xf); // standard values + SAFR = 0x1; // broadcast mode + EthGenCR = (0x40400400 | (duplex << 16)); // dma mode, full duplex, + // enable pNA mode(needed + // for alignment) + + cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA1, // Interrupt Vector + 0, // Interrupt Priority + (cyg_addrword_t)&netarm_sc, // Reference + // to Driver + // Instance + dma_rx_isr, + dma_rx_dsr, + &dma_rx_int_handle, + &dma_rx_int_object); + + cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA2, // Interrupt Vector + 0, // Interrupt Priority + (cyg_addrword_t)&netarm_sc, // Reference + // to Driver + // Instance + dma_tx_isr, + dma_tx_dsr, + &dma_tx_int_handle, + &dma_tx_int_object); + + cyg_drv_interrupt_attach(dma_rx_int_handle); + cyg_drv_interrupt_attach(dma_tx_int_handle); + + cyg_mutex_init(&Key_Mutex); + + sc->funs->eth_drv->init(sc, esa); + + return true; +} + +static void +netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) +{ + int i, len; + private_data_t *pd = (private_data_t *)(sc->driver_private); + unsigned char *data, *buf = pd->RxBuffer; + + for (i = 0; i < sg_len; i++) { + data = (unsigned char *)(sg_list[i].buf); + len = sg_list[i].len; + if (len) + { + if(i == 1) + { + buf += 2; + } + + fastcopy(data, buf, len); + buf += len; + } + } +} + +static void +netarm_deliver(struct eth_drv_sc *sc) +{ + static int a = 0, b = 0, c = 0; + unsigned long key; + private_data_t *pd = (private_data_t *)(sc->driver_private); + + while((key = GetKey(pd))) + { + sc->funs->eth_drv->tx_done(sc, key, 0); + } + + while(pRxBDP_A[a].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_A[a].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_A[a].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_A[a].hi = BufferSizeA; + HAL_REORDER_BARRIER(); + a = (a + 1) % NumA; + } + + while(pRxBDP_B[b].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_B[b].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_B[b].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_B[b].hi = BufferSizeB; + HAL_REORDER_BARRIER(); + b = (b + 1) % NumB; + } + + while(pRxBDP_C[c].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_C[c].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_C[c].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_C[c].hi = BufferSizeC; + HAL_REORDER_BARRIER(); + c = (c + 1) % NumC; + } + + if((DMA1A_SR & 0x20000000) || (DMA1B_SR & 0x20000000) || (DMA1C_SR & 0x20000000)) + { + EthGenCR &= ~0xc0000000; // reset Rx FIFO + EthGenCR |= 0xc0000000; + } + + DMA1A_SR = 0x20a00000; + DMA1B_SR = 0x20a00000; + DMA1C_SR = 0x20a00000; +} + +static int +netarm_can_send(struct eth_drv_sc *sc) +{ + private_data_t *pd = (private_data_t *)(sc->driver_private); + + if((pTxBDP[0].hi & 0x8000) || (pTxBDP[1].hi & 0x8000) || KeyBufferFull(pd)) + return 0; + + return 1; +} + +static void +netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, + int sg_len, int total_len, unsigned long key) +{ + private_data_t *pd = (private_data_t *)(sc->driver_private); + int i, len; + unsigned char *data; + volatile char *buf = pTxBuffer; + + AddKey(key, pd); + + // Put data into buffer + for (i = 0; i < sg_len; i++) { + data = (unsigned char *)sg_list[i].buf; + len = sg_list[i].len; + + if(i == 0) + { + if((unsigned long)data & 0x3) + { + memcpy((unsigned char*)pTxHeader, data, 0xe); + } + else + { + fastcopy((unsigned char *)pTxHeader, data, 0xe); + } + + len -= 0xe; + data += 0xe; + } + + if (len) + { + fastcopy((unsigned char *)buf, data, len); + buf += len; + } + } + + cyg_drv_dsr_lock(); + pTxBDP[0].hi = 0x800e; + HAL_REORDER_BARRIER(); + pTxBDP[1].hi = (total_len - 0xe) | 0x8000; + HAL_REORDER_BARRIER(); + DMA2_SR |= 0xf0000000; + cyg_drv_dsr_unlock(); +} + +static void +netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) +{ + SetMAC(enaddr); // set MAC address + HAL_REORDER_BARRIER(); + EthGenCR |= 0x80800000; // enable Rx und Tx FIFO + HAL_REORDER_BARRIER(); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA1); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA2); +} + +static void +netarm_stop(struct eth_drv_sc *sc) +{ + EthGenCR &= 0x7f7fffff; + HAL_REORDER_BARRIER(); + cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA1); + cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA2); +} + +static int +netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, int len) +{ + switch (key) + { + case ETH_DRV_SET_MAC_ADDRESS: + return 0; + break; + case ETH_DRV_SET_MC_LIST: + case ETH_DRV_SET_MC_ALL: + return 0; + default: + return 1; + break; + } +} + +static void +netarm_poll(struct eth_drv_sc *sc) +{ +} + +static int +netarm_int_vector(struct eth_drv_sc *sc) +{ + return CYGNUM_HAL_INTERRUPT_DMA1; +} + +static void +SetMAC(unsigned char *esa) +{ + SAR1 = (esa[1] << 8) | esa[0]; // set MAC address + SAR2 = (esa[3] << 8) | esa[2]; + SAR3 = (esa[5] << 8) | esa[4]; +}
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.h @@ -0,0 +1,86 @@ +#ifndef NETARM_ETH_DRV_H +#define NETARM_ETH_DRV_H + +//==================================================================== +// +// netarm_eth_drv.h +// +// Device I/O - Description of NET+ARM ethernet hardware functions +// and data structures +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2005 eCosCentric LTD +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: Internal interfaces and data structures +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +#define MaxKeys 20 + +typedef struct +{ + unsigned char *RxBuffer; + unsigned short key_head, key_tail; + unsigned KeyBuffer[MaxKeys]; +}private_data_t; + +typedef struct +{ + unsigned lo; + unsigned hi; +}BDP_t; + + +static bool netarm_init(struct cyg_netdevtab_entry *tab); + +static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, + int sg_len); +static void netarm_deliver(struct eth_drv_sc *sc); +static int netarm_can_send(struct eth_drv_sc *sc); +static void netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, + int sg_len, int total_len, unsigned long key); +static void netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags); +static void netarm_stop(struct eth_drv_sc *sc); +static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, + int len); +static void netarm_poll(struct eth_drv_sc *sc); +static int netarm_int_vector(struct eth_drv_sc *sc); + +static void SetMAC(unsigned char *esa); + +#endif //NETARM__ETH_DRV_H +
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -1130,6 +1130,14 @@ package CYGPKG_DEVS_ETH_ARM_CERFPDA { description "Ethernet driver for Crystal LAN on the Cerfpda." } +package CYGPKG_DEVS_ETH_ARM_NETARM { + alias { "Ethernet driver for the NETARM" NETARM_eth_driver } + hardware + directory devs/eth/arm/netarm + script netarm_eth_driver.cdl + description "Ethernet driver for NETARM." +} + package CYGPKG_IO_SERIAL_SH_EDK7708 { alias { "SH3 EDK7708 serial device drivers" devs_serial_sh3_edk7708