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changeset 1729:ea82d8fd5dd6

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Support new board rev 1.1
author gthomas
date Tue, 24 Aug 2004 13:16:52 +0000
parents 650ae718ca77
children 3175dbfa11a7
files packages/hal/powerpc/moab/current/ChangeLog packages/hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl packages/hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h packages/hal/powerpc/moab/current/sa_tests/start.S packages/hal/powerpc/moab/current/sa_tests/tty.c packages/hal/powerpc/moab/current/src/moab.S
diffstat 6 files changed, 77 insertions(+), 37 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/powerpc/moab/current/ChangeLog
+++ b/packages/hal/powerpc/moab/current/ChangeLog
@@ -1,3 +1,12 @@
+2004-08-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/moab.S: 
+	* sa_tests/tty.c: 
+	* sa_tests/start.S: 
+	* include/pkgconf/mlt_powerpc_moab_romram.h: 
+	* cdl/hal_powerpc_moab.cdl: Support for new board revision.  Minor
+	layout changes, change in RAM/FLASH sizes.
+
 2004-02-26  Gary Thomas  <gary@mlbassoc.com>
 
 	* misc/redboot_BOOT.ecm: 
--- a/packages/hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl
+++ b/packages/hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl
@@ -102,11 +102,21 @@ cdl_package CYGPKG_HAL_POWERPC_MOAB {
            the existence of a debug environment, such as GDB stubs."
     }
 
+    cdl_component CYG_HAL_MOAB_BOARD_REVISION {
+        display       "PC revision"
+        flavor        data
+        legal_values  {"1_0" "1_1"}
+        default_value {"1_1"}
+        description   "
+           This option describes the board (PC) revision.  Certain changes were
+           made between the various revisions and this allows the kernel to adapt."
+    }
+
     cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
         display          "Development board clock speed (MHz)"
         flavor           data
-        legal_values     250 333
-        default_value    250
+        legal_values     250 300 333 400
+        default_value    { CYG_HAL_MOAB_BOARD_REVISION == "1_1" ? 400 : 250 }
         description      "
            MOAB Development Boards have various system clock speeds
            depending on the processor and oscillator fitted.  Select 
@@ -117,7 +127,7 @@ cdl_package CYGPKG_HAL_POWERPC_MOAB {
    cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
         display          "Development board memory bus speed (MHz)"
         flavor           data
-        legal_values     66
+        legal_values     66 100 133
         default_value    66
         description      "
            MOAB Development Boards have various system clock speeds
--- a/packages/hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h
+++ b/packages/hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h
@@ -8,7 +8,7 @@
 
 #endif
 #define CYGMEM_REGION_ram (0)
-#define CYGMEM_REGION_ram_SIZE (0x2000000)
+#define CYGMEM_REGION_ram_SIZE (0x4000000)
 #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
 #define CYGMEM_REGION_rom (0xfff80000)
 #define CYGMEM_REGION_rom_SIZE (0x80000)
@@ -16,4 +16,4 @@
 extern char CYG_LABEL_NAME (__heap1) [];
 #endif
 #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
-#define CYGMEM_SECTION_heap1_SIZE (0x2000000 - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
--- a/packages/hal/powerpc/moab/current/sa_tests/start.S
+++ b/packages/hal/powerpc/moab/current/sa_tests/start.S
@@ -2,14 +2,14 @@
 // Simple test code framework
 //
 //-----------------------------------------------------------------
-// Copyright (C) 2003, Gary Thomas <gary@mlbassoc.com>
+// Copyright (C) 2003, 2004 Gary Thomas <gary@mlbassoc.com>
 //-----------------------------------------------------------------
 
 #include "ppc.inc"        
         
-#define GPIO0           0xEF600700        
-#define GPIO0_OR        GPIO0+0x000
-#define GPIO0_TCR       GPIO0+0x004
+#define GPIO0           (0xEF600700)
+#define GPIO0_OR        (GPIO0+0x000)
+#define GPIO0_TCR       (GPIO0+0x004)
 
         .text
         .globl  start
@@ -27,6 +27,7 @@ 10:     dccci   0,r3
         cmpw    r3,r4
         bne     10b        
 
+#if 0 // Assume that 'boot' environment has set this up        
 //
 // Setup GPIO to drive LEDs
 //
@@ -34,6 +35,7 @@ 10:     dccci   0,r3
         li      r4,0x80
         stw     r4,GPIO0_TCR-GPIO0(r11)
         stw     r4,GPIO0_OR-GPIO0(r11)
+#endif        
 
         // Setup and clear a stack used by the C code
         lwi     sp,stack_base-4
--- a/packages/hal/powerpc/moab/current/sa_tests/tty.c
+++ b/packages/hal/powerpc/moab/current/sa_tests/tty.c
@@ -2,7 +2,7 @@
 // TTY support code
 //
 //-----------------------------------------------------------------
-// Copyright (C) 2003, Gary Thomas <gary@mlbassoc.com>
+// Copyright (C) 2003, 2004 Gary Thomas <gary@mlbassoc.com>
 //-----------------------------------------------------------------
 
 struct uart {
@@ -81,10 +81,12 @@ tty_init(void)
     uart->fcr = (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2);
     uart->fcr = 0;
 
+#if 0 // Assume that baud rate has been properly set
     // Set speed to 38400.
     uart->lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1 | SIO_LCR_DLAB;
     uart->dll = 0x12;
     uart->dlm = 0;
+#endif
 
     // 8-1-no parity.
     uart->lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1;
--- a/packages/hal/powerpc/moab/current/src/moab.S
+++ b/packages/hal/powerpc/moab/current/src/moab.S
@@ -9,7 +9,7 @@
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002, 2003 Gary Thomas
+## Copyright (C) 2002, 2003, 2004 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
@@ -60,8 +60,39 @@
 #------------------------------------------------------------------------------
 
 // No useable LEDs
-#define LED(x)                          
-	
+#define LED(x)
+
+//
+// Various setup values - based on board revision &/or xtal speed
+//                        
+#if defined(CYG_HAL_MOAB_BOARD_REVISION_1_0)
+#define MOAB_DCR_SDRAM0_RTR    0x05F00000
+#define MOAB_DCR_SDRAM0_B1CR   0x00062001                
+#define MOAB_DCR_SDRAM0_B0CR   0x02062001
+#define MOAB_DCR_SDRAM0_CFG    0x80800000
+#elif defined(CYG_HAL_MOAB_BOARD_REVISION_1_1)
+#define MOAB_DCR_SDRAM0_RTR    0x07F00000
+#define MOAB_DCR_SDRAM0_B1CR   0x00084001                        
+#define MOAB_DCR_SDRAM0_B0CR   0x00000000
+#define MOAB_DCR_SDRAM0_CFG    0x80800000
+#else
+#error "Illegal board revision"
+#endif                        
+#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250        
+#define MOAB_DCR_CPC0_CR0      0x09F8502A	
+#define MOAB_DCR_EBC0_B1AP     0x03840000           
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
+#define MOAB_DCR_CPC0_CR0      0x09F8503A
+#define MOAB_DCR_EBC0_B1AP     0x05840000           
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 300
+#define MOAB_DCR_CPC0_CR0      0x0FF85034        
+#define MOAB_DCR_EBC0_B1AP     0x0A840000           
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 400      
+#define MOAB_DCR_CPC0_CR0      0x0FF8503C
+#define MOAB_DCR_EBC0_B1AP     0x0C840000           
+#else
+#error "Illegal CPU speed"
+#endif                        
 #------------------------------------------------------------------------------       
                 
 FUNC_START( hal_hardware_init )
@@ -72,7 +103,6 @@ FUNC_START( hal_hardware_init )
         li      r3,0x00000000              // Make sure nothing is cacheable
         mticcr  r3
         mtdccr  r3
-
         // Force data caches to be totally clean
         lwi     r3,0
         lwi     r4,0x8000
@@ -83,14 +113,7 @@ 10:     dcbf    0,r3
         bne     10b
 
         // Basic chip configuration
-#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250        
-        lwi     r3,0x09f8102a
-        lwi     r3,0x09f8502a
-#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
-        lwi     r3,0x09f8503a
-#else
-#error "Unsupported board/CPU speed"        
-#endif
+        lwi     r3,MOAB_DCR_CPC0_CR0
         mtdcr   DCR_CPC0_CR0,r3
         li      r3,0x00000000
         mtdcr   DCR_CPC0_CR1,r3
@@ -115,7 +138,7 @@ 10:     dcbf    0,r3
         li      r3,DCR_SDRAM0_CFG          // See if SDRAM already configured
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mfdcr   r4,DCR_SDRAM0_CFGDATA
-        lwi     r3,0x80800000
+        lwi     r3,MOAB_DCR_SDRAM0_CFG        
         and     r4,r4,r3
         cmpw    r3,r4
         beq     sdram_ok
@@ -129,16 +152,17 @@ 10:     dcbf    0,r3
         lwi     r4,0x010A800E
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mtdcr   DCR_SDRAM0_CFGDATA,r4
-        li      r3,DCR_SDRAM0_RTR
-        lwi     r4,0x05F00000
+        li      r3,DCR_SDRAM0_RTR            // Refresh timing
+        lwi     r4,MOAB_DCR_SDRAM0_RTR  
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mtdcr   DCR_SDRAM0_CFGDATA,r4
         li      r3,DCR_SDRAM0_B1CR           // Note: non-ascending addresses because
-        lwi     r4,0x00062001                // the low 1/2 of memory fails on some boards
+                                             // the low 1/2 of memory fails on some boards        
+        lwi     r4,MOAB_DCR_SDRAM0_B1CR
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mtdcr   DCR_SDRAM0_CFGDATA,r4
         li      r3,DCR_SDRAM0_B0CR
-        lwi     r4,0x02062001
+        lwi     r4,MOAB_DCR_SDRAM0_B0CR
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mtdcr   DCR_SDRAM0_CFGDATA,r4
         
@@ -152,7 +176,7 @@ 13:     nop
         bdnz    13b
         
         li      r3,DCR_SDRAM0_CFG         // Enable controller
-        lwi     r4,0x80800000
+        lwi     r4,MOAB_DCR_SDRAM0_CFG        
         mtdcr   DCR_SDRAM0_CFGADDR,r3        
         mtdcr   DCR_SDRAM0_CFGDATA,r4
 
@@ -167,14 +191,7 @@ sdram_ok:
         mtdcr   DCR_EBC0_CFGADDR,r3
         mtdcr   DCR_EBC0_CFGDATA,r4
         li      r3,DCR_EBC0_B1AP          // MAIN FLASH at 0xCxxxxxxx, R/W
-#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250        
-        lwi     r4,0x03840000             // Cycle time = 50ns
-#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
-        lwi     r4,0x05840000            
-#else
-        lwi     r4,0x0C840000            
-#error "Unsupported board/CPU speed"        
-#endif
+        lwi     r4,MOAB_DCR_EBC0_B1AP
         mtdcr   DCR_EBC0_CFGADDR,r3
         mtdcr   DCR_EBC0_CFGDATA,r4
         li      r3,DCR_EBC0_B1CR
@@ -199,7 +216,7 @@ sdram_ok:
         lwi     r3,0x80000001              // DRAM can be cached - instructions only
         iccci   0,r3
         mticcr  r3
-        li      r3,0x00000000
+        lwi     r3,0x00000000
         mtdccr  r3
 
 #ifdef CYG_HAL_STARTUP_ROMRAM