Mercurial > ecos
changeset 568:eb5d4fbc238d
misc xscale fixes
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--- a/packages/hal/arm/xscale/cores/current/ChangeLog +++ b/packages/hal/arm/xscale/cores/current/ChangeLog @@ -1,3 +1,13 @@ +2003-02-04 Mark Salter <msalter@redhat.com> + + * cdl/hal_arm_xscale_core.cdl (CYGSEM_HAL_ARM_XSCALE_BTB): New option. + + * include/hal_xscale.h: Make enabling of BTB conditional on + CYGSEM_HAL_ARM_XSCALE_BTB. + + * include/hal_cache.h: Support systems using write-through caching + which need no DCACHE_FLUSH_AREA. + 2002-11-13 Mark Salter <msalter@redhat.com> * src/xscale_stub.c (find_watch_address): Squelch compiler warning. @@ -24,7 +34,7 @@ 2002-09-19 Mark Salter <msalter@redhat //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free
--- a/packages/hal/arm/xscale/cores/current/cdl/hal_arm_xscale_core.cdl +++ b/packages/hal/arm/xscale/cores/current/cdl/hal_arm_xscale_core.cdl @@ -62,4 +62,18 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_CORE { implements CYGINT_HAL_ARM_ARCH_XSCALE compile xscale_misc.c xscale_stub.c + + cdl_option CYGSEM_HAL_ARM_XSCALE_BTB { + display "Enable Branch Target Buffer" + flavor bool + default_value 1 + description " + This option controls whether or not the Branch Target + Buffer is enabled. The BTB is used for branch prediction + and can have significant performance benefits. Control + is provided because there is an errata for A-step 80200 + CPUS which will lead to problems with thumb branches + if the BTB is on. Normal ARM programs are not affected + by this errata." + } }
--- a/packages/hal/arm/xscale/cores/current/include/hal_cache.h +++ b/packages/hal/arm/xscale/cores/current/include/hal_cache.h @@ -11,7 +11,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -246,9 +246,12 @@ CYG_MACRO_START /* this macro can dis ); \ CYG_MACRO_END +// DCACHE_FLUSH_AREA is defined if writeback caching is used. Otherwise +// write-through is assumed. +#ifdef DCACHE_FLUSH_AREA -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() \ +// Evict dirty lines from write-back caches +#define HAL_DCACHE_EVICT() \ CYG_MACRO_START \ /* The best way to evict a dirty line is by using the */ \ /* line allocate operation on non-existent memory. */ \ @@ -260,6 +263,20 @@ CYG_MACRO_START "add r0, r0, #32;" /* 32 bytes/line */ \ "teq r1, r0;" \ "bne 667b;" \ + : \ + : "i" (DCACHE_FLUSH_AREA) \ + : "r0","r1" /* Clobber list */ \ + ); \ +CYG_MACRO_END +#else +#define HAL_DCACHE_EVICT() +#endif + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() \ +CYG_MACRO_START \ + HAL_DCACHE_EVICT(); \ + asm volatile ( \ "mcr p15,0,r0,c7,c6,0;" /* invalidate data cache */ \ /* cpuwait */ \ "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \ @@ -272,7 +289,7 @@ CYG_MACRO_START "sub pc,pc,#4;" \ "nop" \ : \ - : "i" (DCACHE_FLUSH_AREA) \ + : \ : "r0","r1" /* Clobber list */ \ ); \ CYG_MACRO_END @@ -289,9 +306,15 @@ CYG_MACRO_END #define HAL_DCACHE_WRITEBACK_MODE 1 // Get the current writeback mode - or only writeback mode if fixed +#ifdef DCACHE_FLUSH_AREA #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \ _mode_ = HAL_DCACHE_WRITEBACK_MODE; \ CYG_MACRO_END +#else +#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \ + _mode_ = HAL_DCACHE_WRITETHRU_MODE; \ +CYG_MACRO_END +#endif // Load the contents of the given address range into the data cache // and then lock the cache so that it stays there.
--- a/packages/hal/arm/xscale/cores/current/include/hal_xscale.h +++ b/packages/hal/arm/xscale/cores/current/include/hal_xscale.h @@ -8,7 +8,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -54,6 +54,7 @@ #define CYGONCE_HAL_ARM_XSCALE_HAL_XSCALE_H #include <pkgconf/system.h> +#include <pkgconf/hal_arm_xscale_core.h> #ifdef __ASSEMBLER__ // Useful CPU macros @@ -75,7 +76,11 @@ // Enable the BTB .macro BTB_INIT reg mrc p15, 0, \reg, c1, c0, 0 +#ifdef CYGSEM_HAL_ARM_XSCALE_BTB orr \reg, \reg, #MMU_Control_BTB +#else + bic \reg, \reg, #MMU_Control_BTB +#endif mcr p15, 0, \reg, c1, c0, 0 CPWAIT \reg .endm
--- a/packages/hal/arm/xscale/iop310/current/ChangeLog +++ b/packages/hal/arm/xscale/iop310/current/ChangeLog @@ -1,3 +1,9 @@ +2003-02-04 Mark Salter <msalter@redhat.com> + + * include/hal_iop310.h (IOP310_EARLY_PCI_SETUP): Fix ifdef test. + + * cdl/hal_arm_xscale_iop310.cdl: Remove CYGSEM_HAL_ARM_IOP310_BTB. + 2003-01-22 Mark Salter <msalter@redhat.com> * include/var_io.h: Remove unused duplicate code.
--- a/packages/hal/arm/xscale/iop310/current/cdl/hal_arm_xscale_iop310.cdl +++ b/packages/hal/arm/xscale/iop310/current/cdl/hal_arm_xscale_iop310.cdl @@ -294,19 +294,6 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_IOP310 compiler flags used only in building this package, and details of which tests are built." - cdl_option CYGSEM_HAL_ARM_IOP310_BTB { - display "Enable Branch Target Buffer" - flavor bool - default_value 0 - description " - Enable this option to turn on the IQ80200 Branch Target Buffer - which is used for branch prediction. This is turned off by - default because of CPU errata which may cause thumb branches - to execute improperly on A-step CPUs. Normal ARM programs are - not affected by this errata, so enabling this option for - ARM-only applications may improve program performance." - } - cdl_option CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY { display "Have RedBoot clear PCI Retry bit" flavor bool
--- a/packages/hal/arm/xscale/iop310/current/include/hal_iop310.h +++ b/packages/hal/arm/xscale/iop310/current/include/hal_iop310.h @@ -646,7 +646,7 @@ extern unsigned int _80312_EMISR; // On sub \reg1, \reg_dram_size, #1 // dram_size - 1 mvn \reg1, \reg1 // 1s complement str \reg1, [\reg0] -#ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY +#ifdef CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY ldr \reg0, =EBCR_ADDR mov \reg1, #0x0008 strh \reg1, [\reg0]
--- a/packages/hal/arm/xscale/iq80310/current/ChangeLog +++ b/packages/hal/arm/xscale/iq80310/current/ChangeLog @@ -1,3 +1,13 @@ +2003-01-31 Mark Salter <msalter@redhat.com> + + * include/hal_platform_setup.h: Disabling of write buffer + is not necessary. + + * misc/redboot_RAM.ecm: Don't enable BTB for RedBoot. + * misc/redboot_RAMA.ecm: Ditto. + * misc/redboot_ROM.ecm: Ditto. + * misc/redboot_ROMA.ecm: Ditto. + 2003-01-30 Mark Salter <msalter@redhat.com> * include/pkgconf/mlt_*: Adjust RAM size to match max supported.
--- a/packages/hal/arm/xscale/iq80310/current/include/hal_platform_setup.h +++ b/packages/hal/arm/xscale/iq80310/current/include/hal_platform_setup.h @@ -11,7 +11,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -253,12 +253,6 @@ mcr p15,0,r0,c7,c10,4 CPWAIT r0 - // Disable write buffer coalescing - mrc p15,0,r0,c1,c0,1 - orr r0,r0,#1 // set the disable bit - mcr p15,0,r0,c1,c0,1 - CPWAIT r0 - // Delay appx 60 ms to let battery-backup reset complete DELAY_FOR 0x400000, r0 // Eventually we will be able to check a register bit
--- a/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm +++ b/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm @@ -133,3 +133,7 @@ cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRA cdl_option CYGPKG_HAL_GDB_FILEIO { user_value 1 }; + +cdl_option CYGSEM_HAL_ARM_XSCALE_BTB { + user_value 0 +};
--- a/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm +++ b/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm @@ -92,3 +92,7 @@ cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRA cdl_option CYGPKG_HAL_GDB_FILEIO { user_value 1 }; + +cdl_option CYGSEM_HAL_ARM_XSCALE_BTB { + user_value 0 +};
--- a/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm +++ b/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm @@ -137,3 +137,7 @@ cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRA cdl_option CYGPKG_HAL_GDB_FILEIO { user_value 1 }; + +cdl_option CYGSEM_HAL_ARM_XSCALE_BTB { + user_value 0 +};
--- a/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm +++ b/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm @@ -100,3 +100,7 @@ cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRA cdl_option CYGPKG_HAL_GDB_FILEIO { user_value 1 }; + +cdl_option CYGSEM_HAL_ARM_XSCALE_BTB { + user_value 0 +};