Mercurial > flash_v2
annotate packages/hal/powerpc/arch/current/include/hal_intr.h @ 14:01ce82f3e11a ecos-sw-1999-06-11
Merge from eCos master repository on 1999-06-11-17:05:41-BST
| author | jlarmour |
|---|---|
| date | Fri, 11 Jun 1999 09:36:56 +0000 |
| parents | d3fbcdfa1b2f |
| children | 5f5102441818 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_INTR_H |
| 2 #define CYGONCE_HAL_INTR_H | |
| 3 | |
| 2 | 4 //========================================================================== |
| 0 | 5 // |
| 6 // hal_intr.h | |
| 7 // | |
| 8 // HAL Interrupt and clock support | |
| 9 // | |
| 2 | 10 //========================================================================== |
| 0 | 11 //####COPYRIGHTBEGIN#### |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 2 | 32 //========================================================================== |
| 0 | 33 //#####DESCRIPTIONBEGIN#### |
| 34 // | |
| 2 | 35 // Author(s): nickg |
| 36 // Contributors: nickg, jskov, | |
| 37 // jlarmour | |
| 38 // Date: 1999-02-19 | |
| 39 // Purpose: Define Interrupt support | |
| 40 // Description: The macros defined here provide the HAL APIs for handling | |
| 41 // interrupts and the clock. | |
| 0 | 42 // |
| 43 // Usage: | |
| 2 | 44 // #include <cyg/hal/hal_intr.h> |
| 45 // ... | |
| 0 | 46 // |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 2 | 50 //========================================================================== |
| 0 | 51 |
| 52 #include <pkgconf/hal.h> | |
| 53 | |
| 54 #include <cyg/infra/cyg_type.h> | |
| 55 | |
| 2 | 56 #include <cyg/hal/ppc_regs.h> // register definitions |
| 57 #include <cyg/hal/hal_io.h> // io macros | |
| 58 #include <cyg/infra/cyg_ass.h> // CYG_FAIL | |
| 59 | |
| 60 //-------------------------------------------------------------------------- | |
| 61 // PowerPC exception vectors. These correspond to VSRs and are the values | |
| 62 // to use for HAL_VSR_GET/SET | |
| 63 | |
| 64 #define CYGNUM_HAL_VECTOR_RESERVED_0 0 | |
| 65 #define CYGNUM_HAL_VECTOR_RESET 1 | |
| 66 #define CYGNUM_HAL_VECTOR_MACHINE_CHECK 2 | |
| 67 #define CYGNUM_HAL_VECTOR_DSI 3 | |
| 68 #define CYGNUM_HAL_VECTOR_ISI 4 | |
| 69 #define CYGNUM_HAL_VECTOR_INTERRUPT 5 | |
| 70 #define CYGNUM_HAL_VECTOR_ALIGNMENT 6 | |
| 71 #define CYGNUM_HAL_VECTOR_PROGRAM 7 | |
| 72 #define CYGNUM_HAL_VECTOR_FP_UNAVAILABLE 8 | |
| 73 #define CYGNUM_HAL_VECTOR_DECREMENTER 9 | |
| 74 #define CYGNUM_HAL_VECTOR_RESERVED_A 10 | |
| 75 #define CYGNUM_HAL_VECTOR_RESERVED_B 11 | |
| 76 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 12 | |
| 77 #define CYGNUM_HAL_VECTOR_TRACE 13 | |
| 78 #define CYGNUM_HAL_VECTOR_FP_ASSIST 14 | |
| 79 | |
| 80 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESERVED_0 | |
| 81 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST | |
| 82 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 ) | |
| 83 | |
| 84 // The decoded interrupts. | |
| 85 // Define decrementer as the first interrupt since it is guaranteed to | |
| 86 // be defined on all PowerPCs. External may expand into several interrupts | |
| 87 // depending on interrupt controller capabilities. | |
| 88 #define CYGNUM_HAL_INTERRUPT_DECREMENTER 0 | |
| 89 #define CYGNUM_HAL_INTERRUPT_EXTERNAL 1 | |
| 90 | |
| 91 // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S. | |
| 92 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER | |
| 93 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL | |
| 94 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 ) | |
| 95 | |
| 96 // Exception vectors. These are the values used when passed out to an | |
| 97 // external exception handler using cyg_hal_deliver_exception() | |
| 0 | 98 |
| 2 | 99 #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 |
| 100 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK | |
| 101 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI | |
| 102 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI | |
| 103 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ | |
| 104 CYGNUM_HAL_VECTOR_ALIGNMENT | |
| 105 #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE | |
| 106 #define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A | |
| 107 #define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B | |
| 108 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL | |
| 109 #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE | |
| 110 #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST | |
| 111 | |
| 112 // decoded exception vectors | |
| 113 #define CYGNUM_HAL_EXCEPTION_TRAP (-1) | |
| 114 #define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2) | |
| 115 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3) | |
| 116 #define CYGNUM_HAL_EXCEPTION_FPU (-4) | |
| 117 | |
| 118 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU | |
| 119 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_FP_ASSIST | |
| 120 #define CYGNUM_HAL_EXCEPTION_COUNT \ | |
| 121 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) | |
| 122 | |
| 123 | |
| 124 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 125 // Additional exceptions on the MPC8xx | |
| 126 #define CYGNUM_HAL_VECTOR_RESERVED_F 15 | |
| 127 #define CYGNUM_HAL_VECTOR_SW_EMUL 16 | |
| 128 #define CYGNUM_HAL_VECTOR_ITLB_MISS 17 | |
| 129 #define CYGNUM_HAL_VECTOR_DTLB_MISS 18 | |
| 130 #define CYGNUM_HAL_VECTOR_ITLB_ERROR 19 | |
| 131 #define CYGNUM_HAL_VECTOR_DTLB_ERROR 20 | |
| 132 #define CYGNUM_HAL_VECTOR_RESERVED_15 21 | |
| 133 #define CYGNUM_HAL_VECTOR_RESERVED_16 22 | |
| 134 #define CYGNUM_HAL_VECTOR_RESERVED_17 23 | |
| 135 #define CYGNUM_HAL_VECTOR_RESERVED_18 24 | |
| 136 #define CYGNUM_HAL_VECTOR_RESERVED_19 25 | |
| 137 #define CYGNUM_HAL_VECTOR_RESERVED_1A 26 | |
| 138 #define CYGNUM_HAL_VECTOR_RESERVED_1B 27 | |
| 139 #define CYGNUM_HAL_VECTOR_DATA_BP 28 | |
| 140 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29 | |
| 141 #define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30 | |
| 142 #define CYGNUM_HAL_VECTOR_NMI 31 | |
| 0 | 143 |
| 2 | 144 #define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F |
| 145 #define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL | |
| 146 #define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_ITLB_MISS | |
| 147 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_DTLB_MISS | |
| 148 #define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \ | |
| 149 CYGNUM_HAL_VECTOR_ITLB_ERROR | |
| 150 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \ | |
| 151 CYGNUM_HAL_VECTOR_DTLB_ERROR | |
| 152 #define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15 | |
| 153 #define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16 | |
| 154 #define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17 | |
| 155 #define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18 | |
| 156 #define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19 | |
| 157 #define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A | |
| 158 #define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B | |
| 159 #define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP | |
| 160 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP | |
| 161 #define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP | |
| 162 #define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI | |
| 163 | |
| 164 #undef CYGNUM_HAL_EXCEPTION_MAX | |
| 165 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI | |
| 166 | |
| 167 // The first level of external interrupts | |
| 168 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1 | |
| 169 #define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2 | |
| 170 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3 | |
| 171 #define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4 | |
| 172 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5 | |
| 173 #define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6 | |
| 174 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7 | |
| 175 #define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8 | |
| 176 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9 | |
| 177 #define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10 | |
| 178 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11 | |
| 179 #define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12 | |
| 180 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13 | |
| 181 #define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14 | |
| 182 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15 | |
| 183 #define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16 | |
| 184 | |
| 185 // Further decoded interrups | |
| 186 #define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 | |
| 187 #define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 | |
| 188 #define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 | |
| 189 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 | |
| 190 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 | |
| 191 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ 22 | |
| 192 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23 | |
| 193 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ 24 | |
| 194 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25 | |
| 195 #define CYGNUM_HAL_INTERRUPT_SIU_CPM 26 | |
| 196 | |
| 197 // Even further... | |
| 198 #define CYGNUM_HAL_INTERRUPT_CPM_PC15 27 | |
| 199 #define CYGNUM_HAL_INTERRUPT_CPM_SCC1 28 | |
| 200 #define CYGNUM_HAL_INTERRUPT_CPM_SCC2 29 | |
| 201 #define CYGNUM_HAL_INTERRUPT_CPM_SCC3 30 | |
| 202 #define CYGNUM_HAL_INTERRUPT_CPM_SCC4 31 | |
| 203 #define CYGNUM_HAL_INTERRUPT_CPM_PC14 32 | |
| 204 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER1 33 | |
| 205 #define CYGNUM_HAL_INTERRUPT_CPM_PC13 34 | |
| 206 #define CYGNUM_HAL_INTERRUPT_CPM_PC12 35 | |
| 207 #define CYGNUM_HAL_INTERRUPT_CPM_SDMA 36 | |
| 208 #define CYGNUM_HAL_INTERRUPT_CPM_IDMA1 37 | |
| 209 #define CYGNUM_HAL_INTERRUPT_CPM_IDMA2 38 | |
| 210 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13 39 | |
| 211 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER2 40 | |
| 212 #define CYGNUM_HAL_INTERRUPT_CPM_RISCTT 41 | |
| 213 #define CYGNUM_HAL_INTERRUPT_CPM_I2C 42 | |
| 214 #define CYGNUM_HAL_INTERRUPT_CPM_PC11 43 | |
| 215 #define CYGNUM_HAL_INTERRUPT_CPM_PC10 44 | |
| 216 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D 45 | |
| 217 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER3 46 | |
| 218 #define CYGNUM_HAL_INTERRUPT_CPM_PC9 47 | |
| 219 #define CYGNUM_HAL_INTERRUPT_CPM_PC8 48 | |
| 220 #define CYGNUM_HAL_INTERRUPT_CPM_PC7 49 | |
| 221 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08 50 | |
| 222 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER4 51 | |
| 223 #define CYGNUM_HAL_INTERRUPT_CPM_PC6 52 | |
| 224 #define CYGNUM_HAL_INTERRUPT_CPM_SPI 53 | |
| 225 #define CYGNUM_HAL_INTERRUPT_CPM_SMC1 54 | |
| 226 #define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP 55 | |
| 227 #define CYGNUM_HAL_INTERRUPT_CPM_PC5 56 | |
| 228 #define CYGNUM_HAL_INTERRUPT_CPM_PC4 57 | |
| 229 #define CYGNUM_HAL_INTERRUPT_CPM_ERROR 58 | |
| 230 | |
| 231 #define CYGNUM_HAL_INTERRUPT_CPM_FIRST CYGNUM_HAL_INTERRUPT_CPM_PC15 | |
| 232 #define CYGNUM_HAL_INTERRUPT_CPM_LAST CYGNUM_HAL_INTERRUPT_CPM_ERROR | |
| 233 | |
| 234 #undef CYGNUM_HAL_ISR_MAX | |
| 235 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CPM_LAST | |
| 0 | 236 #endif |
| 237 | |
| 2 | 238 // The vector used by the Real time clock |
| 239 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_DECREMENTER | |
| 0 | 240 |
| 2 | 241 //-------------------------------------------------------------------------- |
| 0 | 242 // Static data used by HAL |
| 243 | |
| 244 // ISR tables | |
| 2 | 245 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
| 246 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; | |
| 247 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; | |
| 248 // VSR table | |
| 249 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; | |
| 0 | 250 |
| 2 | 251 //-------------------------------------------------------------------------- |
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252 // Default ISRs |
| 0 | 253 |
| 254 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); | |
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255 externC cyg_uint32 hal_default_decrementer_isr(CYG_ADDRWORD vector, |
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256 CYG_ADDRWORD data); |
| 0 | 257 |
| 2 | 258 //-------------------------------------------------------------------------- |
| 0 | 259 // Interrupt state storage |
| 260 | |
| 261 typedef cyg_uint32 CYG_INTERRUPT_STATE; | |
| 262 | |
| 2 | 263 //-------------------------------------------------------------------------- |
| 0 | 264 // Interrupt control macros |
| 265 | |
| 266 #define HAL_DISABLE_INTERRUPTS(_old_) \ | |
| 267 asm volatile ( \ | |
| 268 "mfmsr %0;" \ | |
| 269 "lis 4,0;" \ | |
| 270 "ori 4,4,0x8000 ;" \ | |
| 271 "not 5,4;" \ | |
| 272 "and 5,%0,5;" \ | |
| 273 "mtmsr 5;" \ | |
| 274 "and %0,%0,4" \ | |
| 275 : "=r"(_old_) \ | |
| 276 : \ | |
| 277 : "r4", "r5" \ | |
| 278 ); | |
| 279 | |
| 280 #define HAL_ENABLE_INTERRUPTS() \ | |
| 281 asm volatile ( \ | |
| 282 "mfmsr 3;" \ | |
| 283 "lis 4,0;" \ | |
| 284 "ori 4,4,0x8000 ;" \ | |
| 285 "or 3,3,4;" \ | |
| 286 "mtmsr 3;" \ | |
| 287 : \ | |
| 288 : \ | |
| 289 : "r3", "r4" \ | |
| 290 ); | |
| 291 | |
| 292 #define HAL_RESTORE_INTERRUPTS(_old_) \ | |
| 293 asm volatile ( \ | |
| 294 "mfmsr 3;" \ | |
| 295 "lis 4,0;" \ | |
| 296 "ori 4,4,0x8000 ;" \ | |
| 297 "and 4,%0,4;" \ | |
| 298 "or 4,3,4;" \ | |
| 299 "mtmsr 4;" \ | |
| 300 : \ | |
| 301 : "r"(_old_) \ | |
| 302 : "r3", "r4" \ | |
| 303 ); | |
| 304 | |
| 305 // FIXME: using andi with side-effect on cc would be better but causes | |
| 306 // compiler problem. | |
| 307 #define HAL_QUERY_INTERRUPTS(_old_) \ | |
| 308 asm volatile ( \ | |
| 309 "mfmsr %0;" \ | |
| 310 "lis 4,0;" \ | |
| 311 "ori 4,4,0x8000;" \ | |
| 312 "and %0,%0,4;" \ | |
| 313 : "=r"(_old_) \ | |
| 314 : \ | |
| 315 : "r4" \ | |
| 316 ); | |
| 317 | |
| 2 | 318 //-------------------------------------------------------------------------- |
| 0 | 319 // Vector translation. |
| 2 | 320 |
| 321 #ifndef HAL_TRANSLATE_VECTOR | |
| 322 // Basic PowerPC configuration only has two vectors; decrementer and | |
| 323 // external. Isr tables/chaining use same vector decoder. | |
| 324 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ | |
| 325 (_index_) = (_vector_) | |
| 326 #endif | |
| 0 | 327 |
| 2 | 328 //-------------------------------------------------------------------------- |
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329 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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330 |
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331 externC void hal_interrupt_stack_call_pending_DSRs(void); |
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332 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ |
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333 hal_interrupt_stack_call_pending_DSRs() |
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334 |
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335 // these are offered solely for stack usage testing |
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336 // if they are not defined, then there is no interrupt stack. |
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337 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base |
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338 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack |
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339 // use them to declare these extern however you want: |
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340 // extern char HAL_INTERRUPT_STACK_BASE[]; |
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341 // extern char HAL_INTERRUPT_STACK_TOP[]; |
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342 // is recommended |
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343 #endif |
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344 |
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345 //-------------------------------------------------------------------------- |
| 2 | 346 // Interrupt and VSR attachment macros |
| 0 | 347 |
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348 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
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349 CYG_MACRO_START \ |
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350 cyg_uint32 _index_; \ |
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351 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
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352 \ |
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353 if((hal_interrupt_handlers[_index_] \ |
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354 == (CYG_ADDRESS)hal_default_decrementer_isr) \ |
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355 || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \ |
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356 (_state_) = 0; \ |
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357 else \ |
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358 (_state_) = 1; \ |
| 2 | 359 CYG_MACRO_END |
| 0 | 360 |
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361 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ |
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362 CYG_MACRO_START \ |
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363 cyg_uint32 _index_; \ |
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364 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
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365 \ |
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366 if((hal_interrupt_handlers[_index_] \ |
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367 == (CYG_ADDRESS)hal_default_decrementer_isr) \ |
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368 || (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \ |
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369 { \ |
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370 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ |
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371 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \ |
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372 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ |
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373 } \ |
| 0 | 374 CYG_MACRO_END |
| 375 | |
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376 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ |
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377 CYG_MACRO_START \ |
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378 cyg_uint32 _index_; \ |
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379 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
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380 \ |
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381 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ |
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382 { \ |
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383 if (CYGNUM_HAL_INTERRUPT_DECREMENTER == (_vector_)) \ |
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384 hal_interrupt_handlers[_index_] = \ |
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385 (CYG_ADDRESS)hal_default_decrementer_isr; \ |
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386 else \ |
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387 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ |
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388 hal_interrupt_data[_index_] = 0; \ |
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389 hal_interrupt_objects[_index_] = 0; \ |
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390 } \ |
| 0 | 391 CYG_MACRO_END |
| 392 | |
| 393 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ | |
| 394 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_]; | |
| 395 | |
| 396 | |
| 397 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ | |
| 398 CYG_MACRO_START \ | |
| 399 if( _poldvsr_ != NULL ) \ | |
| 400 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ | |
| 401 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ | |
| 402 CYG_MACRO_END | |
| 403 | |
| 2 | 404 //-------------------------------------------------------------------------- |
| 0 | 405 // Interrupt controller access |
| 406 | |
| 2 | 407 #ifdef CYG_HAL_POWERPC_MPC860 |
| 408 | |
| 409 // FIXME: Should probably be put in a separate .inl file?!? | |
| 410 | |
| 411 static __inline__ void | |
| 412 cyg_hal_interrupt_mask ( cyg_uint32 vector ) | |
| 413 { | |
| 414 switch (vector) { | |
| 415 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: | |
| 416 { | |
| 417 // SIU interrupt vectors | |
| 418 cyg_uint32 simask; | |
| 419 | |
| 420 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); | |
| 421 simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) | |
| 422 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); | |
| 423 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); | |
| 424 break; | |
| 425 } | |
| 426 case CYGNUM_HAL_INTERRUPT_SIU_TB_A: | |
| 427 { | |
| 428 // TimeBase A interrupt | |
| 429 cyg_uint16 tbscr; | |
| 430 | |
| 431 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 432 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE); | |
| 433 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 434 break; | |
| 435 } | |
| 436 case CYGNUM_HAL_INTERRUPT_SIU_TB_B: | |
| 437 { | |
| 438 // TimeBase B interrupt | |
| 439 cyg_uint16 tbscr; | |
| 440 | |
| 441 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 442 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE); | |
| 443 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 444 break; | |
| 445 } | |
| 446 case CYGNUM_HAL_INTERRUPT_SIU_PIT: | |
| 447 { | |
| 448 // Periodic Interrupt | |
| 449 cyg_uint16 piscr; | |
| 450 | |
| 451 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 452 piscr &= ~(CYGARC_REG_IMM_PISCR_PIE); | |
| 453 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 454 break; | |
| 455 } | |
| 456 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: | |
| 457 { | |
| 458 // Real Time Clock Second | |
| 459 cyg_uint16 rtcsc; | |
| 460 | |
| 461 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 462 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE); | |
| 463 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 464 break; | |
| 465 } | |
| 466 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: | |
| 467 { | |
| 468 // Real Time Clock Alarm | |
| 469 cyg_uint16 rtcsc; | |
| 470 | |
| 471 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 472 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE); | |
| 473 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 474 break; | |
| 475 } | |
| 476 // PCMCIA_A_IRQ | |
| 477 // PCMCIA_A_CHLVL | |
| 478 // PCMCIA_B_IRQ | |
| 479 // PCMCIA_B_CHLVL | |
| 480 case CYGNUM_HAL_INTERRUPT_SIU_CPM: | |
| 481 { | |
| 482 // Communications Processor Module | |
| 483 cyg_uint16 cicr; | |
| 484 | |
| 485 HAL_READ_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 486 cicr &= ~(CYGARC_REG_IMM_CICR_IEN); | |
| 487 HAL_WRITE_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 488 break; | |
| 489 } | |
| 490 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: | |
| 491 { | |
| 492 // CPM interrupts | |
| 493 cyg_uint32 cimr; | |
| 494 | |
| 495 HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); | |
| 496 cimr &= ~(((cyg_uint32) 0x80000000) | |
| 497 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); | |
| 498 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); | |
| 499 break; | |
| 500 } | |
| 501 default: | |
| 502 CYG_FAIL("Unknown Interrupt!!!"); | |
| 503 break; | |
| 504 } | |
| 505 } | |
| 506 | |
| 507 static __inline__ void | |
| 508 cyg_hal_interrupt_unmask ( cyg_uint32 vector ) | |
| 509 { | |
| 510 switch (vector) { | |
| 511 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: | |
| 512 { | |
| 513 // SIU interrupt vectors | |
| 514 cyg_uint32 simask; | |
| 515 | |
| 516 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask); | |
| 517 simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0) | |
| 518 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); | |
| 519 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask); | |
| 520 break; | |
| 521 } | |
| 522 case CYGNUM_HAL_INTERRUPT_SIU_TB_A: | |
| 523 { | |
| 524 // TimeBase A interrupt | |
| 525 cyg_uint16 tbscr; | |
| 526 | |
| 527 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 528 tbscr |= CYGARC_REG_IMM_TBSCR_REFAE; | |
| 529 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 530 break; | |
| 531 } | |
| 532 case CYGNUM_HAL_INTERRUPT_SIU_TB_B: | |
| 533 { | |
| 534 // TimeBase B interrupt | |
| 535 cyg_uint16 tbscr; | |
| 536 | |
| 537 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 538 tbscr |= CYGARC_REG_IMM_TBSCR_REFBE; | |
| 539 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 540 break; | |
| 541 } | |
| 542 case CYGNUM_HAL_INTERRUPT_SIU_PIT: | |
| 543 { | |
| 544 // Periodic Interrupt | |
| 545 cyg_uint16 piscr; | |
| 546 | |
| 547 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 548 piscr |= CYGARC_REG_IMM_PISCR_PIE; | |
| 549 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 550 break; | |
| 551 } | |
| 552 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: | |
| 553 { | |
| 554 // Real Time Clock Second | |
| 555 cyg_uint16 rtcsc; | |
| 556 | |
| 557 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 558 rtcsc |= CYGARC_REG_IMM_RTCSC_SIE; | |
| 559 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 560 break; | |
| 561 } | |
| 562 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: | |
| 563 { | |
| 564 // Real Time Clock Alarm | |
| 565 cyg_uint16 rtcsc; | |
| 566 | |
| 567 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 568 rtcsc |= CYGARC_REG_IMM_RTCSC_ALE; | |
| 569 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 570 break; | |
| 571 } | |
| 572 // PCMCIA_A_IRQ | |
| 573 // PCMCIA_A_CHLVL | |
| 574 // PCMCIA_B_IRQ | |
| 575 // PCMCIA_B_CHLVL | |
| 576 case CYGNUM_HAL_INTERRUPT_SIU_CPM: | |
| 577 { | |
| 578 // Communications Processor Module | |
| 579 cyg_uint16 cicr; | |
| 580 | |
| 581 HAL_READ_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 582 cicr |= CYGARC_REG_IMM_CICR_IEN; | |
| 583 HAL_WRITE_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 584 break; | |
| 585 } | |
| 586 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: | |
| 587 { | |
| 588 // CPM interrupts | |
| 589 cyg_uint32 cimr; | |
| 590 | |
| 591 HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr); | |
| 592 cimr |= (((cyg_uint32) 0x80000000) | |
| 593 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); | |
| 594 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr); | |
| 595 break; | |
| 596 } | |
| 597 default: | |
| 598 CYG_FAIL("Unknown Interrupt!!!"); | |
| 599 break; | |
| 600 } | |
| 601 } | |
| 602 | |
| 603 static __inline__ void | |
| 604 cyg_hal_interrupt_acknowledge ( cyg_uint32 vector ) | |
| 605 { | |
| 606 switch (vector) { | |
| 607 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: | |
| 608 { | |
| 609 // SIU interrupt vectors | |
| 610 cyg_uint32 sipend; | |
| 611 | |
| 612 // When IRQx is configured as an edge interrupt it needs to be | |
| 613 // cleared. Write to INTx and IRQ/level bits are ignore so | |
| 614 // it's safe to do always. | |
| 615 HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); | |
| 616 sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0) | |
| 617 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); | |
| 618 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend); | |
| 619 break; | |
| 620 } | |
| 621 case CYGNUM_HAL_INTERRUPT_SIU_TB_A: | |
| 622 { | |
| 623 // TimeBase A interrupt | |
| 624 cyg_uint16 tbscr; | |
| 625 | |
| 626 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 627 tbscr |= CYGARC_REG_IMM_TBSCR_REFA; | |
| 628 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 629 break; | |
| 630 } | |
| 631 case CYGNUM_HAL_INTERRUPT_SIU_TB_B: | |
| 632 { | |
| 633 // TimeBase B interrupt | |
| 634 cyg_uint16 tbscr; | |
| 635 | |
| 636 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 637 tbscr |= CYGARC_REG_IMM_TBSCR_REFB; | |
| 638 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 639 break; | |
| 640 } | |
| 641 case CYGNUM_HAL_INTERRUPT_SIU_PIT: | |
| 642 { | |
| 643 // Periodic Interrupt | |
| 644 cyg_uint16 piscr; | |
| 645 | |
| 646 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 647 piscr |= CYGARC_REG_IMM_PISCR_PS; | |
| 648 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 649 break; | |
| 650 } | |
| 651 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: | |
| 652 { | |
| 653 // Real Time Clock Second | |
| 654 cyg_uint16 rtcsc; | |
| 655 | |
| 656 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 657 rtcsc |= CYGARC_REG_IMM_RTCSC_SEC; | |
| 658 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 659 break; | |
| 660 } | |
| 661 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: | |
| 662 { | |
| 663 // Real Time Clock Alarm | |
| 664 cyg_uint16 rtcsc; | |
| 665 | |
| 666 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 667 rtcsc |= CYGARC_REG_IMM_RTCSC_ALR; | |
| 668 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 669 break; | |
| 670 } | |
| 671 // PCMCIA_A_IRQ | |
| 672 // PCMCIA_A_CHLVL | |
| 673 // PCMCIA_B_IRQ | |
| 674 // PCMCIA_B_CHLVL | |
| 675 case CYGNUM_HAL_INTERRUPT_SIU_CPM: | |
| 676 // Communications Processor Module | |
| 677 // The CPM interrupts must be acknowledged individually. | |
| 678 break; | |
| 679 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: | |
| 680 { | |
| 681 // CPM interrupts | |
| 682 cyg_uint32 cisr; | |
| 683 | |
| 684 HAL_READ_UINT32 (CYGARC_REG_IMM_CISR, cisr); | |
| 685 cisr |= (((cyg_uint32) 0x80000000) | |
| 686 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST)); | |
| 687 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CISR, cisr); | |
| 688 break; | |
| 689 } | |
| 690 default: | |
| 691 CYG_FAIL("Unknown Interrupt!!!"); | |
| 692 break; | |
| 693 } | |
| 694 } | |
| 695 | |
| 696 static __inline__ void | |
| 697 cyg_hal_interrupt_configure ( cyg_uint32 vector, | |
| 698 cyg_bool level, | |
| 699 cyg_bool up ) | |
| 700 { | |
| 701 switch (vector) { | |
| 702 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0: | |
| 703 case CYGNUM_HAL_INTERRUPT_SIU_IRQ1: | |
| 704 case CYGNUM_HAL_INTERRUPT_SIU_IRQ2: | |
| 705 case CYGNUM_HAL_INTERRUPT_SIU_IRQ3: | |
| 706 case CYGNUM_HAL_INTERRUPT_SIU_IRQ4: | |
| 707 case CYGNUM_HAL_INTERRUPT_SIU_IRQ5: | |
| 708 case CYGNUM_HAL_INTERRUPT_SIU_IRQ6: | |
| 709 case CYGNUM_HAL_INTERRUPT_SIU_IRQ7: | |
| 710 { | |
| 711 // External interrupts | |
| 712 cyg_uint32 siel, bit; | |
| 713 | |
| 714 CYG_ASSERT( level || !up, "Only falling edge is supported"); | |
| 715 | |
| 716 bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_IRQ0) | |
| 717 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0)); | |
| 718 | |
| 719 HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel); | |
| 720 siel &= ~bit; | |
| 721 if (!level) { | |
| 722 // Set edge detect bit. | |
| 723 siel |= bit; | |
| 724 } | |
| 725 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel); | |
| 726 break; | |
| 727 } | |
| 728 case CYGNUM_HAL_INTERRUPT_SIU_LVL0: | |
| 729 case CYGNUM_HAL_INTERRUPT_SIU_LVL1: | |
| 730 case CYGNUM_HAL_INTERRUPT_SIU_LVL2: | |
| 731 case CYGNUM_HAL_INTERRUPT_SIU_LVL3: | |
| 732 case CYGNUM_HAL_INTERRUPT_SIU_LVL4: | |
| 733 case CYGNUM_HAL_INTERRUPT_SIU_LVL5: | |
| 734 case CYGNUM_HAL_INTERRUPT_SIU_LVL6: | |
| 735 case CYGNUM_HAL_INTERRUPT_SIU_LVL7: | |
| 736 case CYGNUM_HAL_INTERRUPT_SIU_TB_A: | |
| 737 case CYGNUM_HAL_INTERRUPT_SIU_TB_B: | |
| 738 case CYGNUM_HAL_INTERRUPT_SIU_PIT: | |
| 739 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: | |
| 740 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: | |
| 741 // PCMCIA_A_IRQ | |
| 742 // PCMCIA_A_CHLVL | |
| 743 // PCMCIA_B_IRQ | |
| 744 // PCMCIA_B_CHLVL | |
| 745 case CYGNUM_HAL_INTERRUPT_SIU_CPM: | |
| 746 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: | |
| 747 // These cannot be configured. | |
| 748 break; | |
| 749 | |
| 750 default: | |
| 751 CYG_FAIL("Unknown Interrupt!!!"); | |
| 752 break; | |
| 753 } | |
| 754 } | |
| 755 | |
| 756 static __inline__ void | |
| 757 cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level ) | |
| 758 { | |
| 759 // Note: highest priority has the lowest numerical value. | |
| 760 CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority"); | |
| 761 CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority"); | |
| 762 | |
| 763 switch (vector) { | |
| 764 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7: | |
| 765 // These cannot be configured. | |
| 766 break; | |
| 767 case CYGNUM_HAL_INTERRUPT_SIU_TB_A: | |
| 768 case CYGNUM_HAL_INTERRUPT_SIU_TB_B: | |
| 769 { | |
| 770 // TimeBase A+B interrupt | |
| 771 cyg_uint16 tbscr; | |
| 772 | |
| 773 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 774 tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK); | |
| 775 tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level; | |
| 776 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr); | |
| 777 break; | |
| 778 } | |
| 779 case CYGNUM_HAL_INTERRUPT_SIU_PIT: | |
| 780 { | |
| 781 // Periodic Interrupt | |
| 782 cyg_uint16 piscr; | |
| 783 | |
| 784 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 785 piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK); | |
| 786 piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level; | |
| 787 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr); | |
| 788 break; | |
| 789 } | |
| 790 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC: | |
| 791 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR: | |
| 792 { | |
| 793 // Real Time Clock Second & Real Time Clock Alarm | |
| 794 cyg_uint16 rtcsc; | |
| 795 | |
| 796 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 797 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK); | |
| 798 rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level; | |
| 799 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc); | |
| 800 break; | |
| 801 } | |
| 802 // PCMCIA_A_IRQ | |
| 803 // PCMCIA_A_CHLVL | |
| 804 // PCMCIA_B_IRQ | |
| 805 // PCMCIA_B_CHLVL | |
| 806 case CYGNUM_HAL_INTERRUPT_SIU_CPM: | |
| 807 { | |
| 808 // Communications Processor Module | |
| 809 cyg_uint16 cicr; | |
| 810 | |
| 811 HAL_READ_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 812 cicr &= ~(CYGARC_REG_IMM_CICR_IRQMASK); | |
| 813 cicr |= level << CYGARC_REG_IMM_CICR_IRQ_SHIFT; | |
| 814 HAL_WRITE_UINT16 (CYGARC_REG_IMM_CICR, cicr); | |
| 815 break; | |
| 816 } | |
| 817 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST: | |
| 818 // CPM interrupt levels are for internal priority. All interrupts | |
| 819 // fed to the CPU use the CPM level set above. | |
| 820 // FIXME: Control of SCdP ordering. | |
| 821 break; | |
| 822 default: | |
| 823 CYG_FAIL("Unknown Interrupt!!!"); | |
| 824 break; | |
| 825 } | |
| 826 } | |
| 827 | |
| 828 // The decrementer interrupt cannnot be masked, configured or acknowledged. | |
| 829 | |
| 830 #define HAL_INTERRUPT_MASK( _vector_ ) \ | |
| 831 CYG_MACRO_START \ | |
| 832 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ | |
| 833 cyg_hal_interrupt_mask ( (_vector_) ); \ | |
| 834 CYG_MACRO_END | |
| 835 | |
| 836 #define HAL_INTERRUPT_UNMASK( _vector_ ) \ | |
| 837 CYG_MACRO_START \ | |
| 838 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ | |
| 839 cyg_hal_interrupt_unmask ( (_vector_) ); \ | |
| 840 CYG_MACRO_END | |
| 841 | |
| 842 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ | |
| 843 CYG_MACRO_START \ | |
| 844 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ | |
| 845 cyg_hal_interrupt_acknowledge ( (_vector_) ); \ | |
| 846 CYG_MACRO_END | |
| 847 | |
| 848 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ | |
| 849 CYG_MACRO_START \ | |
| 850 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ | |
| 851 cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \ | |
| 852 CYG_MACRO_END | |
| 853 | |
| 854 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ | |
| 855 CYG_MACRO_START \ | |
| 856 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ | |
| 857 cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \ | |
| 858 CYG_MACRO_END | |
| 859 | |
| 860 #else | |
| 861 | |
| 862 // No interrupt configuration possible without interrupt controller. | |
| 0 | 863 |
| 864 #define HAL_INTERRUPT_MASK( _vector_ ) | |
| 865 | |
| 866 #define HAL_INTERRUPT_UNMASK( _vector_ ) | |
| 867 | |
| 868 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) | |
| 869 | |
| 870 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) | |
| 871 | |
| 872 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) | |
| 873 | |
| 2 | 874 #endif |
| 875 | |
| 876 //-------------------------------------------------------------------------- | |
| 877 // Interrupt arbiters | |
| 878 | |
| 879 #ifdef CYG_HAL_POWERPC_MPC860 | |
| 880 | |
| 881 externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, | |
| 882 CYG_ADDRWORD data); | |
| 883 externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector, | |
| 884 CYG_ADDRWORD data); | |
| 885 externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector, | |
| 886 CYG_ADDRWORD data); | |
| 887 externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, | |
| 888 CYG_ADDRWORD data); | |
| 889 | |
| 890 #endif // ifdef CYG_HAL_POWERPC_MPC860 | |
| 891 | |
| 892 //-------------------------------------------------------------------------- | |
| 0 | 893 // Clock control |
| 894 | |
| 895 #define HAL_CLOCK_INITIALIZE( _period_ ) \ | |
| 896 asm volatile ( \ | |
| 897 "mtdec %0;" \ | |
| 898 : \ | |
| 2 | 899 : "r"(_period_) \ |
| 900 ); | |
| 0 | 901 |
| 902 #define HAL_CLOCK_RESET( _vector_, _period_ ) \ | |
| 903 asm volatile ( \ | |
| 904 "mtdec %0;" \ | |
| 905 : \ | |
| 2 | 906 : "r"(_period_) \ |
| 907 ); | |
| 0 | 908 |
| 909 #define HAL_CLOCK_READ( _pvalue_ ) \ | |
| 910 CYG_MACRO_START \ | |
| 911 register cyg_uint32 result; \ | |
| 912 asm volatile( \ | |
| 913 "mfdec %0;" \ | |
| 914 : "=r"(result) \ | |
| 915 ); \ | |
| 916 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-result; \ | |
| 917 CYG_MACRO_END | |
| 918 | |
| 2 | 919 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY |
| 920 #define HAL_CLOCK_LATENCY( _pvalue_ ) \ | |
| 921 CYG_MACRO_START \ | |
| 922 register cyg_int32 result; \ | |
| 923 asm volatile( \ | |
| 924 "mfdec %0;" \ | |
| 925 : "=r"(result) \ | |
| 926 ); \ | |
| 927 /* Pending DEC interrupts cannot be discarded. If dec is */ \ | |
| 928 /* positive it''s because a DEC interrupt occured while */ \ | |
| 929 /* eCos was getting ready to run. Just return 0 in that */ \ | |
| 930 /* case. */ \ | |
| 931 if (result > 0) \ | |
| 932 result = 0; \ | |
| 933 *(_pvalue_) = -result; \ | |
| 934 CYG_MACRO_END | |
| 935 #endif | |
| 936 | |
| 937 //-------------------------------------------------------------------------- | |
| 0 | 938 #endif // ifndef CYGONCE_HAL_INTR_H |
| 939 // End of hal_intr.h |