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annotate packages/hal/sh/arch/current/src/hal_misc.c @ 128:0c2b7be0d798 ecos-sw-2000-10-12

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Merge from eCos master repository on 2000-10-12-08:46:24-BST
author jlarmour
date Thu, 12 Oct 2000 20:31:43 +0000
parents 518f42066aba
children eb9fd8c04db3
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1 //==========================================================================
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2 //
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3 // hal_misc.c
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4 //
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5 // HAL miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors: jskov, jlarmour, nickg
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36 // Date: 1999-04-03
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37 // Purpose: HAL miscellaneous functions
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38 // Description: This file contains miscellaneous functions provided by the
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39 // HAL.
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //===========================================================================
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44
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45 #include <pkgconf/hal.h>
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46
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47 #include <cyg/infra/cyg_type.h>
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48 #include <cyg/infra/cyg_trac.h> // tracing macros
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49 #include <cyg/infra/cyg_ass.h> // assertion macros
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50 #include <cyg/infra/diag.h> // diag_printf
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51
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52 #include <cyg/hal/hal_arch.h> // HAL header
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53 #include <cyg/hal/hal_cache.h> // HAL cache
112
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54 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) || \
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55 defined(CYGPKG_HAL_EXCEPTIONS)
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56 # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions
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57 #endif
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58
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59 //---------------------------------------------------------------------------
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60 // Functions used during initialization.
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61
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62 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
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63 cyg_bool cyg_hal_stop_constructors;
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64 #endif
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65
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66 typedef void (*pfunc) (void);
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67 extern pfunc __CTOR_LIST__[];
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68 extern pfunc __CTOR_END__[];
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69
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70 void
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71 cyg_hal_invoke_constructors (void)
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72 {
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73 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
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74 static pfunc *p = &__CTOR_END__[-1];
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75
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76 cyg_hal_stop_constructors = 0;
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77 for (; p >= __CTOR_LIST__; p--) {
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78 (*p) ();
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79 if (cyg_hal_stop_constructors) {
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80 p--;
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81 break;
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82 }
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83 }
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84 #else
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85 pfunc *p;
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86
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87 for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
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88 (*p) ();
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89 #endif
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90 }
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91
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92 //---------------------------------------------------------------------------
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93 // First level C exception handler.
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94
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95 externC void __handle_exception (void);
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96
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97 externC HAL_SavedRegisters *_hal_registers;
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98 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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99 externC volatile void *__mem_fault_handler;
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100 #endif
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101
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102 void
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103 cyg_hal_exception_handler(HAL_SavedRegisters *regs)
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104 {
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105 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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106 if (__mem_fault_handler &&
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107 ((regs->event >= CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS) &&
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108 (regs->event <= CYGNUM_HAL_EXCEPTION_DATA_WRITE))) {
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109 regs->pc = (unsigned long)__mem_fault_handler;
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110 return; // Caught an exception inside stubs
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111 }
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112
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113 // Set the pointer to the registers of the current exception
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114 // context. At entry the GDB stub will expand the
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115 // HAL_SavedRegisters structure into a (bigger) register array.
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116 _hal_registers = regs;
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117
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118 __handle_exception();
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119
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120 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
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121 defined(CYGPKG_HAL_EXCEPTIONS)
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122
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123 cyg_hal_deliver_exception( regs->event, (CYG_ADDRWORD)regs );
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124
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125 #else
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126
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127 CYG_FAIL("Exception!!!");
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128
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129 #endif
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130
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131 return;
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132 }
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133
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134 //---------------------------------------------------------------------------
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135 // Default ISR
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136 externC cyg_uint32
105
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137 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
76
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138 {
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139 return 0;
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140 }
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141
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142 //--------------------------------------------------------------------------
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143 // Determine the index of the ls bit of the supplied mask.
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144
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145 cyg_uint32
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146 hal_lsbit_index(cyg_uint32 mask)
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147 {
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148 cyg_uint32 n = mask;
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149
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150 static const signed char tab[64] =
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151 { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10,
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152 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11,
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153 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0,
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154 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0
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155 };
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156
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157 n &= ~(n-1UL);
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158 n = (n<<16)-n;
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159 n = (n<<6)+n;
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160 n = (n<<4)+n;
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161
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162 return tab[n>>26];
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163 }
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164
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165 //--------------------------------------------------------------------------
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166 // Determine the index of the ms bit of the supplied mask.
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167
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168 cyg_uint32
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169 hal_msbit_index(cyg_uint32 mask)
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170 {
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171 cyg_uint32 x = mask;
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172 cyg_uint32 w;
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173
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174 // Phase 1: make word with all ones from that one to the right
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175 x |= x >> 16;
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176 x |= x >> 8;
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177 x |= x >> 4;
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178 x |= x >> 2;
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179 x |= x >> 1;
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180
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181 // Phase 2: calculate number of "1" bits in the word
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182 w = (x & 0x55555555) + ((x >> 1) & 0x55555555);
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183 w = (w & 0x33333333) + ((w >> 2) & 0x33333333);
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184 w = w + (w >> 4);
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185 w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F);
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186 return (cyg_uint32)((w + (w >> 16)) & 0xFF);
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187
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188 }
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189
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190 //---------------------------------------------------------------------------
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191 // Idle thread action
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192
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193 void
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194 hal_idle_thread_action( cyg_uint32 count )
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195 {
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196 }
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197
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198 //---------------------------------------------------------------------------
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199 // Initial cache enabling
128
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200
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201 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK
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202 # define CACHE_MODE_P0 0
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203 #else
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204 # define CACHE_MODE_P0 CYGARC_REG_CCR_WT
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205 #endif
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206
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207 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK
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208 # define CACHE_MODE_P1 CYGARC_REG_CCR_CB
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209 #else
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210 # define CACHE_MODE_P1 0
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211 #endif
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212
76
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213 externC void
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214 cyg_hal_enable_caches(void)
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215 {
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216 // Initialize cache.
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217 HAL_UCACHE_INVALIDATE_ALL();
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218
128
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219 // Set cache modes
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220 HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1);
76
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221
128
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222 #ifdef CYGHWR_HAL_SH_CACHE_ENABLE
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223 // Enable cache.
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224 HAL_UCACHE_ENABLE();
128
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225 #endif
76
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226 }
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227
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228 //---------------------------------------------------------------------------
105
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229 // SH3 variant stuff
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230 // This should be split out...
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231 void
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232 hal_variant_init(void)
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233 {
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234 }
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235
112
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236 // Low-level delay (in microseconds)
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237
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238 void
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239 hal_delay_us(int usecs)
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240 {
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241 unsigned char _tstr; // Current clock control
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242 volatile unsigned char *tstr = (volatile unsigned char *)CYGARC_REG_TSTR;
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243 volatile unsigned long *tcnt = (volatile unsigned long *)CYGARC_REG_TCNT1;
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244 volatile unsigned long *tcor = (volatile unsigned long *)CYGARC_REG_TCOR1;
128
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245 unsigned long clocks_per_us = (CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED+(CYGHWR_HAL_SH_TMU_PRESCALE_0-1))/CYGHWR_HAL_SH_TMU_PRESCALE_0; // Rounded up
112
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246 int diff, diff2;
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247 cyg_uint32 val1, val2;
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248
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249 _tstr = *tstr;
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250 *tstr |= CYGARC_REG_TSTR_STR1; // Enable channel 1
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251 while (usecs-- > 0) {
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252 diff = 0;
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253 while (diff < clocks_per_us) {
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254 val1 = *tcnt;
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255 while ((val2 = *tcnt) == val1) ;
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256 diff2 = val2 - val1;
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257 if (diff2 < 0) diff2 += *tcor;
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258 diff += diff2;
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259 }
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260 }
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261 *tstr = _tstr; // Restore timer to previous state
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262 }
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263
105
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diff changeset
264 //---------------------------------------------------------------------------
126
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diff changeset
265 // Interrupt function support
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266
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diff changeset
267 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
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268 externC cyg_uint8 cyg_hal_ILVL_table[];
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diff changeset
269 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \
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270 /* Update the ILVL table, so it is easy for the interrupt entry */ \
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diff changeset
271 /* code to find out the level of a given interrupt source. */ \
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diff changeset
272 cyg_hal_ILVL_table[(_vector_)] = (_level_)
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diff changeset
273 #else
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274 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_)
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diff changeset
275 #endif
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276
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diff changeset
277 void
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278 hal_interrupt_set_level(int vector, int level)
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diff changeset
279 {
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diff changeset
280 cyg_uint16 iprX;
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diff changeset
281
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282 CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
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diff changeset
283 CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
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diff changeset
284 && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");
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diff changeset
285
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diff changeset
286 HAL_UPDATE_ILVL_TABLE(vector, level);
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diff changeset
287
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diff changeset
288 switch( (vector) ) {
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diff changeset
289 case CYGNUM_HAL_INTERRUPT_NMI:
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diff changeset
290 /* fall through */
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diff changeset
291 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
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diff changeset
292 /* Cannot change levels */
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diff changeset
293 break;
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diff changeset
294
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diff changeset
295 /* IPRA */
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diff changeset
296 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0:
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297 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
298 iprX &= ~CYGARC_REG_IPRA_TMU0_MASK;
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diff changeset
299 iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1;
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diff changeset
300 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
301 break;
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diff changeset
302 case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1:
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diff changeset
303 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
304 iprX &= ~CYGARC_REG_IPRA_TMU1_MASK;
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diff changeset
305 iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1;
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diff changeset
306 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
307 break;
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diff changeset
308 case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2:
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diff changeset
309 case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2:
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diff changeset
310 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
311 iprX &= ~CYGARC_REG_IPRA_TMU2_MASK;
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diff changeset
312 iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1;
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diff changeset
313 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
314 break;
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diff changeset
315 case CYGNUM_HAL_INTERRUPT_RTC_ATI:
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diff changeset
316 case CYGNUM_HAL_INTERRUPT_RTC_PRI:
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diff changeset
317 case CYGNUM_HAL_INTERRUPT_RTC_CUI:
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diff changeset
318 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
319 iprX &= ~CYGARC_REG_IPRA_RTC_MASK;
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diff changeset
320 iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1;
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diff changeset
321 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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diff changeset
322 break;
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diff changeset
323
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diff changeset
324 /* IPRB */
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diff changeset
325 case CYGNUM_HAL_INTERRUPT_SCI_ERI:
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diff changeset
326 case CYGNUM_HAL_INTERRUPT_SCI_RXI:
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diff changeset
327 case CYGNUM_HAL_INTERRUPT_SCI_TXI:
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diff changeset
328 case CYGNUM_HAL_INTERRUPT_SCI_TEI:
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diff changeset
329 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
330 iprX &= ~CYGARC_REG_IPRB_SCI_MASK;
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diff changeset
331 iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1;
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diff changeset
332 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
333 break;
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diff changeset
334 case CYGNUM_HAL_INTERRUPT_WDT_ITI:
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diff changeset
335 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
336 iprX &= ~CYGARC_REG_IPRB_WDT_MASK;
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diff changeset
337 iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1;
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diff changeset
338 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
339 break;
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diff changeset
340 case CYGNUM_HAL_INTERRUPT_REF_RCMI:
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diff changeset
341 case CYGNUM_HAL_INTERRUPT_REF_ROVI:
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diff changeset
342 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
343 iprX &= ~CYGARC_REG_IPRB_REF_MASK;
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diff changeset
344 iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1;
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diff changeset
345 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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diff changeset
346 break;
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347
128
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diff changeset
348 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
126
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diff changeset
349 /* IPRC */
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diff changeset
350 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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diff changeset
351 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
352 iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
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diff changeset
353 iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
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diff changeset
354 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
355 break;
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diff changeset
356 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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diff changeset
357 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
358 iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
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diff changeset
359 iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
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diff changeset
360 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
361 break;
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diff changeset
362 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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diff changeset
363 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
364 iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
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diff changeset
365 iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
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diff changeset
366 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
367 break;
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diff changeset
368 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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diff changeset
369 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
370 iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
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diff changeset
371 iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
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diff changeset
372 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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diff changeset
373 break;
128
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diff changeset
374 #endif
126
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diff changeset
375 /* IPRD */
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diff changeset
376 case CYGNUM_HAL_INTERRUPT_PINT_PINT07:
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diff changeset
377 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
378 iprX &= ~CYGARC_REG_IPRD_PINT07_MASK;
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diff changeset
379 iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1;
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diff changeset
380 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
381 break;
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diff changeset
382 case CYGNUM_HAL_INTERRUPT_PINT_PINT8F:
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diff changeset
383 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
384 iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK;
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diff changeset
385 iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1;
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diff changeset
386 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
387 break;
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diff changeset
388 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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diff changeset
389 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
390 iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK;
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diff changeset
391 iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1;
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diff changeset
392 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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diff changeset
393 break;
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diff changeset
394 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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diff changeset
395 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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parents: 112
diff changeset
396 iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK;
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jlarmour
parents: 112
diff changeset
397 iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1;
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jlarmour
parents: 112
diff changeset
398 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents: 112
diff changeset
399 break;
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jlarmour
parents: 112
diff changeset
400
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jlarmour
parents: 112
diff changeset
401 /* IPRE */
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jlarmour
parents: 112
diff changeset
402 case CYGNUM_HAL_INTERRUPT_DMAC_DEI0:
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jlarmour
parents: 112
diff changeset
403 case CYGNUM_HAL_INTERRUPT_DMAC_DEI1:
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jlarmour
parents: 112
diff changeset
404 case CYGNUM_HAL_INTERRUPT_DMAC_DEI2:
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jlarmour
parents: 112
diff changeset
405 case CYGNUM_HAL_INTERRUPT_DMAC_DEI3:
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jlarmour
parents: 112
diff changeset
406 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
407 iprX &= ~CYGARC_REG_IPRE_DMAC_MASK;
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jlarmour
parents: 112
diff changeset
408 iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1;
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jlarmour
parents: 112
diff changeset
409 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
410 break;
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jlarmour
parents: 112
diff changeset
411 case CYGNUM_HAL_INTERRUPT_IRDA_ERI1:
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jlarmour
parents: 112
diff changeset
412 case CYGNUM_HAL_INTERRUPT_IRDA_RXI1:
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jlarmour
parents: 112
diff changeset
413 case CYGNUM_HAL_INTERRUPT_IRDA_BRI1:
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jlarmour
parents: 112
diff changeset
414 case CYGNUM_HAL_INTERRUPT_IRDA_TXI1:
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jlarmour
parents: 112
diff changeset
415 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
416 iprX &= ~CYGARC_REG_IPRE_IRDA_MASK;
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jlarmour
parents: 112
diff changeset
417 iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1;
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jlarmour
parents: 112
diff changeset
418 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
419 break;
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jlarmour
parents: 112
diff changeset
420 case CYGNUM_HAL_INTERRUPT_SCIF_ERI2:
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jlarmour
parents: 112
diff changeset
421 case CYGNUM_HAL_INTERRUPT_SCIF_RXI2:
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jlarmour
parents: 112
diff changeset
422 case CYGNUM_HAL_INTERRUPT_SCIF_BRI2:
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jlarmour
parents: 112
diff changeset
423 case CYGNUM_HAL_INTERRUPT_SCIF_TXI2:
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jlarmour
parents: 112
diff changeset
424 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
425 iprX &= ~CYGARC_REG_IPRE_SCIF_MASK;
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jlarmour
parents: 112
diff changeset
426 iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1;
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jlarmour
parents: 112
diff changeset
427 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
428 break;
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jlarmour
parents: 112
diff changeset
429 case CYGNUM_HAL_INTERRUPT_ADC_ADI:
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jlarmour
parents: 112
diff changeset
430 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
431 iprX &= ~CYGARC_REG_IPRE_ADC_MASK;
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jlarmour
parents: 112
diff changeset
432 iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1;
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jlarmour
parents: 112
diff changeset
433 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents: 112
diff changeset
434 break;
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jlarmour
parents: 112
diff changeset
435
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jlarmour
parents: 112
diff changeset
436 /* IPRF */
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jlarmour
parents: 112
diff changeset
437 case CYGNUM_HAL_INTERRUPT_LCDC_LCDI:
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jlarmour
parents: 112
diff changeset
438 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
439 iprX &= ~CYGARC_REG_IPRF_LCDI_MASK;
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jlarmour
parents: 112
diff changeset
440 iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1;
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jlarmour
parents: 112
diff changeset
441 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
442 break;
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jlarmour
parents: 112
diff changeset
443 case CYGNUM_HAL_INTERRUPT_PCC_PCC0:
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jlarmour
parents: 112
diff changeset
444 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
445 iprX &= ~CYGARC_REG_IPRF_PCC0_MASK;
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jlarmour
parents: 112
diff changeset
446 iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1;
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jlarmour
parents: 112
diff changeset
447 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
448 break;
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jlarmour
parents: 112
diff changeset
449 case CYGNUM_HAL_INTERRUPT_PCC_PCC1:
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jlarmour
parents: 112
diff changeset
450 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
451 iprX &= ~CYGARC_REG_IPRF_PCC1_MASK;
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jlarmour
parents: 112
diff changeset
452 iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1;
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jlarmour
parents: 112
diff changeset
453 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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jlarmour
parents: 112
diff changeset
454 break;
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jlarmour
parents: 112
diff changeset
455
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jlarmour
parents: 112
diff changeset
456 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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jlarmour
parents: 112
diff changeset
457 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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jlarmour
parents: 112
diff changeset
458 /* Do nothing for these reserved vectors. */
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jlarmour
parents: 112
diff changeset
459 break;
128
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jlarmour
parents: 126
diff changeset
460
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jlarmour
parents: 126
diff changeset
461 default:
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jlarmour
parents: 126
diff changeset
462 CYG_FAIL("Unknown interrupt vector");
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jlarmour
parents: 126
diff changeset
463 break;
126
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jlarmour
parents: 112
diff changeset
464 }
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jlarmour
parents: 112
diff changeset
465 }
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jlarmour
parents: 112
diff changeset
466
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jlarmour
parents: 112
diff changeset
467 void
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jlarmour
parents: 112
diff changeset
468 hal_interrupt_mask(int vector)
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jlarmour
parents: 112
diff changeset
469 {
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jlarmour
parents: 112
diff changeset
470 switch( (vector) ) {
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jlarmour
parents: 112
diff changeset
471 case CYGNUM_HAL_INTERRUPT_NMI:
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jlarmour
parents: 112
diff changeset
472 /* fall through */
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jlarmour
parents: 112
diff changeset
473 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
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jlarmour
parents: 112
diff changeset
474 /* Can only be masked by fiddling Imask in SR. */
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jlarmour
parents: 112
diff changeset
475 break;
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jlarmour
parents: 112
diff changeset
476 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX:
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jlarmour
parents: 112
diff changeset
477 HAL_INTERRUPT_SET_LEVEL((vector), 0);
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jlarmour
parents: 112
diff changeset
478 break;
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jlarmour
parents: 112
diff changeset
479 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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parents: 112
diff changeset
480 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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jlarmour
parents: 112
diff changeset
481 /* Do nothing for these reserved vectors. */
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jlarmour
parents: 112
diff changeset
482 break;
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jlarmour
parents: 112
diff changeset
483 default:
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jlarmour
parents: 112
diff changeset
484 CYG_FAIL("Unknown interrupt vector");
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jlarmour
parents: 112
diff changeset
485 break;
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jlarmour
parents: 112
diff changeset
486 }
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jlarmour
parents: 112
diff changeset
487 }
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jlarmour
parents: 112
diff changeset
488
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jlarmour
parents: 112
diff changeset
489 void
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jlarmour
parents: 112
diff changeset
490 hal_interrupt_unmask(int vector)
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jlarmour
parents: 112
diff changeset
491 {
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jlarmour
parents: 112
diff changeset
492 switch( (vector) ) {
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jlarmour
parents: 112
diff changeset
493 case CYGNUM_HAL_INTERRUPT_NMI:
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jlarmour
parents: 112
diff changeset
494 /* fall through */
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jlarmour
parents: 112
diff changeset
495 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
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jlarmour
parents: 112
diff changeset
496 /* Can only be unmasked by fiddling Imask in SR. */
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jlarmour
parents: 112
diff changeset
497 break;
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jlarmour
parents: 112
diff changeset
498 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX:
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jlarmour
parents: 112
diff changeset
499 HAL_INTERRUPT_SET_LEVEL((vector), 1);
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jlarmour
parents: 112
diff changeset
500 break;
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jlarmour
parents: 112
diff changeset
501 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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parents: 112
diff changeset
502 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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jlarmour
parents: 112
diff changeset
503 /* Do nothing for these reserved vectors. */
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jlarmour
parents: 112
diff changeset
504 break;
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jlarmour
parents: 112
diff changeset
505 default:
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jlarmour
parents: 112
diff changeset
506 CYG_FAIL("Unknown interrupt vector");
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jlarmour
parents: 112
diff changeset
507 break;
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jlarmour
parents: 112
diff changeset
508 }
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jlarmour
parents: 112
diff changeset
509 }
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jlarmour
parents: 112
diff changeset
510
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jlarmour
parents: 112
diff changeset
511 void
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jlarmour
parents: 112
diff changeset
512 hal_interrupt_acknowledge(int vector)
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jlarmour
parents: 112
diff changeset
513 {
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jlarmour
parents: 112
diff changeset
514 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
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jlarmour
parents: 112
diff changeset
515 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
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jlarmour
parents: 112
diff changeset
516
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jlarmour
parents: 112
diff changeset
517 cyg_uint8 irr0;
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jlarmour
parents: 112
diff changeset
518
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jlarmour
parents: 112
diff changeset
519 HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);
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jlarmour
parents: 112
diff changeset
520 switch ( vector ) {
128
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jlarmour
parents: 126
diff changeset
521 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
126
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jlarmour
parents: 112
diff changeset
522 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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jlarmour
parents: 112
diff changeset
523 irr0 &= ~CYGARC_REG_IRR0_IRQ0;
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jlarmour
parents: 112
diff changeset
524 break;
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jlarmour
parents: 112
diff changeset
525 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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jlarmour
parents: 112
diff changeset
526 irr0 &= ~CYGARC_REG_IRR0_IRQ1;
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jlarmour
parents: 112
diff changeset
527 break;
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jlarmour
parents: 112
diff changeset
528 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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jlarmour
parents: 112
diff changeset
529 irr0 &= ~CYGARC_REG_IRR0_IRQ2;
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jlarmour
parents: 112
diff changeset
530 break;
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jlarmour
parents: 112
diff changeset
531 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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jlarmour
parents: 112
diff changeset
532 irr0 &= ~CYGARC_REG_IRR0_IRQ3;
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jlarmour
parents: 112
diff changeset
533 break;
128
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jlarmour
parents: 126
diff changeset
534 #endif
126
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535 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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536 irr0 &= ~CYGARC_REG_IRR0_IRQ4;
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537 break;
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538 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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539 irr0 &= ~CYGARC_REG_IRR0_IRQ5;
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540 break;
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541 default:
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542 CYG_FAIL("Unhandled interrupt vector");
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543 }
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544 HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);
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545 }
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546 }
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547
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548 // Note: The PINTs can be masked and configured individually, even
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549 // though there are only two vectors. Maybe add some fake vectors just
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550 // for masking/configuring?
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551 void
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552 hal_interrupt_configure(int vector, int level, int up)
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553 {
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554 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
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555 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
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556
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557 cyg_uint16 icr1, ss, mask;
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558 ss = 0;
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559 mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
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560 if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
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561 if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
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562 CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
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563
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564 switch( (vector) ) {
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565 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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566 ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
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567 mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
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568 break;
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569 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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570 ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
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571 mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
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572 break;
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573 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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574 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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575 ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
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576 mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
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577 break;
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578 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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579 ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
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580 mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
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581 break;
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582 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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583 ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
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584 mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
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585 break;
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586 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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587 ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
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588 mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
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589 break;
128
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590 #endif
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591 default:
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592 CYG_FAIL("Unhandled interrupt vector");
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593 }
126
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594
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595 HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
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596 icr1 &= ~mask;
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597 icr1 |= ss;
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598 HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
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599 }
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600 }
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601
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602 //---------------------------------------------------------------------------
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603 // End of hal_misc.c