Mercurial > flash_v2
annotate packages/hal/powerpc/adder/current/src/adder.S @ 1453:0e3378e69a2a
Fix some issues with network debugging by not clearing caches on startup
| author | gthomas |
|---|---|
| date | Sun, 21 Dec 2003 13:41:17 +0000 |
| parents | 725ba4e57f0c |
| children |
| rev | line source |
|---|---|
| 432 | 1 ##============================================================================= |
| 2 ## | |
| 3 ## adder.S | |
| 4 ## | |
| 5 ## ADDER board hardware setup | |
| 6 ## | |
| 7 ##============================================================================= | |
| 8 #####ECOSGPLCOPYRIGHTBEGIN#### | |
| 9 ## ------------------------------------------- | |
| 10 ## This file is part of eCos, the Embedded Configurable Operating System. | |
| 11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. | |
|
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12 ## Copyright (C) 2002, 2003 Gary Thomas |
| 432 | 13 ## |
| 14 ## eCos is free software; you can redistribute it and/or modify it under | |
| 15 ## the terms of the GNU General Public License as published by the Free | |
| 16 ## Software Foundation; either version 2 or (at your option) any later version. | |
| 17 ## | |
| 18 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 19 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 21 ## for more details. | |
| 22 ## | |
| 23 ## You should have received a copy of the GNU General Public License along | |
| 24 ## with eCos; if not, write to the Free Software Foundation, Inc., | |
| 25 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
| 26 ## | |
| 27 ## As a special exception, if other files instantiate templates or use macros | |
| 28 ## or inline functions from this file, or you compile this file and link it | |
| 29 ## with other works to produce a work based on this file, this file does not | |
| 30 ## by itself cause the resulting work to be covered by the GNU General Public | |
| 31 ## License. However the source code for this file must still be made available | |
| 32 ## in accordance with section (3) of the GNU General Public License. | |
| 33 ## | |
| 34 ## This exception does not invalidate any other reasons why a work based on | |
| 35 ## this file might be covered by the GNU General Public License. | |
| 36 ## | |
| 37 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. | |
| 38 ## at http://sources.redhat.com/ecos/ecos-license/ | |
| 39 ## ------------------------------------------- | |
| 40 #####ECOSGPLCOPYRIGHTEND#### | |
| 41 ##============================================================================= | |
| 42 #######DESCRIPTIONBEGIN#### | |
| 43 ## | |
| 44 ## Author(s): hmt | |
| 45 ## Contributors:hmt, gthomas | |
| 46 ## Date: 1999-06-08 | |
| 47 ## Purpose: ADDER board hardware setup | |
| 48 ## Description: This file contains any code needed to initialize the | |
| 49 ## hardware on a ADDER PPC860 board. | |
| 50 ## | |
| 51 ######DESCRIPTIONEND#### | |
| 52 ## | |
| 53 ##============================================================================= | |
| 54 | |
| 55 #include <pkgconf/hal.h> | |
| 56 | |
| 57 #include <cyg/hal/arch.inc> /* register symbols et al */ | |
| 58 #include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */ | |
| 59 /* registers, IMM layout... */ | |
| 60 #include <cyg/hal/quicc/ppc8xx.h> /* more of the same */ | |
| 61 | |
| 62 #------------------------------------------------------------------------------ | |
| 63 # this is controlled with one define for tidiness: | |
| 64 # (and it is undefined by default) | |
| 65 | |
| 66 //#define CYGPRI_RAM_START_PROGRAMS_UPMS | |
| 67 | |
| 68 #if defined(CYG_HAL_STARTUP_ROM) \ | |
| 69 || defined(CYG_HAL_STARTUP_ROMRAM) \ | |
| 70 || defined(CYGPRI_RAM_START_PROGRAMS_UPMS) | |
| 71 # define CYGPRI_DO_PROGRAM_UPMS | |
| 72 #endif | |
| 73 | |
| 74 /* The intention is that we only set up the UPMs in ROM start, be it actual | |
| 75 * ROM application start or Stub ROMs that we built from the same sources. | |
| 76 * | |
| 77 * The alternative approach - in which we have reliability doubts - is to | |
| 78 * program the UPMs with *old* timing data in StubROM start, then | |
| 79 * *reprogram* them with *new* timing data in RAM start - and of course | |
| 80 * program with *new* timing data in plain ROM application start. | |
| 81 * (Re-programming from new to new timing data fails - hence the suspicion | |
| 82 * of reprogramming _at_all_, hence this private configuration) | |
| 83 * | |
| 84 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour | |
| 85 * - programming the UPMs exactly once - is obtained. Define it to get the | |
| 86 * latter, untrusted behaviour. | |
| 87 */ | |
| 88 | |
| 89 #------------------------------------------------------------------------------ | |
| 90 | |
| 91 FUNC_START( hal_hardware_init ) | |
| 92 | |
| 93 # Throughout this routine, r4 is the base address of the control | |
| 94 # registers. r3 and r5 are scratch in general. | |
| 95 | |
| 96 lwi r4,CYGARC_REG_IMM_BASE # base address of control registers | |
| 97 mtspr CYGARC_REG_IMMR,r4 | |
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98 |
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99 #ifndef CYG_HAL_STARTUP_RAM |
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100 |
| 432 | 101 #define CACHE_UNLOCKALL 0x0a00 |
| 102 #define CACHE_DISABLE 0x0400 | |
| 103 #define CACHE_INVALIDATEALL 0x0c00 | |
| 104 #define CACHE_ENABLE 0x0200 | |
| 105 #define CACHE_ENABLEBIT 0x8000 | |
| 106 | |
| 107 #define CACHE_FORCEWRITETHROUGH 0x0100 | |
| 108 #define CACHE_NOWRITETHROUGH 0x0300 | |
| 109 #define CACHE_CLEAR_LE_SWAP 0x0700 | |
| 110 | |
| 111 # DATA CACHE | |
| 112 mfspr r3,CYGARC_REG_DC_CST /* clear error bits */ | |
| 113 lis r3,CACHE_UNLOCKALL | |
| 114 sync | |
| 115 mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */ | |
| 116 | |
| 117 lis r3,CACHE_INVALIDATEALL | |
| 118 sync | |
| 119 mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */ | |
| 120 | |
| 121 lis r3,CACHE_DISABLE | |
| 122 sync | |
| 123 mtspr CYGARC_REG_DC_CST,r3 /* disable */ | |
| 124 | |
| 125 lis r3,CACHE_FORCEWRITETHROUGH | |
| 126 sync | |
| 127 mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */ | |
| 128 | |
| 129 lis r3,CACHE_CLEAR_LE_SWAP | |
| 130 sync | |
| 131 mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */ | |
| 132 /* (dunno what this is, but it sounds like a bad thing) */ | |
| 133 | |
| 134 # INSTRUCTION CACHE (no writeback modes) | |
| 135 mfspr r3,CYGARC_REG_IC_CST /* clear error bits */ | |
| 136 lis r3,CACHE_UNLOCKALL | |
| 137 mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */ | |
| 138 isync | |
| 139 lis r3,CACHE_INVALIDATEALL | |
| 140 mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */ | |
| 141 isync | |
| 142 lis r3,CACHE_DISABLE | |
| 143 mtspr CYGARC_REG_IC_CST,r3 /* disable */ | |
| 144 isync | |
| 145 | |
| 146 sync | |
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147 |
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148 #endif // ! CYG_HAL_STARTUP_RAM |
| 432 | 149 |
| 150 /* | |
| 151 * SIU Initialization. | |
| 152 */ | |
| 153 lwi r3,0x00610400 | |
| 154 stw r3,SIUMCR(r4) | |
| 155 | |
| 156 #ifdef CYG_HAL_STARTUP_ROMRAM | |
| 157 // Need to set the PC into the FLASH (ROM) before the address map changes | |
| 158 lwi r3,10f | |
| 159 lwi r5,0xFE000000 | |
| 160 or r3,r3,r5 | |
| 161 mtctr r3 | |
| 162 bctr | |
| 163 10: | |
| 164 #endif | |
| 165 | |
| 166 /* | |
| 167 * Enable bus monitor. Disable Watchdog timer. | |
| 168 */ | |
| 169 lwi r3,0xffffff88 | |
| 170 stw r3,SYPCR(r4) | |
| 171 | |
| 172 /* | |
| 173 * Clear REFA & REFB. Enable but freeze timebase. | |
| 174 */ | |
| 175 lwi r3,0x0000 // FIXME: should this be 0x0000 or 0x00C2 | |
| 176 sth r3,TBSCR(r4) | |
| 177 | |
| 178 /* | |
| 179 * Unlock some RTC registers (see section 5.11.2) | |
| 180 */ | |
| 181 lwi r3,0x55ccaa33 | |
| 182 stw r3,RTCSCK(r4) | |
| 183 stw r3,RTCK(r4) | |
| 184 stw r3,RTSECK(r4) | |
| 185 stw r3,RTCALK(r4) | |
| 186 | |
| 187 /* | |
| 188 * Clear SERC & ALR. RTC runs on freeze. Enable RTC. | |
| 189 */ | |
| 190 li r3,0x0000 // FIXME: should this be 0x0000 or 0x00C3 | |
| 191 sth r3,RTCSC(r4) | |
| 192 | |
| 193 /* | |
| 194 * Clear periodic timer interrupt status. | |
| 195 * Enable periodic timer and stop it on freeze. | |
| 196 */ | |
| 197 li r3,0x0001 // FIXME: should this be 0x0001 or 0x0083 | |
| 198 sth r3,PISCR(r4) | |
| 199 | |
| 200 #ifdef CYGPRI_DO_PROGRAM_UPMS | |
| 201 /* | |
| 202 * Perform UPM programming by writing to its 64 RAM locations. | |
| 203 * Note that UPM initialization must be done before the Bank Register | |
| 204 * initialization. Otherwise, system may hang when writing to Bank | |
| 205 * Registers in certain cases. | |
| 206 */ | |
| 207 lis r5,__upmtbl_start@h | |
| 208 ori r5,r5,__upmtbl_start@l | |
| 209 lis r6,__upmtbl_end@h | |
| 210 ori r6,r6,__upmtbl_end@l | |
| 211 sub r7,r6,r5 /* size of table */ | |
| 212 srawi r7,r7,2 /* in words */ | |
| 213 | |
| 214 li r6,0x00000000 /* Command - OP=Write, UPMA, MAD=0 */ | |
| 215 1: | |
| 216 lwz r3,0(r5) /* get data from table */ | |
| 217 stw r3,MDR(r4) /* store the data to MD register */ | |
| 218 stw r6,MCR(r4) /* issue command to MCR register */ | |
| 219 addi r5,r5,4 /* next entry in the table */ | |
| 220 addi r6,r6,1 /* next MAD address */ | |
| 221 cmpw r6,r7 /* done yet ? */ | |
| 222 blt 1b | |
| 223 #endif // CYGPRI_DO_PROGRAM_UPMS | |
| 224 | |
| 225 /* | |
| 226 * Set refresh timer prescaler to divide by 8. | |
| 227 */ | |
| 228 li r3,PTP_DIV32 | |
| 229 sth r3,MPTPR(r4) | |
| 230 | |
| 231 /* | |
| 232 * See Table 15-16 MPC860 User's Manual. | |
| 233 * | |
| 234 // Set the value of Machine A Mode Register (MAMR) to $5E802114. | |
| 235 // Field PTA (bits 0-7) = 94 | |
| 236 // Field PTAE (bit 8) = 1 | |
| 237 // Field AMA (bits 9-11) = 0 | |
| 238 // Field Reserved (bit 12) = 0 | |
| 239 // Field DSA (bits 13-14) = 0 | |
| 240 // Field Reserved (bit 15) = 0 | |
| 241 // Field G0CLA (bits 16-18) = 1 | |
| 242 // Field GPL_A4DIS (bit 19) = 0 | |
| 243 // Field RLFA (bits 20-23) = 1 | |
| 244 // Field WLFA (bits 24-27) = 1 | |
| 245 // Field TLFA (bits 28-31) = 4 | |
| 246 */ | |
| 247 | |
| 248 // | |
| 249 // PTA field is (System Clock in MHz * Refresh rate in us) / Prescale | |
| 250 // e.g. ((14*3.6864)*62.5)/32 => 100.8 => 101 | |
| 251 // | |
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252 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) |
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253 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 48) |
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254 #define PLPRCR_VALUE 0x32594000 // MFI=9 MFN=6 MFD=9 PDF=0 S=1 OSCLK=10MEG |
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255 #define MAMR_PTA 93 //sysclk * 62.5e-6 /32 |
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256 #endif |
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257 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 50) |
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258 #define PLPRCR_VALUE 0xD05A4000 // MFI=10 MFN=0 MFD=1 PDF=0 S=1 OSCLK=10MEG |
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259 #define MAMR_PTA 97 //sysclk * 62.5e-6 /32 |
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260 #endif |
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261 #else |
| 432 | 262 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47) |
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263 #define PLPRCR_VALUE 0x00C04000 // MFI=9 MFN=6 MFD=9 PDF=0 S=1 OSCLK=10MEG |
| 432 | 264 #define MAMR_PTA 94 |
| 265 #endif | |
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266 #endif |
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267 |
| 432 | 268 //#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF) |
| 269 lwi r3,0x00802114|(MAMR_PTA<<24) | |
| 270 stw r3,MAMR(r4) | |
| 271 stw r3,MBMR(r4) | |
| 272 | |
| 273 /* | |
| 274 * Base Register initialization. | |
| 275 */ | |
| 276 | |
| 277 /* BOOT ROM */ | |
| 278 lwi r3,0xFE000801 # 16-bit, GPCM | |
| 279 lwi r5,0xFF800774 # 7 wait states, up to 8MB | |
| 280 stw r3,BR0(r4) | |
| 281 stw r5,OR0(r4) | |
| 282 | |
| 283 /* Misc I/O, 16 bit port */ | |
| 284 lwi r3,0xFA100801 | |
| 285 lwi r5,0xFFFF8730 | |
| 286 stw r3,BR2(r4) | |
| 287 stw r5,OR2(r4) | |
| 288 | |
| 289 /* ONBOARD DRAM */ | |
| 290 lwi r3,0x00000081 # 32-bit, UPMA | |
| 291 lwi r5,0xFF800E00 | |
| 292 stw r3,BR1(r4) | |
| 293 stw r5,OR1(r4) | |
| 294 | |
| 295 /* DRAM DIMM BANK1 */ | |
| 296 lwi r3,0x00000080 # 32-bit, UPMA, INVALID | |
| 297 lwi r5,0xFFFF87FC | |
| 298 stw r3,BR3(r4) | |
| 299 stw r5,OR3(r4) | |
| 300 | |
| 301 #if 0 | |
| 302 /* NVRAM */ | |
| 303 lwi r3,0xfa000401 # 8-bit, GPCM | |
| 304 lwi r5,0xffe00930 | |
| 305 stw r3,BR4(r4) | |
| 306 stw r5,OR4(r4) | |
| 307 | |
| 308 /* PCI BRIDGE MEM/IO */ | |
| 309 lwi r3,0x80000001 # 32-bit, GPCM | |
| 310 lwi r5,0xa0000108 | |
| 311 stw r3,BR5(r4) | |
| 312 stw r5,OR5(r4) | |
| 313 | |
| 314 /* PCI BRIDGE REGISTERS */ | |
| 315 lwi r3,0xfa210001 # 32-bit, GPCM | |
| 316 lwi r5,0xffff0108 | |
| 317 stw r3,BR6(r4) | |
| 318 stw r5,OR6(r4) | |
| 319 | |
| 320 /* FLASH */ | |
| 321 lwi r3,0xfc000001 # 32-bit, GPCM | |
| 322 lwi r5,0xff800940 | |
| 323 stw r3,BR7(r4) | |
| 324 stw r5,OR7(r4) | |
| 325 #endif | |
| 326 | |
| 327 /* | |
| 328 * SYSTEM CLOCK CONTROL REGISTER | |
| 329 // Set the value of System Clock and Reset Control Register (SCCR) to $00400000. | |
| 330 // Field Reserved (bit 0) = 0 | |
| 331 // Field COM (bits 1-2) = 0 | |
| 332 // Field Reserved (bits 3-5) = 0 | |
| 333 // Field TBS (bit 6) = 0 | |
| 334 // Field RTDIV (bit 7) = 0 | |
| 335 // Field RTSEL (bit 8) = 0 | |
| 336 // Field CRQEN (bit 9) = 1 | |
| 337 // Field PRQEN (bit 10) = 0 | |
| 338 // Field Reserved (bits 11-12) = 0 | |
| 339 // Field EBDF (bits 13-14) = 0 | |
| 340 // Field Reserved (bits 15-16) = 0 | |
| 341 // Field DFSYNC (bits 17-18) = 0 | |
| 342 // Field DFBRG (bits 19-20) = 0 | |
| 343 // Field DFNL (bits 21-23) = 0 | |
| 344 // Field DFNH (bits 24-26) = 0 | |
| 345 // Field Reserved (bits 27-31) = 0 | |
| 346 */ | |
| 347 lwi r3,0x00400000 | |
| 348 stw r3,SCCR(r4) | |
| 349 | |
| 350 /* | |
| 351 * PLL, LOW POWER, AND RESET CONTROL REGISTER | |
| 352 // Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000. | |
| 353 // Field MF (bits 0-11) = 12 | |
| 354 // Field Reserved (bits 12-15) = 0 | |
| 355 // Field SPLSS (bit 16) = 0 | |
| 356 // Field TEXPS (bit 17) = 1 | |
| 357 // Field Reserved (bit 18) = 0 | |
| 358 // Field TMIST (bit 19) = 0 | |
| 359 // Field Reserved (bit 20) = 0 | |
| 360 // Field CSRC (bit 21) = 0 | |
| 361 // Field LPM (bits 22-23) = 0 | |
| 362 // Field CSR (bit 24) = 0 | |
| 363 // Field LOLRE (bit 25) = 0 | |
| 364 // Field FIOPD (bit 26) = 0 | |
| 365 // Field Reserved (bits 27-31) = 0 | |
| 366 */ | |
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367 // lwi r3,0x04000|(PLPRCR_PTX<<20) |
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368 lwi r3,PLPRCR_VALUE |
| 432 | 369 stw r3,PLPRCR(r4) |
| 370 | |
| 371 lwi r3,0x40000 | |
| 372 mtctr r3 | |
| 373 10: nop | |
| 374 bdnz 10b | |
| 375 | |
| 376 /* SDRAM Initialization Sequence, UPMA, CS1 */ | |
| 377 li r3,0 | |
| 378 stw r3,MAR(r4) | |
| 379 | |
| 380 lwi r3,0x80002115; /* run precharge from loc 21 (0x15) */ | |
| 381 stw r3,MCR(r4) | |
| 382 | |
| 383 lwi r3,0x80002830; /* run refresh 8 times */ | |
| 384 stw r3,MCR(r4) | |
| 385 | |
| 386 lwi r3,0x88; /* MR 88 for high range */ | |
| 387 stw r3,MAR(r4) | |
| 388 | |
| 389 lwi r3,0x80002116; /* run MRS pattern from loc 22 (0x16) */ | |
| 390 stw r3,MCR(r4) | |
| 391 | |
| 392 # mask interrupt sources in the SIU | |
| 393 lis r2,0 | |
| 394 lwi r3,CYGARC_REG_IMM_SIMASK | |
| 395 stw r2,0(r3) | |
| 396 | |
| 397 # set the decrementer to maxint | |
| 398 lwi r2,0 | |
| 399 not r2,r2 | |
| 400 mtdec r2 | |
| 401 | |
| 402 # and enable the timebase and decrementer to make sure | |
| 403 li r2,1 # TBEnable and not TBFreeze | |
| 404 lwi r3,CYGARC_REG_IMM_TBSCR | |
| 405 sth r2,0(r3) | |
| 406 | |
| 407 #ifdef CYG_HAL_STARTUP_ROM | |
| 408 # move return address to where the ROM is | |
| 409 mflr r3 | |
| 410 lwi r4,0x00FFFFFF // CAUTION!! Assumes only low 16M for ROM | |
| 411 and r3,r3,r4 | |
| 412 oris r3,r3,CYGMEM_REGION_rom>>16 | |
| 413 mtlr r3 | |
| 414 #endif | |
| 415 | |
| 416 #ifdef CYG_HAL_STARTUP_ROMRAM | |
| 417 // Copy image from ROM to RAM | |
| 418 mflr r3 | |
| 419 lwi r4,0xFE000000 | |
| 420 lwi r5,0x01FFFFFF // ROM/FLASH base | |
| 421 and r3,r3,r5 // segment relative | |
| 422 lwi r6,_hal_hardware_init_done | |
| 423 mtlr r6 | |
| 424 sub r6,r3,r6 // Absolute address | |
| 425 add r6,r6,r4 // FLASH address | |
| 426 lwi r7,0 // where to copy to | |
| 427 lwi r8,__ram_data_end | |
| 428 10: lwz r5,0(r6) | |
| 429 stw r5,0(r7) | |
| 430 addi r6,r6,4 | |
| 431 addi r7,r7,4 | |
| 432 cmplw r7,r8 | |
| 433 bne 10b | |
| 434 #endif | |
| 435 blr | |
| 436 FUNC_END( hal_hardware_init ) | |
| 437 | |
| 438 | |
| 439 #ifdef CYGPRI_DO_PROGRAM_UPMS | |
| 440 # ------------------------------------------------------------------------- | |
| 441 # this table initializes the User Programmable Machine (UPM) nastiness | |
| 442 # in the QUICC to control DRAM timing. | |
| 443 | |
| 444 __upmtbl_start: | |
| 445 // single read (offset 0x00 in upm ram) | |
| 446 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00 | |
| 447 .long 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04 | |
| 448 // burst read (offset 0x08 in upm ram) | |
| 449 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00 | |
| 450 .long 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44 | |
| 451 .long 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35 | |
| 452 .long 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35 | |
| 453 // single write (offset 0x18 in upm ram) | |
| 454 .long 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47 | |
| 455 .long 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 456 // burst write (offset 0x20 in upm ram) | |
| 457 .long 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00 | |
| 458 .long 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04 | |
| 459 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 460 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 461 // refresh (offset 0x30 in upm ram) | |
| 462 .long 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 463 .long 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04 | |
| 464 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 465 // exception (offset 0x3C in upm ram) | |
| 466 .long 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 | |
| 467 __upmtbl_end: | |
| 468 #endif // CYGPRI_DO_PROGRAM_UPMS | |
| 469 | |
| 470 #------------------------------------------------------------------------------ | |
| 471 # end of adder.S |