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annotate packages/devs/serial/sh/sci/current/src/sh_sci_serial.c @ 124:0ec04793409a ecos-sw-2000-09-11

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Merge from eCos master repository on 2000-09-11-03:00:13-BST
author jlarmour
date Mon, 11 Sep 2000 02:42:46 +0000
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children 0c2b7be0d798
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1 //==========================================================================
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2 //
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3 // io/serial/sh/sh_sci_serial.c
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4 //
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5 // SH Serial SCI I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:gthomas, jskov
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36 // Date: 1999-05-24
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37 // Purpose: SH Serial I/O module (interrupt driven version)
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38 // Description:
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39 //
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40 // Note: Since interrupt sources from the same SCI channel share the same
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41 // interrupt level, there is no risk of races when altering the
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42 // channel's control register from ISRs and DSRs. However, when
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43 // altering the control register from user-level code, interrupts
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44 // must be disabled while the register is being accessed.
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45 //
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46 // FIXME: Receiving in polled mode prevents duplex transfers from working for
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47 // some reason.
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48 //####DESCRIPTIONEND####
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49 //==========================================================================
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50
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51 #include <pkgconf/io_serial.h>
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52 #include <pkgconf/io.h>
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53
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54 #include <cyg/io/io.h>
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55 #include <cyg/hal/hal_intr.h>
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56 #include <cyg/io/devtab.h>
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57 #include <cyg/infra/diag.h>
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58 #include <cyg/io/serial.h>
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59
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60 #include <cyg/hal/sh_regs.h>
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61
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62 // Only compile driver if an inline file with driver details was selected.
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63 #ifdef CYGDAT_IO_SERIAL_SH_SCI_INL
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64
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65 // Controller base (only one supported at the moment)
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66 #define SH_SERIAL_SCI_BASE 0xfffffe80
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67
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68 // The SCI controller register layout on the SH3/7708.
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69 #define SCI_SCSMR 0 // serial mode register
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70 #define SCI_SCBRR 2 // bit rate register
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71 #define SCI_SCSCR 4 // serial control register
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72 #define SCI_SCTDR 6 // transmit data register
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73 #define SCI_SCSSR 8 // serial status register
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74 #define SCI_SCRDR 10 // receive data register
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75 #define SCI_SCSPTR -4 // serial port register
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76
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77 static short select_word_length[] = {
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78 -1,
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79 -1,
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80 CYGARC_REG_SCSMR_CHR, // 7 bits
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81 0 // 8 bits
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82 };
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83
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84 static short select_stop_bits[] = {
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85 -1,
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86 0, // 1 stop bit
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87 -1,
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88 CYGARC_REG_SCSMR_STOP // 2 stop bits
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89 };
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90
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91 static short select_parity[] = {
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92 0, // No parity
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93 CYGARC_REG_SCSMR_PE, // Even parity
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94 CYGARC_REG_SCSMR_PE|CYGARC_REG_SCSMR_OE, // Odd parity
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95 -1,
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96 -1
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97 };
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98
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99 static unsigned short select_baud[] = {
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100 0, // Unused
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101 CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
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102 CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
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103 CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
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104 CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
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105 CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
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106 CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
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107 CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
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108 CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
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109 CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
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110 CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
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111 CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
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112 CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
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113 CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
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114 CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
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115 CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
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116 CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
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117 CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),
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118 CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),
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119 CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),
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120 CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),
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121 CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)
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122 };
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123
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124
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125 typedef struct sh_sci_info {
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126 CYG_ADDRWORD data; // Pointer to data register
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127
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128 CYG_WORD er_int_num, // Error interrupt number
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129 rx_int_num, // Receive interrupt number
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130 tx_int_num; // Transmit interrupt number
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131
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132 CYG_ADDRWORD ctrl_base; // Base address of SCI controller
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133
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134 cyg_interrupt serial_er_interrupt,
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135 serial_rx_interrupt,
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136 serial_tx_interrupt;
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137 cyg_handle_t serial_er_interrupt_handle,
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138 serial_rx_interrupt_handle,
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139 serial_tx_interrupt_handle;
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140
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141 bool tx_enabled;
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142 } sh_sci_info;
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143
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144 static bool sh_serial_init(struct cyg_devtab_entry *tab);
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145 static bool sh_serial_putc(serial_channel *chan, unsigned char c);
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146 static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab,
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147 struct cyg_devtab_entry *sub_tab,
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148 const char *name);
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149 static unsigned char sh_serial_getc(serial_channel *chan);
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150 static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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151 const void *xbuf, cyg_uint32 *len);
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152 static void sh_serial_start_xmit(serial_channel *chan);
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153 static void sh_serial_stop_xmit(serial_channel *chan);
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154
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155 static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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156 static void sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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157 cyg_addrword_t data);
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158 static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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159 static void sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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160 cyg_addrword_t data);
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161 static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data);
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162 static void sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count,
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163 cyg_addrword_t data);
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164
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165 static SERIAL_FUNS(sh_serial_funs,
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166 sh_serial_putc,
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167 sh_serial_getc,
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168 sh_serial_set_config,
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169 sh_serial_start_xmit,
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170 sh_serial_stop_xmit
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171 );
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172
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173 #include CYGDAT_IO_SERIAL_SH_SCI_INL
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174
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175 // Internal function to actually configure the hardware to desired baud rate,
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176 // etc.
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177 static bool
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178 sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,
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179 bool init)
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180 {
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181 cyg_uint16 baud_divisor = select_baud[new_config->baud];
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182 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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183 cyg_uint8 _scr, _smr;
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184
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185 // Check configuration request
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186 if ((-1 == select_word_length[(new_config->word_length -
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187 CYGNUM_SERIAL_WORD_LENGTH_5)])
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188 || -1 == select_stop_bits[new_config->stop]
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189 || -1 == select_parity[new_config->parity]
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190 || baud_divisor == 0)
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191 return false;
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192
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193 // Disable SCI interrupts while changing hardware
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194 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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195 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0);
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196
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197 // Set databits, stopbits and parity.
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198 _smr = select_word_length[(new_config->word_length -
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199 CYGNUM_SERIAL_WORD_LENGTH_5)] |
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200 select_stop_bits[new_config->stop] |
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201 select_parity[new_config->parity];
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202 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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203
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204 // Set baud rate.
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205 _smr &= ~CYGARC_REG_SCSMR_CKSx_MASK;
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206 _smr |= baud_divisor >> 8;
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207 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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208 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff);
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209
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210 // Clear the status register.
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211 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0);
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212
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213 if (init) {
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214 // Always enable transmitter and receiver.
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215 _scr = CYGARC_REG_SCSCR_TE | CYGARC_REG_SCSCR_RE;
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216
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217 if (chan->out_cbuf.len != 0)
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218 _scr |= CYGARC_REG_SCSCR_TIE; // enable tx interrupts
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219
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220 if (chan->in_cbuf.len != 0)
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221 _scr |= CYGARC_REG_SCSCR_RIE; // enable rx interrupts
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222 }
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223
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224 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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225
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226 if (new_config != &chan->config) {
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227 chan->config = *new_config;
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228 }
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229 return true;
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230 }
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231
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232 // Function to initialize the device. Called at bootstrap time.
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233 static bool
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234 sh_serial_init(struct cyg_devtab_entry *tab)
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235 {
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236 serial_channel *chan = (serial_channel *)tab->priv;
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237 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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238 #ifdef CYGDBG_IO_INIT
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239 diag_printf("SH SERIAL init - dev: %x.%d\n",
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240 sh_chan->data, sh_chan->rx_int_num);
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241 #endif
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242 // Really only required for interrupt driven devices
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243 (chan->callbacks->serial_init)(chan);
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244
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245 if (chan->out_cbuf.len != 0) {
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246 cyg_drv_interrupt_create(sh_chan->tx_int_num,
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247 3,
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248 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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249 sh_serial_tx_ISR,
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250 sh_serial_tx_DSR,
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251 &sh_chan->serial_tx_interrupt_handle,
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252 &sh_chan->serial_tx_interrupt);
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253 cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle);
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254 cyg_drv_interrupt_unmask(sh_chan->tx_int_num);
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255 sh_chan->tx_enabled = false;
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256 }
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257 if (chan->in_cbuf.len != 0) {
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258 // Receive interrupt
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259 cyg_drv_interrupt_create(sh_chan->rx_int_num,
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260 3,
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261 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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262 sh_serial_rx_ISR,
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263 sh_serial_rx_DSR,
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264 &sh_chan->serial_rx_interrupt_handle,
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265 &sh_chan->serial_rx_interrupt);
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266 cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle);
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267 // Receive error interrupt
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268 cyg_drv_interrupt_create(sh_chan->er_int_num,
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269 3,
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270 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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271 sh_serial_er_ISR,
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272 sh_serial_er_DSR,
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273 &sh_chan->serial_er_interrupt_handle,
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274 &sh_chan->serial_er_interrupt);
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275 cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle);
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276 // This unmasks both interrupt sources.
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277 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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278 }
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279 sh_serial_config_port(chan, &chan->config, true);
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280 return true;
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281 }
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282
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283 // This routine is called when the device is "looked" up (i.e. attached)
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284 static Cyg_ErrNo
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285 sh_serial_lookup(struct cyg_devtab_entry **tab,
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286 struct cyg_devtab_entry *sub_tab,
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287 const char *name)
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288 {
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289 serial_channel *chan = (serial_channel *)(*tab)->priv;
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290
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291 // Really only required for interrupt driven devices
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292 (chan->callbacks->serial_init)(chan);
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293 return ENOERR;
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294 }
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295
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296 // Send a character to the device output buffer.
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297 // Return 'true' if character is sent to device
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298 static bool
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299 sh_serial_putc(serial_channel *chan, unsigned char c)
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300 {
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301 cyg_uint8 _ssr;
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302 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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303
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304 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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305 if (_ssr & CYGARC_REG_SCSSR_TDRE) {
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306 // Transmit buffer is empty
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307 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c);
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308 // Clear empty flag.
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309 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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310 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_TDRE);
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311 return true;
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312 } else {
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313 // No space
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314 return false;
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315 }
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316 }
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317
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318 // Fetch a character from the device input buffer, waiting if necessary
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319 static unsigned char
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320 sh_serial_getc(serial_channel *chan)
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321 {
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322 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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323 unsigned char c;
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324 cyg_uint8 _ssr;
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325
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326 do {
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327 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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328 } while ((_ssr & CYGARC_REG_SCSSR_RDRF) == 0);
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329
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330 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c);
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331
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332 // Clear buffer full flag.
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333 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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334 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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335
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336 return c;
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337 }
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338
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339 // Set up the device characteristics; baud rate, etc.
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340 static Cyg_ErrNo
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341 sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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342 const void *xbuf, cyg_uint32 *len)
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343 {
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344 switch (key) {
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345 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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346 {
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347 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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348 if ( *len < sizeof(cyg_serial_info_t) ) {
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349 return -EINVAL;
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350 }
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351 *len = sizeof(cyg_serial_info_t);
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352 if ( true != sh_serial_config_port(chan, config, false) )
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353 return -EINVAL;
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354 }
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355 break;
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356 default:
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357 return -EINVAL;
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358 }
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359 return ENOERR;
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360 }
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361
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362 // Enable the transmitter on the device
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363 static void
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364 sh_serial_start_xmit(serial_channel *chan)
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365 {
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366 cyg_uint8 _scr;
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367 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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368
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369 sh_chan->tx_enabled = true;
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370
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371 // Mask the interrupts (all sources of the unit) while changing
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372 // the CR since a rx interrupt in the middle of this would result
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373 // in a bad CR state.
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374 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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375
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376 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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377 _scr |= CYGARC_REG_SCSCR_TIE; // Enable xmit interrupt
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378 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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379
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380 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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381 }
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382
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383 // Disable the transmitter on the device
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384 static void
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385 sh_serial_stop_xmit(serial_channel *chan)
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386 {
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387 cyg_uint8 _scr;
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388 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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389
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390 sh_chan->tx_enabled = false;
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391
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392 // Mask the interrupts (all sources of the unit) while changing
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393 // the CR since a rx interrupt in the middle of this would result
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394 // in a bad CR state.
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395 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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396
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397 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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398 _scr &= ~CYGARC_REG_SCSCR_TIE; // Disable xmit interrupt
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399 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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400
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401 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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402 }
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403
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404 // Serial I/O - low level tx interrupt handler (ISR)
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405 static cyg_uint32
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406 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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407 {
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408 serial_channel *chan = (serial_channel *)data;
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409 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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410 cyg_uint8 _scr;
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411
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412 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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413 _scr &= ~CYGARC_REG_SCSCR_TIE; // mask out tx interrupts
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414 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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415
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416 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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417 }
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418
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419 // Serial I/O - high level tx interrupt handler (DSR)
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420 static void
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421 sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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422 {
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423 serial_channel *chan = (serial_channel *)data;
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424 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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425
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426 (chan->callbacks->xmt_char)(chan);
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427
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428 if (sh_chan->tx_enabled) {
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429 cyg_uint8 _scr;
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430
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431 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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432 _scr |= CYGARC_REG_SCSCR_TIE; // unmask tx interrupts
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433 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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434 }
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435 }
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436
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437 // Serial I/O - low level RX interrupt handler (ISR)
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438 static cyg_uint32
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439 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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440 {
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441 serial_channel *chan = (serial_channel *)data;
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442 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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443 cyg_uint8 _scr;
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444
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445 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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446 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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447 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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448 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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449 }
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450
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451 // Serial I/O - high level rx interrupt handler (DSR)
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452 static void
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453 sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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454 {
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455 serial_channel *chan = (serial_channel *)data;
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456 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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457 cyg_uint8 _ssr, _scr;
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458
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459 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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460 if (_ssr & CYGARC_REG_SCSSR_RDRF) {
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461 cyg_uint8 _c;
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462 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c);
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463 // Clear buffer full flag.
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464 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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465 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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466
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467 (chan->callbacks->rcv_char)(chan, _c);
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468 }
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469
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470 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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471 _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts
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472 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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473 }
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474
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475 static volatile int sh_serial_error_orer = 0;
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476 static volatile int sh_serial_error_fer = 0;
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477 static volatile int sh_serial_error_per = 0;
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478
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479 // Serial I/O - low level error interrupt handler (ISR)
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480 static cyg_uint32
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481 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data)
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482 {
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483 serial_channel *chan = (serial_channel *)data;
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484 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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485 cyg_uint8 _scr;
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486
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487 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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488 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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489 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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490 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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491 }
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492
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493 // Serial I/O - high level error interrupt handler (DSR)
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494 static void
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495 sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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496 {
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497 serial_channel *chan = (serial_channel *)data;
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498 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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499 cyg_uint8 _ssr, _ssr2;
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500
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501 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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502 _ssr2 = CYGARC_REG_SCSSR_CLEARMASK;
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503
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504 if (_ssr & CYGARC_REG_SCSSR_ORER) {
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505 _ssr2 &= ~CYGARC_REG_SCSSR_ORER;
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506 sh_serial_error_orer++;
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507 }
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508 if (_ssr & CYGARC_REG_SCSSR_FER) {
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509 _ssr2 &= ~CYGARC_REG_SCSSR_FER;
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510 sh_serial_error_fer++;
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511 }
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512 if (_ssr & CYGARC_REG_SCSSR_PER) {
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513 _ssr2 &= ~CYGARC_REG_SCSSR_PER;
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514 sh_serial_error_per++;
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515 }
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516 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2);
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517 }
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518
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519 #endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL