Mercurial > flash_v2
annotate packages/hal/arm/arch/current/src/vectors.S @ 28:18ee5a9c102e ecos-sw-1999-08-09
Merge from eCos master repository on 1999-08-09-17:04:48-BST
| author | jlarmour |
|---|---|
| date | Mon, 09 Aug 1999 16:37:19 +0000 |
| parents | 4741a3c3496a |
| children | 29bc183297e1 |
| rev | line source |
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| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 // ####COPYRIGHTEND#### | |
| 29 // #======================================================================== | |
| 30 // ######DESCRIPTIONBEGIN#### | |
| 31 // # | |
| 32 // # Author(s): nickg, gthomas | |
| 33 // # Contributors: nickg, gthomas | |
| 34 // # Date: 1999-02-20 | |
| 35 // # Purpose: ARM exception vectors | |
| 36 // # Description: This file defines the code placed into the exception | |
| 37 // # vectors. It also contains the first level default VSRs | |
| 38 // # that save and restore state for both exceptions and | |
| 39 // # interrupts. | |
| 40 // # | |
| 41 // #####DESCRIPTIONEND#### | |
| 42 // # | |
| 43 // #======================================================================== | |
| 44 | |
| 45 #include <pkgconf/hal.h> | |
| 46 #include <pkgconf/hal_arm.h> | |
| 47 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 48 #include <pkgconf/kernel.h> | |
| 49 #else | |
| 50 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
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51 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 52 #endif |
| 53 #include <cyg/hal/hal_platform_setup.h> | |
| 54 | |
| 55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 56 // The CDL should enforce this | |
| 57 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 58 #endif | |
| 59 | |
| 60 #include "arm.inc" | |
| 61 | |
| 62 #define FUNC_START(name) \ | |
| 63 .globl _name; \ | |
| 64 _name: | |
| 65 | |
| 66 #define PTR(name) \ | |
| 67 .##name: .word name | |
| 68 | |
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69 #ifdef CYGHWR_HAL_ARM_HAS_MMU |
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70 #define UNMAPPED(x) ((x)-__exception_handlers) |
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71 #else |
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72 #define UNMAPPED(x) (x) |
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73 #endif |
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74 |
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75 #define UNMAPPED_PTR(name) \ |
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76 .##name: .word UNMAPPED(name) |
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77 |
| 2 | 78 |
| 79 .file "vectors.S" | |
| 80 | |
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81 |
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82 .macro LED x |
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83 .endm |
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84 |
| 2 | 85 |
| 86 //========================================================================== | |
| 87 // Hardware exception vectors. | |
| 88 // This entire section will be copied to location 0x0000 at startup time. | |
| 89 // | |
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90 .code 32 |
| 2 | 91 .section ".vectors","ax" |
| 92 .global __exception_handlers | |
| 93 __exception_handlers: | |
| 94 ldr pc,.reset_vector // 0x00 | |
| 95 ldr pc,.undefined_instruction // 0x04 | |
| 96 ldr pc,.software_interrupt // 0x08 start && software int | |
| 97 ldr pc,.abort_prefetch // 0x0C | |
| 98 ldr pc,.abort_data // 0x10 | |
| 99 .word 0 // unused | |
| 100 ldr pc,.IRQ // 0x18 | |
| 101 ldr pc,.FIQ // 0x1C | |
| 102 | |
| 103 // The layout of these pointers should match the vector table above since | |
| 104 // they are copied in pairs. | |
| 105 .global vectors | |
| 106 vectors: | |
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107 UNMAPPED_PTR(reset_vector) // 0x20 |
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108 PTR(undefined_instruction) // 0x24 |
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109 PTR(software_interrupt) // 0x28 |
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110 PTR(abort_prefetch) // 0x2C |
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111 PTR(abort_data) // 0x30 |
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112 .word 0 // 0x34 |
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113 PTR(IRQ) // 0x38 |
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114 PTR(FIQ) // 0x3c |
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115 PTR(start) // This is copied to 0x28 for bootup // 0x40 |
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116 // location 0x40 is used for storing DRAM size if known |
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117 // for some platforms. |
| 2 | 118 |
| 119 .text | |
| 120 // Startup code which will get the machine into supervisor mode | |
| 121 .global reset_vector | |
| 122 .type reset_vector,function | |
| 123 reset_vector: | |
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124 |
| 2 | 125 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 126 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 127 mrs r7,cpsr // move back to IRQ mode | |
| 128 and r7,r7,#CPSR_MODE_BITS | |
| 129 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 130 beq start | |
| 131 #endif | |
| 132 | |
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133 PLATFORM_SETUP1 // Early stage platform initialization |
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134 // which can set DRAM size at 0x40 |
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135 // see <cyg/hal/hal_platform_setup.h> |
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136 // We cannot access any LED registers until after PLATFORM_SETUP1 |
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137 LED 7 |
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138 |
| 2 | 139 mov r0,#0 // move vectors |
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140 // We cannot perform a store until after PLATFORM_SETUP1 |
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141 str r0, [r0,#0x40] // DRAM size to zero => unknown |
| 2 | 142 ldr r1,.__exception_handlers |
| 143 ldr r2,[r1,#0x04] // undefined instruction | |
| 144 str r2,[r0,#0x04] | |
| 145 ldr r2,[r1,#0x24] | |
| 146 str r2,[r0,#0x24] | |
| 147 ldr r2,[r1,#0x08] // software interrupt | |
| 148 str r2,[r0,#0x08] | |
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149 #if defined(CYG_HAL_STARTUP_RAM) |
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150 // Ugly hack to get into supervisor mode |
| 2 | 151 ldr r2,[r1,#0x40] |
| 152 str r2,[r0,#0x28] | |
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153 |
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154 LED 6 |
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155 |
| 2 | 156 swi // switch to supervisor mode |
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157 #endif |
| 2 | 158 |
| 159 // ========================================================================= | |
| 160 // Real startup code. We jump here from the reset vector to set up the world. | |
| 161 .globl start | |
| 162 start: | |
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163 |
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164 LED 5 |
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165 |
| 2 | 166 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 167 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 168 // If we get restarted, hang here to avoid corrupting memory | |
| 169 ldr r0,.init_flag | |
| 170 ldr r1,[r0] | |
| 171 1: cmp r1,#0 | |
| 172 bne 1b | |
| 173 ldr r1,init_done | |
| 174 str r1,[r0] | |
| 175 #endif | |
| 176 | |
| 177 // Reset software interrupt pointer | |
| 178 mov r0,#0 // move vectors | |
| 179 ldr r1,.__exception_handlers | |
| 180 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 181 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 182 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 183 beq 10f | |
| 184 #endif | |
| 185 ldr r2,[r1,#0x28] // software interrupt | |
| 186 str r2,[r0,#0x28] | |
| 187 10: | |
| 188 ldr r2,[r1,#0x18] // IRQ | |
| 189 str r2,[r0,#0x18] | |
| 190 ldr r2,[r1,#0x38] | |
| 191 str r2,[r0,#0x38] | |
| 192 ldr r2,[r1,#0x1C] // FIQ | |
| 193 str r2,[r0,#0x1C] | |
| 194 ldr r2,[r1,#0x3C] | |
| 195 str r2,[r0,#0x3C] | |
| 196 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 197 str r2,[r0,#0x0C] | |
| 198 ldr r2,[r1,#0x2C] | |
| 199 str r2,[r0,#0x2C] | |
| 200 ldr r2,[r1,#0x10] // abort (data) | |
| 201 str r2,[r0,#0x10] | |
| 202 ldr r2,[r1,#0x30] | |
| 203 str r2,[r0,#0x30] | |
| 204 | |
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205 LED 4 |
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206 |
| 2 | 207 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) |
| 208 // Relocate [copy] data from ROM to RAM | |
| 209 ldr r3,.__rom_data_start | |
| 210 ldr r4,.__ram_data_start | |
| 211 ldr r5,.__ram_data_end | |
| 212 cmp r4,r5 // jump if no data to move | |
| 213 beq 2f | |
| 214 sub r3,r3,#4 // loop adjustments | |
| 215 sub r4,r4,#4 | |
| 216 1: ldr r0,[r3,#4]! // copy info | |
| 217 str r0,[r4,#4]! | |
| 218 cmp r4,r5 | |
| 219 bne 1b | |
| 220 2: | |
| 221 #endif | |
| 222 | |
| 223 // initialize interrupt/exception environments | |
| 224 ldr sp,.__startup_stack | |
| 225 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 226 msr cpsr,r0 | |
| 227 ldr sp,.__exception_stack | |
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228 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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229 msr cpsr,r0 |
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230 ldr sp,.__FIQ_exception_stack |
| 2 | 231 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 232 msr cpsr,r0 | |
| 233 ldr sp,.__exception_stack | |
| 234 | |
| 235 // initialize CPSR (machine state register) | |
| 236 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 237 msr cpsr,r0 | |
| 238 | |
| 239 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 240 msr spsr,r0 | |
| 241 | |
| 242 // initialize stack | |
| 243 ldr sp,.__startup_stack | |
| 244 | |
| 245 // clear BSS | |
| 246 ldr r1,.__bss_start | |
| 247 ldr r2,.__bss_end | |
| 248 mov r0,#0 | |
| 249 cmp r1,r2 | |
| 250 beq 2f | |
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251 1: str r0,[r1],#4 |
| 2 | 252 cmp r1,r2 |
| 253 bne 1b | |
| 254 2: | |
| 255 | |
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256 |
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257 LED 3 |
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258 |
| 2 | 259 // Call platform specific hardware initialization |
| 260 bl hal_hardware_init | |
| 261 | |
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262 LED 2 |
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263 |
| 2 | 264 // Run through static constructors |
| 265 bl cyg_hal_invoke_constructors | |
| 266 | |
| 267 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 268 bl initialize_stub | |
| 269 #endif | |
| 270 | |
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271 LED 1 |
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272 |
| 2 | 273 // This starts up the eCos kernel |
| 274 bl cyg_start | |
| 275 _start_hang: | |
| 276 b _start_hang | |
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277 .code 32 |
| 2 | 278 |
| 279 init_done: | |
| 280 .long 0xDEADB00B | |
| 281 | |
| 282 // | |
| 283 // Exception handlers | |
| 284 // Assmumption: get here from a Supervisor context [mode] | |
| 285 // | |
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286 .code 32 |
| 2 | 287 undefined_instruction: |
| 288 ldr sp,.__undef_exception_stack // get good stack | |
| 289 sub lr,lr,#4 // PC at time of interrupt | |
| 290 stmfd sp!,{r0,fp,ip,lr} | |
| 291 mrs r0,spsr | |
| 292 stmfd sp!,{r0} | |
| 293 mov ip,sp // save SP which will vanish with | |
| 294 // mode switch | |
| 295 mrs r0,cpsr // switch to Supervisor Mode | |
| 296 bic r0,r0,#CPSR_MODE_BITS | |
| 297 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 298 msr cpsr,r0 // sp,lr are now old values | |
| 299 mov fp,sp | |
| 300 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 301 ldr sp,.__GDB_stack | |
| 302 cmp fp,sp // already on GDB stack? | |
| 303 bhi 10f | |
| 304 ldr r0,.__GDB_stack_base | |
| 305 cmp fp,r0 | |
| 306 bls 10f // no - switch to GDB stack | |
| 307 // (already in sp) | |
| 308 mov sp,fp // yes - no switch | |
| 309 10: | |
| 310 #endif | |
| 311 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 312 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 313 ldmfd ip,{r0-r4} // saved registers | |
| 314 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 315 str r1,[sp,#armreg_r0] // saved R0 | |
| 316 str r2,[sp,#armreg_fp] // saved FP | |
| 317 str r3,[sp,#armreg_ip] // saved IP | |
| 318 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 319 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 320 add r0,ip,#ARMREG_SIZE | |
| 321 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 322 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 323 mov r0,sp | |
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324 bl cyg_hal_report_undefined_instruction |
| 2 | 325 #endif |
| 326 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 327 b call_exception_handler | |
| 328 | |
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329 .code 32 |
| 2 | 330 software_interrupt: |
| 331 ldr sp,.__startup_stack // get good stack | |
| 332 sub lr,lr,#4 // PC at time of interrupt | |
| 333 stmfd sp!,{r0,ip,lr} | |
| 334 mrs r0,spsr | |
| 335 stmfd sp!,{r0} | |
| 336 mov ip,sp // save SP which will vanish with | |
| 337 // mode switch | |
| 338 mrs r0,cpsr // switch to Supervisor Mode | |
| 339 bic r0,r0,#CPSR_MODE_BITS | |
| 340 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 341 msr cpsr,r0 // sp,lr are now old values | |
| 342 mov ip,sp | |
| 343 ldr sp,.__startup_stack // get good stack | |
| 344 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 345 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 346 ldmfd ip,{r0-r3} // saved registers | |
| 347 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 348 str r1,[sp,#armreg_r0] // saved R0 | |
| 349 str r2,[sp,#armreg_ip] // saved IP | |
| 350 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 351 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 352 add r0,ip,#ARMREG_SIZE | |
| 353 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 354 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 355 mov r0,sp | |
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356 bl cyg_hal_report_software_interrupt |
| 2 | 357 #endif |
| 358 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 359 b call_exception_handler | |
| 360 | |
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361 .code 32 |
| 2 | 362 abort_prefetch: |
| 363 ldr sp,.__undef_exception_stack // get good stack | |
| 364 sub lr,lr,#4 // PC at time of interrupt | |
| 365 stmfd sp!,{r0,fp,ip,lr} | |
| 366 mrs r0,spsr | |
| 367 stmfd sp!,{r0} | |
| 368 mov ip,sp // save SP which will vanish with | |
| 369 // mode switch | |
| 370 mrs r0,cpsr // switch to Supervisor Mode | |
| 371 bic r0,r0,#CPSR_MODE_BITS | |
| 372 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 373 msr cpsr,r0 // sp,lr are now old values | |
| 374 mov fp,sp | |
| 375 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 376 ldr sp,.__GDB_stack | |
| 377 cmp fp,sp // already on GDB stack? | |
| 378 bhi 10f | |
| 379 ldr r0,.__GDB_stack_base | |
| 380 cmp fp,r0 | |
| 381 bls 10f // no - switch to GDB stack | |
| 382 // (already in sp) | |
| 383 mov sp,fp // yes - no switch | |
| 384 10: | |
| 385 #endif | |
| 386 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 387 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 388 ldmfd ip,{r0-r4} // saved registers | |
| 389 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 390 str r1,[sp,#armreg_r0] // saved R0 | |
| 391 str r2,[sp,#armreg_fp] // saved FP | |
| 392 str r3,[sp,#armreg_ip] // saved IP | |
| 393 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 394 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 395 add r0,ip,#ARMREG_SIZE | |
| 396 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 397 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 398 mov r0,sp | |
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399 bl cyg_hal_report_abort_prefetch |
| 2 | 400 #endif |
| 401 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 402 b call_exception_handler | |
| 403 | |
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404 .code 32 |
| 2 | 405 abort_data: |
| 406 ldr sp,.__undef_exception_stack // get good stack | |
| 407 sub lr,lr,#4 // PC at time of interrupt | |
| 408 stmfd sp!,{r0,fp,ip,lr} | |
| 409 mrs r0,spsr | |
| 410 stmfd sp!,{r0} | |
| 411 mov ip,sp // save SP which will vanish with | |
| 412 // mode switch | |
| 413 mrs r0,cpsr // switch to Supervisor Mode | |
| 414 bic r0,r0,#CPSR_MODE_BITS | |
| 415 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 416 msr cpsr,r0 // sp,lr are now old values | |
| 417 mov fp,sp | |
| 418 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 419 ldr sp,.__GDB_stack | |
| 420 cmp fp,sp // already on GDB stack? | |
| 421 bhi 10f | |
| 422 ldr r0,.__GDB_stack_base | |
| 423 cmp fp,r0 | |
| 424 bls 10f // no - switch to GDB stack | |
| 425 // (already in sp) | |
| 426 mov sp,fp // yes - no switch | |
| 427 10: | |
| 428 #endif | |
| 429 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 430 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 431 ldmfd ip,{r0-r4} // saved registers | |
| 432 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 433 str r1,[sp,#armreg_r0] // saved R0 | |
| 434 str r2,[sp,#armreg_fp] // saved FP | |
| 435 str r3,[sp,#armreg_ip] // saved IP | |
| 436 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 437 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 438 add r0,ip,#ARMREG_SIZE | |
| 439 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 440 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 441 mov r0,sp | |
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442 bl cyg_hal_report_abort_data |
| 2 | 443 #endif |
| 444 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 445 b call_exception_handler | |
| 446 | |
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447 |
| 2 | 448 // |
| 449 // Dispatch an exception handler. | |
| 450 | |
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451 .code 32 |
| 2 | 452 call_exception_handler: |
| 453 str v1,[sp,#armreg_vector] | |
| 454 mov r0,sp | |
| 455 bl exception_handler | |
| 456 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 457 mov r0,sp | |
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458 bl cyg_hal_report_exception_handler_returned |
| 2 | 459 #endif |
| 460 | |
| 461 // Restore [interrupted] context | |
| 462 mov ip,sp // get stack pointer | |
| 463 | |
| 464 ldr lr,[ip,#armreg_lr] | |
| 465 ldr sp,[sp,#armreg_sp] | |
| 466 | |
| 467 mrs r0,cpsr // move back to IRQ mode | |
| 468 bic r0,r0,#CPSR_MODE_BITS | |
| 469 orr r0,r0,#CPSR_IRQ_MODE | |
| 470 msr cpsr,r0 | |
| 471 | |
| 472 mov sp,ip | |
| 473 ldr lr,[sp,#armreg_pc] | |
| 474 ldr r0,[sp,#armreg_cpsr] | |
| 475 ldr ip,[sp,#armreg_ip] | |
| 476 msr spsr,r0 | |
| 477 ldmfd sp,{r0-r10,fp} | |
| 478 | |
| 479 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 480 | |
| 481 // Handle device interrupts | |
| 482 // This is slightly more complicated than the other exception handlers because | |
| 483 // it needs to interface with the kernel (if present). | |
| 484 | |
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485 .code 32 |
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486 FIQ: |
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487 // Note: I use this exception stack while saving the context because |
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488 // the current SP does not seem to be always valid in this CPU mode. |
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489 ldr sp,.__FIQ_exception_stack // get good stack |
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490 sub lr,lr,#4 // PC at time of interrupt |
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491 stmfd sp!,{r0,fp,ip,lr} |
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492 mrs r0,spsr |
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493 stmfd sp!,{r0} |
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494 b handle_IRQ_or_FIQ |
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495 |
| 2 | 496 IRQ: |
| 497 // Note: I use this exception stack while saving the context because | |
| 498 // the current SP does not seem to be always valid in this CPU mode. | |
| 499 ldr sp,.__exception_stack // get good stack | |
| 500 sub lr,lr,#4 // PC at time of interrupt | |
| 501 stmfd sp!,{r0,fp,ip,lr} | |
| 502 mrs r0,spsr | |
| 503 stmfd sp!,{r0} | |
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504 |
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505 handle_IRQ_or_FIQ: |
| 2 | 506 mov ip,sp // save SP which will vanish with |
| 507 // mode switch | |
| 508 mrs r0,cpsr // switch to Supervisor Mode | |
| 509 bic r0,r0,#CPSR_MODE_BITS | |
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510 orr r0,r0,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE |
| 2 | 511 msr cpsr,r0 // sp,lr are now old values |
| 512 mov fp,sp // save old SP | |
| 513 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 514 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 515 ldmfd ip,{r0-r4} // saved registers | |
| 516 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 517 str r1,[sp,#armreg_r0] // saved R0 | |
| 518 str r2,[sp,#armreg_fp] // saved FP | |
| 519 str r3,[sp,#armreg_ip] // saved IP | |
| 520 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 521 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 522 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 523 mov v6,sp // Save pointer to register frame | |
| 524 | |
| 525 // mov r0,sp | |
| 526 // bl _show_frame_in | |
| 527 | |
| 528 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 529 // Switch to interrupt stack | |
| 530 ldr r2,.irq_level // current number of nested interrupts | |
| 531 ldr r0,[r2] | |
| 532 add r1,r0,#1 | |
| 533 str r1,[r2] // if was zero, switch stacks | |
| 534 cmp r0,#0 | |
| 535 moveq r1,sp // save old stack pointer | |
| 536 ldreq sp,.__interrupt_stack | |
| 537 stmeqfd sp!,{r1} | |
| 538 10: | |
| 539 #endif | |
| 540 | |
| 541 // The entire CPU state is now stashed on the stack, | |
| 542 // increment the scheduler lock and handle the interrupt | |
| 543 | |
| 544 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 545 .extern cyg_scheduler_sched_lock | |
| 546 ldr r3,.cyg_scheduler_sched_lock | |
| 547 ldr r4,[r3] | |
| 548 add r4,r4,#1 | |
| 549 str r4,[r3] | |
| 550 #endif | |
| 551 | |
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552 // TEMP |
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553 mov r0,v6 |
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554 // TEMP |
| 2 | 555 bl hal_IRQ_handler // determine interrupt source |
| 556 mov v1,r0 // returned vector # | |
| 557 | |
| 558 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 559 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 560 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 561 mov r1,v1 // arg1 = vector | |
| 562 mov r2,#0 // arg2 = 0 | |
| 563 bl cyg_instrument // call instrument function | |
| 564 #endif | |
| 565 | |
| 566 mov r0,v1 // vector # | |
| 567 ldr r1,.hal_interrupt_data | |
| 568 ldr r1,[r1,v1,lsl #2] // handler data | |
| 569 ldr r2,.hal_interrupt_handlers | |
| 570 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
| 571 | |
| 572 mov lr,pc // invoke handler (call indirect | |
| 573 mov pc,v3 // thru v3) | |
| 574 | |
| 575 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 576 // If we are returning from the last nested interrupt, move back | |
| 577 // to the thread stack. interrupt_end() must be called on the | |
| 578 // thread stack since it potentially causes a context switch. | |
| 579 ldr r2,.irq_level | |
| 580 ldr r3,[r2] | |
| 581 subs r1,r3,#1 | |
| 582 str r1,[r2] | |
| 583 ldreq sp,[sp] // This should be the saved stack pointer | |
| 584 #endif | |
| 585 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 586 // The return value from the handler (in r0) will indicate whether a | |
| 587 // DSR is to be posted. Pass this together with a pointer to the | |
| 588 // interrupt object we have just used to the interrupt tidy up routine. | |
| 589 | |
| 590 ldr r1,.hal_interrupt_objects | |
| 591 ldr r1,[r1,v1,lsl #2] | |
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592 mov r2,v6 // register frame |
| 2 | 593 bl interrupt_end // post any bottom layer handler |
| 594 // threads and call scheduler | |
| 595 #endif | |
| 596 | |
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597 |
| 2 | 598 // mov r0,sp |
| 599 // bl show_frame_out | |
| 600 | |
| 601 mov ip,sp // get stack pointer | |
| 602 | |
| 603 ldr lr,[ip,#armreg_lr] | |
| 604 ldr sp,[sp,#armreg_sp] | |
| 605 | |
| 606 mrs r0,cpsr // move back to IRQ mode | |
| 607 bic r0,r0,#CPSR_MODE_BITS | |
| 608 orr r0,r0,#CPSR_IRQ_MODE | |
| 609 msr cpsr,r0 | |
| 610 | |
| 611 mov sp,ip | |
| 612 ldr lr,[sp,#armreg_pc] | |
| 613 ldr r0,[sp,#armreg_cpsr] | |
| 614 ldr ip,[sp,#armreg_ip] | |
| 615 msr spsr,r0 | |
| 616 ldmfd sp,{r0-r10,fp} | |
| 617 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 618 | |
| 619 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 620 // Execute pending DSRs the interrupt stack | |
| 621 // Note: this can only be called from code running on a thread stack | |
| 622 .global hal_interrupt_stack_call_pending_DSRs | |
| 623 hal_interrupt_stack_call_pending_DSRs: | |
| 624 stmfd sp!,{r4,r5,lr} | |
| 625 // Disable interrupts | |
| 626 mrs r4,cpsr // disable IRQ's | |
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627 orr r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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628 bic r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 629 msr cpsr,r2 |
| 630 // Switch to interrupt stack | |
| 631 mov r3,sp // save old stack pointer | |
| 632 ldr sp,.__interrupt_stack | |
| 633 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 634 ldr r2,.irq_level // current number of nested interrupts | |
| 635 ldr r3,[r2] | |
| 636 add r3,r3,#1 // bump nesting level | |
| 637 str r3,[r2] | |
| 638 msr cpsr,r5 // enable interrupts | |
| 639 | |
| 640 bl cyg_interrupt_call_pending_DSRs | |
| 641 | |
| 642 // Disable interrupts | |
| 643 mrs r1,cpsr // disable IRQ's | |
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644 orr r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 645 msr cpsr,r2 |
| 646 | |
| 647 // Move back to the thread stack. | |
| 648 ldr r2,.irq_level | |
| 649 ldr r3,[r2] | |
| 650 sub r3,r3,#1 // decrement nesting level | |
| 651 str r3,[r2] | |
| 652 ldr sp,[sp] // This should be the saved stack pointer | |
| 653 msr cpsr,r4 // restore interrupts to original state | |
| 654 | |
| 655 ldmfd sp!,{r4,r5,pc} // return | |
| 656 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
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657 |
| 2 | 658 |
| 659 // Dummy functions | |
| 660 | |
| 661 .global __gccmain | |
| 662 __gccmain: | |
| 663 mov pc,lr | |
| 664 | |
| 665 .global _psr | |
| 666 _psr: | |
| 667 mrs r0,cpsr | |
| 668 mov pc,lr | |
| 669 | |
| 670 .global _sp | |
| 671 _sp: | |
| 672 mov r0,sp | |
| 673 mov pc,lr | |
| 674 | |
| 675 | |
| 676 // | |
| 677 // Pointers to various objects. | |
| 678 // | |
| 679 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 680 PTR(__GDB_stack_base) | |
| 681 PTR(__GDB_stack) | |
| 682 #endif | |
| 683 PTR(__startup_stack) | |
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684 PTR(__FIQ_exception_stack) |
| 2 | 685 PTR(__exception_stack) |
| 686 PTR(__undef_exception_stack) | |
| 687 PTR(__bss_start) | |
| 688 PTR(__bss_end) | |
| 689 PTR(_end) | |
| 690 PTR(__rom_data_start) | |
| 691 PTR(__ram_data_start) | |
| 692 PTR(__ram_data_end) | |
| 693 PTR(hal_interrupt_handlers) | |
| 694 PTR(hal_interrupt_data) | |
| 695 PTR(hal_interrupt_objects) | |
| 696 PTR(__exception_handlers) | |
| 697 PTR(init_flag) | |
| 698 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 699 PTR(cyg_scheduler_sched_lock) | |
| 700 #endif | |
| 701 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 702 PTR(irq_level) | |
| 703 PTR(__interrupt_stack) | |
| 704 #endif | |
| 705 | |
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706 // |
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707 // Identification - useful to find out when a system was configured |
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708 _eCos_id: |
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709 .asciz "eCos : " __DATE__ |
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Merge from eCos master repository on 1999-05-29-00:13:11-BST
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710 |
| 2 | 711 |
| 712 // ------------------------------------------------------------------------- | |
| 713 // Interrupt vector tables. | |
| 714 // These tables contain the isr, data and object pointers used to deliver | |
| 715 // interrupts to user code. | |
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Merge from eCos master repository on 1999-07-16-05:47:06-BST
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716 |
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717 // Despite appearances, their sizes are not #defines, but .equ symbols |
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718 // generated by magic without proper dependencies in arm.inc |
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719 // Recompiling will not DTRT without manual intervention. |
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720 |
| 2 | 721 .data |
| 722 | |
| 723 init_flag: | |
| 724 .long 0 | |
| 725 | |
| 726 .extern hal_default_isr | |
| 727 | |
| 728 .globl hal_interrupt_handlers | |
| 729 hal_interrupt_handlers: | |
| 730 .rept CYGNUM_HAL_ISR_COUNT | |
| 731 .long hal_default_isr | |
| 732 .endr | |
| 733 | |
| 734 .globl hal_interrupt_data | |
| 735 hal_interrupt_data: | |
| 736 .rept CYGNUM_HAL_ISR_COUNT | |
| 737 .long 0 | |
| 738 .endr | |
| 739 | |
| 740 .globl hal_interrupt_objects | |
| 741 hal_interrupt_objects: | |
| 742 .rept CYGNUM_HAL_ISR_COUNT | |
| 743 .long 0 | |
| 744 .endr | |
| 745 | |
| 746 // ------------------------------------------------------------------------- | |
| 747 // Temporary interrupt stack | |
| 748 | |
| 749 .section ".bss" | |
| 750 | |
| 751 // Small stacks, only used for saving information between CPU modes | |
| 752 __exception_stack_base: | |
| 753 .rept 32 | |
| 754 .long 0 | |
| 755 .endr | |
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Merge from eCos master repository on 1999-07-02-23:17:07-BST
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756 __FIQ_exception_stack: |
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757 .rept 32 |
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758 .long 0 |
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759 .endr |
| 2 | 760 __exception_stack: |
| 761 .rept 32 | |
| 762 .long 0 | |
| 763 .endr | |
| 764 __undef_exception_stack: | |
| 765 | |
| 766 // Runtime stack used during all interrupt processing | |
| 767 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 768 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 769 #endif | |
| 770 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 771 .balign 16 | |
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Merge from eCos master repository on 1999-05-21-22:05:54-BST
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772 .global cyg_interrupt_stack_base |
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Merge from eCos master repository on 1999-05-21-22:05:54-BST
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773 cyg_interrupt_stack_base: |
| 2 | 774 __interrupt_stack_base: |
| 775 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 776 .byte 0 | |
| 777 .endr | |
| 778 .balign 16 | |
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779 .global cyg_interrupt_stack |
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780 cyg_interrupt_stack: |
| 2 | 781 __interrupt_stack: |
| 782 irq_level: | |
| 783 .long 0 | |
| 784 #endif | |
| 785 | |
| 786 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 787 .balign 16 | |
| 788 __GDB_stack_base: | |
| 789 .rept 0x400 | |
| 790 .byte 0 | |
| 791 .endr | |
| 792 __GDB_stack: | |
| 793 #endif | |
| 794 .balign 16 | |
| 795 __startup_stack_base: | |
| 796 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 797 .rept 512 | |
| 798 #else | |
| 799 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 800 #endif | |
| 801 .byte 0 | |
| 802 .endr | |
| 803 .balign 16 | |
| 804 __startup_stack: | |
| 805 | |
| 806 // -------------------------------------------------------------------------- | |
| 807 // end of vectors.S |