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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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children 443894e2e912
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/hal_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <cyg/infra/cyg_type.h>
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51
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52 //=============================================================================
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53 // MIPS simulator
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54
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55 #ifdef CYG_HAL_MIPS_SIM
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56
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57 //-----------------------------------------------------------------------------
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58 // Cache dimensions
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59
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60 // Data cache
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61 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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62 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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63 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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64
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65 // Instruction cache
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66 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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67 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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68 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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69
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70 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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71 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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72
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73 //-----------------------------------------------------------------------------
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74 // Global control of data cache
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75
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76 // Enable the data cache
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77 #define HAL_DCACHE_ENABLE()
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78
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79 // Disable the data cache
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80 #define HAL_DCACHE_DISABLE()
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81
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82 // Invalidate the entire cache
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83 #define HAL_DCACHE_INVALIDATE_ALL()
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84
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85 // Synchronize the contents of the cache with memory.
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86 #define HAL_DCACHE_SYNC()
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87
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88 // Set the data cache refill burst size
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89 //#define HAL_DCACHE_BURST_SIZE(_size_)
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90
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91 // Set the data cache write mode
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92 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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93
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94 //#define HAL_DCACHE_WRITETHRU_MODE 0
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95 //#define HAL_DCACHE_WRITEBACK_MODE 1
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96
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97 // Load the contents of the given address range into the data cache
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98 // and then lock the cache so that it stays there.
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99 //#define HAL_DCACHE_LOCK(_base_, _size_)
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100
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101 // Undo a previous lock operation
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102 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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103
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104 //-----------------------------------------------------------------------------
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105 // Data cache line control
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106
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107 // Allocate cache lines for the given address range without reading its
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108 // contents from memory.
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109 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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110
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111 // Write dirty cache lines to memory and invalidate the cache entries
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112 // for the given address range.
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113 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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114
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115 // Invalidate cache lines in the given range without writing to memory.
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116 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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117
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118 // Write dirty cache lines to memory for the given address range.
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119 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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120
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121 // Preread the given range into the cache with the intention of reading
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122 // from it later.
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123 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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124
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125 // Preread the given range into the cache with the intention of writing
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126 // to it later.
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127 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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128
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129 // Allocate and zero the cache lines associated with the given range.
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130 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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131
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132 //-----------------------------------------------------------------------------
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133 // Global control of Instruction cache
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134
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135 // Enable the instruction cache
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136 #define HAL_ICACHE_ENABLE()
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137
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138 // Disable the instruction cache
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139 #define HAL_ICACHE_DISABLE()
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140
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141 // Invalidate the entire cache
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142 #define HAL_ICACHE_INVALIDATE_ALL()
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143
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144 // Synchronize the contents of the cache with memory.
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145 #define HAL_ICACHE_SYNC()
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146
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147 // Set the instruction cache refill burst size
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148 //#define HAL_ICACHE_BURST_SIZE(_size_)
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149
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150 // Load the contents of the given address range into the instruction cache
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151 // and then lock the cache so that it stays there.
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152 //#define HAL_ICACHE_LOCK(_base_, _size_)
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153
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154 // Undo a previous lock operation
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155 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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156
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157 //-----------------------------------------------------------------------------
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158 // Instruction cache line control
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159
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160 // Invalidate cache lines in the given range without writing to memory.
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161 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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162
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163 #endif
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164
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165
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166 //=============================================================================
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167 // Toshiba TX3904
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168
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169 #ifdef CYG_HAL_MIPS_TX3904
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170
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171 //-----------------------------------------------------------------------------
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172 // Cache dimensions
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173
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174 // Data cache
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175 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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176 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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177 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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178
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179 // Instruction cache
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180 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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181 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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182 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
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183
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184 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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185 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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186
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187 //-----------------------------------------------------------------------------
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188 // Global control of data cache
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189
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190 // Enable the data cache
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191 #define HAL_DCACHE_ENABLE() \
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192 { \
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193 asm volatile ("mfc0 $2,$3;" \
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194 "ori $2,$2,0x0010;" \
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195 "mtc0 $2,$3;" \
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196 : \
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197 : \
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198 : "$2" \
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199 ); \
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200 \
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201 }
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202
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203 // Disable the data cache
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204 #define HAL_DCACHE_DISABLE() \
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205 { \
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206 asm volatile ("mfc0 $2,$3;" \
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207 "la $3,0xFFFFFFEF;" \
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208 "and $2,$2,$3;" \
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209 "mtc0 $2,$3;" \
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210 : \
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211 : \
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212 : "$2", "$3" \
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213 ); \
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214 \
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215 }
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216
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217 // Invalidate the entire cache
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218 // We do this by reading a word from each line to invalidate the current
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219 // cache contents.
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220 #define HAL_DCACHE_INVALIDATE_ALL() \
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221 { \
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222 extern char __ram_data_start; \
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223 CYG_WORD *addr = (CYG_WORD *)&__ram_data_start; \
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224 CYG_WORD sum = 0; \
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225 int i; \
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226 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
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227 { \
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228 sum += addr[i]; \
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229 } \
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230 }
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231
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232 // Synchronize the contents of the cache with memory.
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233 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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234
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235 // Set the data cache refill burst size
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236 //#define HAL_DCACHE_BURST_SIZE(_size_)
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237
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238 // Set the data cache write mode
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239 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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240
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241 //#define HAL_DCACHE_WRITETHRU_MODE 0
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242 //#define HAL_DCACHE_WRITEBACK_MODE 1
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243
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244 // Load the contents of the given address range into the data cache
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245 // and then lock the cache so that it stays there.
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246 #define HAL_DCACHE_LOCK(_base_, _size_) \
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247 { \
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248 asm volatile ("mfc0 $2,$7;" \
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249 "ori $2,$2,0x0100;" \
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250 "mtc0 $2,$7;" \
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251 : \
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252 : \
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253 : "$2" \
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254 ); \
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255 }
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256
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257 // Undo a previous lock operation
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258 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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259 { \
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260 asm volatile ("mfc0 $2,$7;" \
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261 "la $3,0xFFFFFEFF;" \
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262 "and $2,$2,$3;" \
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263 "mtc0 $2,$7;" \
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264 : \
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265 : \
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266 : "$2", "$3" \
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267 ); \
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268 }
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269
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270 //-----------------------------------------------------------------------------
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271 // Data cache line control
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272
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273 // Allocate cache lines for the given address range without reading its
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274 // contents from memory.
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275 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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276
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277 // Write dirty cache lines to memory and invalidate the cache entries
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278 // for the given address range.
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279 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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280
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281 // Invalidate cache lines in the given range without writing to memory.
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282 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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283 { \
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284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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285 register CYG_WORD _size_ = (_asize_); \
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286 HAL_DCACHE_DISABLE(); \
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287 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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288 { \
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289 asm volatile ("cache 17,0(%0)" : : "r"(addr) ); \
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290 } \
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291 HAL_DCACHE_ENABLE(); \
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292 }
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293
3111d98ba7b3 Initial commit of eCos version 1.1
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294 // Write dirty cache lines to memory for the given address range.
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295 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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296
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297 // Preread the given range into the cache with the intention of reading
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diff changeset
298 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1
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299 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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300
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
301 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
302 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1
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303 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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304
3111d98ba7b3 Initial commit of eCos version 1.1
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305 // Allocate and zero the cache lines associated with the given range.
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306 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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307
3111d98ba7b3 Initial commit of eCos version 1.1
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308 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
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309 // Global control of Instruction cache
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diff changeset
310
3111d98ba7b3 Initial commit of eCos version 1.1
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311 // Enable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
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312 #define HAL_ICACHE_ENABLE() \
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313 { \
3111d98ba7b3 Initial commit of eCos version 1.1
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314 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
315 "ori $2,$2,0x0020;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
316 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
317 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
318 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
319 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
320 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
321 \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
322 }
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
323
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
324 // Disable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
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325 #define HAL_ICACHE_DISABLE() \
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326 { \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
327 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
328 "la $3,0xFFFFFFDF;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
329 "and $2,$2,$3;" \
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diff changeset
330 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
331 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
332 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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333 : "$2", "$3" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
334 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
335 \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
336 }
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
337
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
338 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
339 #define HAL_ICACHE_INVALIDATE_ALL() \
3111d98ba7b3 Initial commit of eCos version 1.1
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340 { \
3111d98ba7b3 Initial commit of eCos version 1.1
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341 register CYG_ADDRESS addr; \
3111d98ba7b3 Initial commit of eCos version 1.1
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342 HAL_ICACHE_DISABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
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343 for( addr = 0; addr < HAL_ICACHE_SIZE; addr += HAL_ICACHE_LINE_SIZE ) \
3111d98ba7b3 Initial commit of eCos version 1.1
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344 { \
3111d98ba7b3 Initial commit of eCos version 1.1
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345 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
3111d98ba7b3 Initial commit of eCos version 1.1
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346 } \
3111d98ba7b3 Initial commit of eCos version 1.1
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347 HAL_ICACHE_ENABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
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348 }
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
349
3111d98ba7b3 Initial commit of eCos version 1.1
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350 // Synchronize the contents of the cache with memory.
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351 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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diff changeset
352
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353 // Set the instruction cache refill burst size
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354 //#define HAL_ICACHE_BURST_SIZE(_size_)
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355
3111d98ba7b3 Initial commit of eCos version 1.1
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356 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
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357 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1
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358 #define HAL_ICACHE_LOCK(_base_, _size_) \
3111d98ba7b3 Initial commit of eCos version 1.1
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359 { \
3111d98ba7b3 Initial commit of eCos version 1.1
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360 asm volatile ("mfc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
361 "ori $2,$2,0x0200;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
362 "mtc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
363 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
364 : \
3111d98ba7b3 Initial commit of eCos version 1.1
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365 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
366 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
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367 }
3111d98ba7b3 Initial commit of eCos version 1.1
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368
3111d98ba7b3 Initial commit of eCos version 1.1
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369 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1
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370 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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371 { \
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372 asm volatile ("mfc0 $2,$7;" \
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373 "la $3,0xFFFFFDFF;" \
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374 "and $2,$2,$3;" \
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375 "mtc0 $2,$7;" \
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376 : \
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377 : \
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378 : "$2", "$3" \
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379 ); \
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380 }
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381
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382 //-----------------------------------------------------------------------------
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383 // Instruction cache line control
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384
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385 // Invalidate cache lines in the given range without writing to memory.
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386 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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387 { \
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388 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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389 register CYG_WORD _size_ = (_asize_); \
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390 HAL_ICACHE_DISABLE(); \
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391 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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392 { \
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393 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
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394 } \
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395 HAL_ICACHE_ENABLE(); \
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396 }
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397
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398 #endif
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399
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400 //-----------------------------------------------------------------------------
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401 #endif // ifndef CYGONCE_HAL_CACHE_H
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402 // End of hal_cache.h