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annotate packages/hal/mips/arch/current/src/context.S @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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children 443894e2e912
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1 ##=============================================================================##
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2 ## context.S
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3 ##
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4 ## MIPS context switch code
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5 ##
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6 ##=============================================================================
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7 #####COPYRIGHTBEGIN####
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8 #
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9 # -------------------------------------------
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10 # The contents of this file are subject to the Cygnus eCos Public License
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11 # Version 1.0 (the "License"); you may not use this file except in
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12 # compliance with the License. You may obtain a copy of the License at
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13 # http://sourceware.cygnus.com/ecos
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14 #
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15 # Software distributed under the License is distributed on an "AS IS"
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16 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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17 # License for the specific language governing rights and limitations under
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18 # the License.
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19 #
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20 # The Original Code is eCos - Embedded Cygnus Operating System, released
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21 # September 30, 1998.
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22 #
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23 # The Initial Developer of the Original Code is Cygnus. Portions created
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24 # by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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25 # -------------------------------------------
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26 #
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27 #####COPYRIGHTEND####
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28 ##=============================================================================
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29 #######DESCRIPTIONBEGIN####
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30 ##
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31 ## Author(s): nickg
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32 ## Contributors: nickg
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33 ## Date: 1998-04-27
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34 ## Purpose: MIPS context switch code
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35 ## Description: This file contains implementations of the thread context
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36 ## switch routines. It also contains the longjmp() and setjmp()
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37 ## routines.
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38 ##
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39 ######DESCRIPTIONEND####
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40 ##
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41 ##=============================================================================
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42
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43 #include <pkgconf/hal.h>
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44
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45 #include <cyg/hal/mips.inc>
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46
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47 .set noat
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48
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49 #------------------------------------------------------------------------------
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50 # hal_thread_switch_context
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51 # Switch thread contexts
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52 # A0 = address of sp of next thread to execute
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53 # A1 = address of sp save location of current thread
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54
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55 .global hal_thread_switch_context
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56 hal_thread_switch_context:
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57
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58 addi sp,sp,-mipsreg_size # space for registers
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59
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60 # store GPRs
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61 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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62 sw $0,(mipsreg_regs+0*4)(sp)
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63 sw $1,(mipsreg_regs+1*4)(sp)
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64 sw $2,(mipsreg_regs+2*4)(sp)
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65 sw $3,(mipsreg_regs+3*4)(sp)
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66 sw $4,(mipsreg_regs+4*4)(sp)
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67 sw $5,(mipsreg_regs+5*4)(sp)
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68 sw $6,(mipsreg_regs+6*4)(sp)
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69 sw $7,(mipsreg_regs+7*4)(sp)
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70 sw $8,(mipsreg_regs+8*4)(sp)
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71 sw $9,(mipsreg_regs+9*4)(sp)
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72 sw $10,(mipsreg_regs+10*4)(sp)
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73 sw $11,(mipsreg_regs+11*4)(sp)
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74 sw $12,(mipsreg_regs+12*4)(sp)
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75 sw $13,(mipsreg_regs+13*4)(sp)
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76 sw $14,(mipsreg_regs+14*4)(sp)
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77 sw $15,(mipsreg_regs+15*4)(sp)
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78 sw $24,(mipsreg_regs+24*4)(sp)
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79 sw $25,(mipsreg_regs+25*4)(sp)
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80 sw $28,(mipsreg_regs+28*4)(sp) # == GP
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81 #endif
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82 sw $16,(mipsreg_regs+16*4)(sp)
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83 sw $17,(mipsreg_regs+17*4)(sp)
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84 sw $18,(mipsreg_regs+18*4)(sp)
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85 sw $19,(mipsreg_regs+19*4)(sp)
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86 sw $20,(mipsreg_regs+20*4)(sp)
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87 sw $21,(mipsreg_regs+21*4)(sp)
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88 sw $22,(mipsreg_regs+22*4)(sp)
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89 sw $23,(mipsreg_regs+23*4)(sp)
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90 # sw $26,(mipsreg_regs+26*4)(sp) # == K0
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91 # sw $27,(mipsreg_regs+27*4)(sp) # == K1
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92 # sw $29,(mipsreg_regs+29*4)(sp) # == SP
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93 sw $30,(mipsreg_regs+30*4)(sp) # == FP
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94 sw $31,(mipsreg_regs+31*4)(sp) # == RA
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95 sw $31,(mipsreg_pc)(sp) # == PC (to help with debugging)
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96
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97 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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98
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99 mflo t0 # save LO and HI regs
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100 mfhi t1
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101 sw t0,mipsreg_lo(sp)
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102 sw t1,mipsreg_hi(sp)
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103
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104 #endif
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105
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106 addi t0,sp,mipsreg_size # save SP in reg dump
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107 sw t0,(mipsreg_regs+29*4)(sp)
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108
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109 sw sp,0(a1) # save sp in save loc
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110
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111 # Now load the destination thread by dropping through
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112 # to hal_thread_load_context
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113
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114 #------------------------------------------------------------------------------
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115 # hal_thread_load_context
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116 # Load thread context
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117 # A0 = address of sp of next thread to execute
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118 # Note that this function is also the second half of hal_thread_switch_context
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119 # and is simply dropped into from it.
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120
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121 .global hal_thread_load_context
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122 hal_thread_load_context:
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123
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124 lw sp,0(a0) # load new SP directly
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125
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126 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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127
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128 lw t0,mipsreg_hi(sp) # load HI and LO regs
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129 lw t1,mipsreg_lo(sp)
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130 mthi t0
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131 mtlo t1
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132
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133 #endif
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134
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135 # load GPRs
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136 # lw $0,(mipsreg_regs+0*4)(sp)
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137 lw $4,(mipsreg_regs+4*4)(sp) # A0, must load for thread startup
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138 #ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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139 lw $1,(mipsreg_regs+1*4)(sp)
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140 lw $2,(mipsreg_regs+2*4)(sp)
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141 lw $3,(mipsreg_regs+3*4)(sp)
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142 lw $5,(mipsreg_regs+5*4)(sp)
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143 lw $6,(mipsreg_regs+6*4)(sp)
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144 lw $7,(mipsreg_regs+7*4)(sp)
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145 lw $8,(mipsreg_regs+8*4)(sp)
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146 lw $9,(mipsreg_regs+9*4)(sp)
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147 lw $10,(mipsreg_regs+10*4)(sp)
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148 lw $11,(mipsreg_regs+11*4)(sp)
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149 lw $12,(mipsreg_regs+12*4)(sp)
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150 lw $13,(mipsreg_regs+13*4)(sp)
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151 lw $14,(mipsreg_regs+14*4)(sp)
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152 lw $15,(mipsreg_regs+15*4)(sp)
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153 lw $24,(mipsreg_regs+24*4)(sp)
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154 lw $25,(mipsreg_regs+25*4)(sp)
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155 #endif
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156 lw $16,(mipsreg_regs+16*4)(sp)
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157 lw $17,(mipsreg_regs+17*4)(sp)
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158 lw $18,(mipsreg_regs+18*4)(sp)
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159 lw $19,(mipsreg_regs+19*4)(sp)
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160 lw $20,(mipsreg_regs+20*4)(sp)
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161 lw $21,(mipsreg_regs+21*4)(sp)
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162 lw $22,(mipsreg_regs+22*4)(sp)
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163 lw $23,(mipsreg_regs+23*4)(sp)
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164 # lw $26,(mipsreg_regs+26*4)(sp) # == K0
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165 # lw $27,(mipsreg_regs+27*4)(sp) # == K1
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166 # lw $28,(mipsreg_regs+28*4)(sp) # == GP
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167 # lw $29,(mipsreg_regs+29*4)(sp) # == SP
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168 lw $30,(mipsreg_regs+30*4)(sp) # == FP
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169 lw $31,(mipsreg_regs+31*4)(sp) # == RA
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170
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171 # Note that the following lw must go here and not
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172 # in the jr delay slot, since it has a delay slot
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173 # of its own.
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174 lw sp,(mipsreg_regs+29*4)(sp) # load SP
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175 jr ra # return via ra
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176 nop # delay slot - must be nop
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177
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178 #------------------------------------------------------------------------------
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179 # HAL longjmp, setjmp implementations
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180 # hal_setjmp saves only to callee save registers 13-31, r1[sp],r2
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181 # and lr into buffer supplied in r3[arg0]
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182
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183 .globl hal_setjmp
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184 .ent hal_setjmp
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185 hal_setjmp:
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186 sw $31,44(a0) # ra (link)
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187 sw $30,40(a0)
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188 sw $28,36(a0) # gp, optimize out?
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189 sw $23,32(a0)
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190 sw $22,28(a0)
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191 sw $21,24(a0)
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192 sw $20,20(a0)
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193 sw $19,16(a0)
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194 sw $18,12(a0)
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195 sw $17,8(a0)
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196 sw $16,4(a0)
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197 sw sp,0(a0) # $29
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198 li v0,0
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199 jr ra
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200 nop # delay slot
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201 .end hal_setjmp
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202
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203 .globl hal_longjmp
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204 .ent hal_longjmp
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205 hal_longjmp:
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206 lw $31,44(a0) # ra (link)
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207 lw $30,40(a0)
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208 lw $28,36(a0) # gp, optimize out?
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209 lw $23,32(a0)
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210 lw $22,28(a0)
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211 lw $21,24(a0)
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212 lw $20,20(a0)
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213 lw $19,16(a0)
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214 lw $18,12(a0)
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215 lw $17,8(a0)
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216 lw $16,4(a0)
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217 lw sp,0(a0) # $29
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218 move v0,a1
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219 jr ra
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220 nop # delay slot
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221 .end hal_longjmp
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222
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223
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224 #------------------------------------------------------------------------------
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225 # end of context.S
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226
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227