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1 //============================================================================= |
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2 // |
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3 // hal_misc.c |
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4 // |
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5 // HAL miscellaneous functions |
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6 // |
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7 //============================================================================= |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 // September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Cygnus. Portions created |
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25 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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26 // ------------------------------------------- |
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27 // |
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28 //####COPYRIGHTEND#### |
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29 //============================================================================= |
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30 //#####DESCRIPTIONBEGIN#### |
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31 // |
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32 // Author(s): nickg |
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33 // Contributors: nickg |
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34 // Date: 1998-02-05 |
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35 // Purpose: HAL miscellaneous functions |
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36 // Description: This file contains miscellaneous functions provided by the |
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37 // HAL. |
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38 // |
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39 //####DESCRIPTIONEND#### |
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40 // |
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41 //===========================================================================*/ |
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42 |
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43 #include <pkgconf/hal.h> |
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44 |
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45 #include <cyg/infra/cyg_type.h> // Base types |
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46 #include <cyg/infra/cyg_trac.h> // tracing macros |
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47 #include <cyg/infra/cyg_ass.h> // assertion macros |
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48 |
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49 #include <cyg/hal/hal_arch.h> // architectural definitions |
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50 |
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51 #include <cyg/hal/hal_intr.h> // Interrupt handling |
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52 |
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53 #include <cyg/hal/hal_cache.h> // Cache handling |
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54 |
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55 /*---------------------------------------------------------------------------*/ |
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56 /* First level C exception handler. */ |
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57 |
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58 externC void __handle_exception (void); |
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59 |
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60 externC HAL_SavedRegisters *_hal_registers; |
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61 |
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62 externC void exception_handler(HAL_SavedRegisters *regs) |
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63 { |
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64 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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65 |
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66 // Set the pointer to the registers of the current exception |
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67 // context. At entry the GDB stub will expand the |
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68 // HAL_SavedRegisters structure into a (bigger) register array. |
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69 _hal_registers = regs; |
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70 __handle_exception(); |
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71 |
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72 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS) |
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73 |
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74 // We should decode the vector and pass a more appropriate |
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75 // value as the second argument. For now we simply pass a |
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76 // pointer to the saved registers. We should also divert |
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77 // breakpoint and other debug vectors into the debug stubs. |
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78 |
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79 deliver_exception( regs->vector>>2, (CYG_ADDRWORD)regs ); |
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80 |
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81 #else |
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82 |
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83 CYG_FAIL("Exception!!!"); |
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84 |
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85 #endif |
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86 return; |
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87 } |
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88 |
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89 /*---------------------------------------------------------------------------*/ |
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90 /* default ISR */ |
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91 |
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92 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
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93 { |
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94 CYG_TRACE1(true, "Interrupt: %d", vector); |
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95 CYG_FAIL("Spurious Interrupt!!!"); |
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96 return 0; |
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97 } |
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98 |
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99 /*---------------------------------------------------------------------------*/ |
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100 /* data copy and bss zero functions */ |
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101 |
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102 typedef void (CYG_ROM_ADDRESS)(void); |
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103 |
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104 #ifdef CYG_HAL_STARTUP_ROM |
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105 void hal_copy_data(void) |
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106 { |
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107 extern char __ram_data_start; |
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108 extern char __ram_data_end; |
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109 extern CYG_ROM_ADDRESS __rom_data_start; |
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110 char *p = &__ram_data_start; |
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111 char *q = (char *)&__rom_data_start; |
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112 |
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113 while( p != (char *)&__ram_data_end ) |
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114 *p++ = *q++; |
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115 } |
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116 #endif |
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117 |
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118 void hal_zero_bss(void) |
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119 { |
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120 extern CYG_ROM_ADDRESS __bss_start; |
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121 extern CYG_ROM_ADDRESS _end; |
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122 char *p = (char *)&__bss_start; |
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123 |
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124 while( p != (char *)&_end ) |
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125 *p++ = 0; |
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126 } |
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127 |
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128 /*---------------------------------------------------------------------------*/ |
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129 |
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130 void fake_ctor(void) {}; |
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131 |
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132 void |
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133 cyg_hal_invoke_constructors (void) |
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134 { |
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135 #ifdef CYG_KERNEL_USE_INIT_PRIORITY |
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136 |
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137 typedef void (*pfunc) (void); |
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138 extern pfunc __CTOR_LIST__[]; |
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139 long i = (long)(__CTOR_LIST__[0]); |
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140 pfunc p; |
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141 |
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142 for ( ; i > 0; i-- ) |
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143 { |
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144 p = __CTOR_LIST__[i]; |
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145 p (); |
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146 } |
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147 |
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148 #else |
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149 |
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150 typedef void (CYG_CODE_ADDRESS)(); |
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151 extern CYG_CODE_ADDRESS __sched_text_start; |
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152 extern CYG_CODE_ADDRESS __sched_text_end; |
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153 extern CYG_CODE_ADDRESS __clock_text_start; |
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154 extern CYG_CODE_ADDRESS __clock_text_end; |
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155 extern CYG_CODE_ADDRESS __thread_text_start; |
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156 extern CYG_CODE_ADDRESS __thread_text_end; |
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157 |
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158 typedef void (*pfunc) (); |
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159 extern pfunc __CTOR_LIST__[]; |
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160 pfunc *p; |
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161 |
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162 for (p = __CTOR_LIST__+1; *p != 0; p++) |
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163 { |
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164 CYG_ADDRESS *pp = (CYG_ADDRESS *)*p; |
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165 |
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166 if( pp > (CYG_ADDRESS *)&__sched_text_start && |
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167 pp < (CYG_ADDRESS *)&__sched_text_end ) |
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168 { |
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169 (*p) (); |
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170 *p = fake_ctor; |
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171 } |
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172 } |
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173 |
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174 for (p = __CTOR_LIST__+1; *p != 0; p++) |
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175 { |
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176 CYG_ADDRESS *pp = (CYG_ADDRESS *)*p; |
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177 |
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178 if( pp > (CYG_ADDRESS *)&__clock_text_start && |
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179 pp < (CYG_ADDRESS *)&__clock_text_end ) |
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180 { |
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181 (*p) (); |
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182 *p = fake_ctor; |
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183 } |
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184 } |
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185 |
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186 for (p = __CTOR_LIST__+1; *p != 0; p++) |
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187 { |
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188 CYG_ADDRESS *pp = (CYG_ADDRESS *)*p; |
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189 |
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190 if( pp > (CYG_ADDRESS *)&__thread_text_start && |
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191 pp < (CYG_ADDRESS *)&__thread_text_end ) |
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192 { |
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193 (*p) (); |
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194 *p = fake_ctor; |
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195 } |
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196 } |
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197 |
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198 for (p = __CTOR_LIST__+1; *p != 0; p++) |
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199 { |
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200 (*p) (); |
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201 *p = fake_ctor; |
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202 } |
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203 |
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204 #endif |
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205 |
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206 #ifdef CYG_HAL_MIPS_TX3904 |
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207 |
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208 // On the real hardware we also enable the cache. |
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209 // doing this here is a temporary measure until we |
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210 // have a proper platform specific place to do it. |
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211 |
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212 HAL_ICACHE_INVALIDATE_ALL(); |
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213 HAL_ICACHE_ENABLE(); |
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214 HAL_DCACHE_INVALIDATE_ALL(); |
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215 HAL_DCACHE_ENABLE(); |
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216 |
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217 #endif |
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218 |
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219 #if defined(CYG_HAL_USE_ROM_MONITOR) && \ |
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220 !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ |
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221 defined(CYG_HAL_TX39_JMR3904) |
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222 |
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223 { |
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224 static void hal_init_ctrlc_intr(void); |
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225 hal_init_ctrlc_intr(); |
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226 } |
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227 |
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228 #endif |
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229 #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ |
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230 defined(CYG_HAL_USE_ROM_MONITOR) && \ |
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231 defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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232 { |
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233 extern void patch_dbg_syscalls(void * vector); |
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234 #define DBG_SYSCALL_VEC_NUM 15 |
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235 patch_dbg_syscalls( (void *)(&hal_vsr_table[DBG_SYSCALL_VEC_NUM]) ); |
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236 } |
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237 #endif |
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238 } |
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239 |
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240 /*---------------------------------------------------------------------------*/ |
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241 /* Determine the index of the ls bit of the supplied mask. */ |
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242 |
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243 cyg_uint32 hal_lsbit_index(cyg_uint32 mask) |
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244 { |
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245 cyg_uint32 n = mask; |
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246 |
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247 static const signed char tab[64] = |
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248 { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, |
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249 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, |
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250 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, |
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251 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 |
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252 }; |
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253 |
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254 n &= ~(n-1UL); |
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255 n = (n<<16)-n; |
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256 n = (n<<6)+n; |
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257 n = (n<<4)+n; |
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258 |
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259 return tab[n>>26]; |
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260 } |
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261 |
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262 /*---------------------------------------------------------------------------*/ |
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263 /* Determine the index of the ms bit of the supplied mask. */ |
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264 |
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265 cyg_uint32 hal_msbit_index(cyg_uint32 mask) |
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266 { |
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267 cyg_uint32 x = mask; |
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268 cyg_uint32 w; |
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269 |
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270 /* Phase 1: make word with all ones from that one to the right */ |
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271 x |= x >> 16; |
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272 x |= x >> 8; |
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273 x |= x >> 4; |
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274 x |= x >> 2; |
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275 x |= x >> 1; |
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276 |
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277 /* Phase 2: calculate number of "1" bits in the word */ |
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278 w = (x & 0x55555555) + ((x >> 1) & 0x55555555); |
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279 w = (w & 0x33333333) + ((w >> 2) & 0x33333333); |
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280 w = w + (w >> 4); |
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281 w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); |
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282 return (cyg_uint32)((w + (w >> 16)) & 0xFF); |
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283 |
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284 } |
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285 |
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286 /*---------------------------------------------------------------------------*/ |
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287 /* Idle thread action */ |
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288 |
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289 void hal_idle_thread_action( cyg_uint32 count ) |
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290 { |
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291 #if 0 //def CYG_HAL_MIPS_SIM |
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292 if( (count % 1000) == 0 ) |
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293 { |
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294 // This code causes a fake interrupt. |
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295 asm volatile ( |
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296 "xor $24,$24,$24;" |
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297 "mtc0 $24,$13;" |
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298 "lui $25,%%hi(1f);" |
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299 "ori $25,$25,%%lo(1f);" |
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300 "j other_vector;" |
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301 "nop;" |
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302 "1:" |
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303 : |
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304 : |
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305 : "t8", "t9" |
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306 ); |
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307 } |
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308 #endif |
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309 #if 0 //def CYG_HAL_MIPS_JMR3904 |
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310 |
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311 { |
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312 // cyg_uint32 tval, isr, imr, ilr; |
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313 cyg_uint32 sr, cr; |
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314 // HAL_CLOCK_READ( &tval ); |
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315 // HAL_READ_UINT32( 0xFFFFC000, isr ); |
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316 // HAL_READ_UINT32( 0xFFFFC004, imr ); |
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317 // HAL_READ_UINT32( 0xFFFFC01C, ilr ); |
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318 // CYG_TRACE2(1, "Timer value, ISR ",tval, isr); |
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319 // CYG_TRACE2(1, "IMR ILR0 ", imr, ilr); |
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320 |
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321 asm volatile ( |
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322 "mfc0 %0,$12;" |
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323 "mfc0 %1,$13;" |
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324 : "=r"(sr), "=r"(cr) |
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325 ); |
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326 |
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327 CYG_TRACE2(1, "Status Cause ", sr, cr); |
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328 |
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329 // if( count == 4 ) |
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330 // { |
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331 // HAL_ENABLE_INTERRUPTS(); |
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332 // } |
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333 |
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334 // if( count >= 10 ) |
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335 // for(;;); |
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336 } |
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337 #endif |
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338 } |
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339 |
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340 /*---------------------------------------------------------------------------*/ |
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341 /* This code installs an interrupt handler to capture Ctrl-C. */ |
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342 /* It's here for lack of anywhere more suitable to put it. */ |
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343 |
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344 #if defined(CYG_HAL_USE_ROM_MONITOR) && \ |
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345 !defined(CYGDBG_INFRA_DIAG_USE_DEVICE) && \ |
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346 defined(CYG_HAL_TX39_JMR3904) |
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347 |
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348 #define DIAG_BASE 0xfffff300 |
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349 #define DIAG_SLCR (DIAG_BASE+0x00) |
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350 #define DIAG_SLSR (DIAG_BASE+0x04) |
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351 #define DIAG_SLDICR (DIAG_BASE+0x08) |
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352 #define DIAG_SLDISR (DIAG_BASE+0x0C) |
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353 #define DIAG_SFCR (DIAG_BASE+0x10) |
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354 #define DIAG_SBRG (DIAG_BASE+0x14) |
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355 #define DIAG_TFIFO (DIAG_BASE+0x20) |
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356 #define DIAG_RFIFO (DIAG_BASE+0x30) |
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357 |
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358 #define BRG_T0 0x0000 |
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359 #define BRG_T2 0x0100 |
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360 #define BRG_T4 0x0200 |
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361 #define BRG_T5 0x0300 |
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362 |
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363 static cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
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364 { |
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365 char c; |
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366 CYG_WORD16 disr; |
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367 |
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368 HAL_READ_UINT16( DIAG_SLDISR , disr ); |
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369 |
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370 if( disr & 0x0001 ) |
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371 { |
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372 |
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373 disr = disr & ~0x0001; |
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374 |
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375 HAL_READ_UINT8( DIAG_RFIFO, c ); |
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376 |
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377 HAL_WRITE_UINT16( DIAG_SLDISR , disr ); |
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378 |
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379 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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380 if( c == 3 ) |
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381 { |
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382 // Ctrl-C: breakpoint. |
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383 extern void breakpoint(void); |
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384 breakpoint(); |
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385 } |
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386 #elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) |
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387 if( c == 3 ) |
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388 { |
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389 // Ctrl-C: breakpoint. |
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390 // HAL_BREAKPOINT(_breakinst); |
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391 typedef void bpt_fn(void); |
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392 bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; |
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393 |
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394 bfn(); |
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395 } |
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396 #elif defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) |
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397 if( c == 3 ) |
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398 { |
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399 // Ctrl-C: breakpoint. |
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400 HAL_BREAKPOINT(_breakinst1); |
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401 } |
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402 #endif |
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403 } |
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404 |
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405 return 0; |
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406 } |
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407 |
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408 |
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409 static void hal_init_ctrlc_intr(void) |
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410 { |
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411 CYG_WORD16 dicr; |
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412 |
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413 HAL_INTERRUPT_ATTACH( CYG_VECTOR_SIO_0, hal_ctrlc_isr, NULL, NULL ); |
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414 |
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415 HAL_INTERRUPT_UNMASK( CYG_VECTOR_SIO_0 ); |
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416 |
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417 HAL_READ_UINT16( DIAG_SLDICR , dicr ); |
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418 dicr = 0x0001; |
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419 HAL_WRITE_UINT16( DIAG_SLDICR , dicr ); |
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420 } |
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421 |
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422 #endif |
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423 |
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424 /*---------------------------------------------------------------------------*/ |
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425 /* End of hal_misc.c */ |
