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1 //========================================================================== |
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2 // |
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3 // intr/intr.cxx |
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4 // |
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5 // Interrupt class implementations |
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6 // |
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7 //========================================================================== |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 // September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Cygnus. Portions created |
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25 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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26 // ------------------------------------------- |
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27 // |
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28 //####COPYRIGHTEND#### |
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29 //========================================================================== |
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30 //#####DESCRIPTIONBEGIN#### |
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31 // |
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32 // Author(s): nickg |
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33 // Contributors: nickg |
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34 // Date: 1997-10-15 |
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35 // Purpose: Interrupt class implementation |
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36 // Description: This file contains the definitions of the interrupt |
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37 // class. |
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38 // |
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39 //####DESCRIPTIONEND#### |
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40 // |
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41 //========================================================================== |
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42 |
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43 #include <pkgconf/kernel.h> |
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44 |
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45 #include <cyg/kernel/ktypes.h> // base kernel types |
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46 #include <cyg/infra/cyg_trac.h> // tracing macros |
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47 #include <cyg/infra/cyg_ass.h> // assertion macros |
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48 #include <cyg/kernel/instrmnt.h> // instrumentation |
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49 |
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50 #include <cyg/kernel/intr.hxx> // our header |
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51 |
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52 #include <cyg/kernel/sched.hxx> // scheduler |
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53 |
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54 #include <cyg/kernel/sched.inl> |
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55 |
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56 // ------------------------------------------------------------------------- |
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57 |
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58 Cyg_Interrupt::Cyg_Interrupt( |
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59 cyg_vector vec, // Vector to attach to |
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60 cyg_priority pri, // Queue priority |
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61 CYG_ADDRWORD d, // Data pointer |
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62 cyg_ISR *ir, // Interrupt Service Routine |
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63 cyg_DSR *dr // Deferred Service Routine |
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64 ) |
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65 { |
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66 vector = vec; |
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67 priority = pri; |
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68 isr = ir; |
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69 dsr = dr; |
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70 data = d; |
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71 |
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72 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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73 |
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74 dsr_count = 0; |
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75 next_dsr = NULL; |
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76 |
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77 #endif |
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78 |
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79 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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80 |
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81 next = NULL; |
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82 |
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83 #endif |
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84 |
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85 }; |
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86 |
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87 // ------------------------------------------------------------------------- |
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88 |
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89 Cyg_Interrupt::~Cyg_Interrupt() |
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90 { |
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91 detach(); |
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92 }; |
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93 |
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94 // ------------------------------------------------------------------------- |
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95 // DSR handling statics: |
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96 |
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97 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
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98 |
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99 Cyg_Interrupt *Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; |
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100 |
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101 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; |
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102 |
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103 cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; |
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104 |
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105 #endif |
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106 |
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107 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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108 |
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109 Cyg_Interrupt *Cyg_Interrupt::dsr_list = NULL; |
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110 |
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111 #endif |
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112 |
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113 // ------------------------------------------------------------------------- |
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114 // Call any pending DSRs |
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115 |
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116 void Cyg_Interrupt::call_pending_DSRs() |
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117 { |
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118 // CYG_REPORT_FUNCTION(); |
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119 |
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120 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
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121 |
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122 while( dsr_table_head != dsr_table_tail ) |
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123 { |
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124 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; |
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125 |
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126 dsr_table_head++; |
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127 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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128 dsr_table_head = 0; |
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129 |
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130 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); |
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131 |
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132 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
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133 } |
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134 |
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135 #endif |
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136 |
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137 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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138 |
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139 while( dsr_list != NULL ) |
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140 { |
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141 Cyg_Interrupt *intr; |
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142 cyg_uint32 old_intr; |
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143 cyg_count32 count; |
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144 |
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145 HAL_DISABLE_INTERRUPTS(old_intr); |
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146 |
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147 intr = dsr_list; |
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148 dsr_list = intr->next_dsr; |
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149 count = intr->dsr_count; |
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150 intr->dsr_count = 0; |
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151 |
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152 HAL_RESTORE_INTERRUPTS(old_intr); |
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153 |
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154 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); |
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155 |
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156 } |
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157 |
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158 #endif |
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159 |
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160 }; |
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161 |
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162 // ------------------------------------------------------------------------- |
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163 |
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164 void Cyg_Interrupt::post_dsr() |
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165 { |
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166 // CYG_REPORT_FUNCTION(); |
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167 |
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168 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); |
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169 |
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170 cyg_uint32 old_intr; |
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171 |
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172 // We need to disable interrupts during this part to |
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173 // guard against nested interrupts. |
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174 |
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175 HAL_DISABLE_INTERRUPTS(old_intr); |
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176 |
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177 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
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178 |
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179 dsr_table[dsr_table_tail++] = this; |
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180 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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181 dsr_table_tail = 0; |
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182 |
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183 #endif |
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184 |
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185 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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186 |
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187 // Only add the interrupt to the dsr list if this is |
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188 // the first DSR call. |
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189 // At present DSRs are pushed onto the list and will be |
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190 // called in reverse order. We do not define the order |
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191 // in which DSRs are called, so this is acceptable. |
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192 |
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193 if( dsr_count++ == 0 ) |
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194 { |
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195 next_dsr = dsr_list; |
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196 dsr_list = this; |
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197 } |
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198 |
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199 #endif |
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200 |
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201 HAL_RESTORE_INTERRUPTS(old_intr); |
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202 }; |
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203 |
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204 // ------------------------------------------------------------------------- |
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205 |
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206 externC void interrupt_end( |
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207 cyg_uint32 isr_ret, |
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208 Cyg_Interrupt *intr, |
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209 HAL_SavedRegisters *regs |
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210 ) |
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211 { |
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212 // CYG_REPORT_FUNCTION(); |
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213 |
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214 CYG_INSTRUMENT_INTR(END, intr->vector, isr_ret); |
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215 |
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216 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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217 |
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218 // Only do this if we are in a non-chained configuration. |
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219 // If we are chained, then chain_isr below will do the DSR |
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220 // posting. |
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221 |
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222 if( isr_ret & 2 ) intr->post_dsr(); |
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223 |
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224 #endif |
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225 |
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226 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT |
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227 |
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228 // If we have GDB support enabled, and there is the possibility |
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229 // that this thread will be context switched as a result of this |
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230 // interrupt, then save the pointer to the saved thread context in |
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231 // the thread object so that GDB can get a meaningful context to |
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232 // look at. |
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233 |
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234 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); |
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235 |
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236 #endif |
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237 |
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238 // Now unlock the scheduler, which may also call DSRs |
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239 // and cause a thread switch to happen. |
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240 |
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241 Cyg_Scheduler::unlock(); |
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242 |
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243 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT |
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244 |
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245 Cyg_Scheduler::get_current_thread()->set_saved_context(0); |
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246 |
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247 #endif |
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248 |
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249 |
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250 CYG_INSTRUMENT_INTR(RESTORE, intr->vector, 0); |
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251 } |
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252 |
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253 // ------------------------------------------------------------------------- |
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254 // Interrupt chaining statics. |
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255 |
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256 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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257 |
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258 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYG_ISR_COUNT]; |
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259 |
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260 #endif |
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261 |
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262 // ------------------------------------------------------------------------- |
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263 // Chaining ISR inserted in HAL vector |
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264 |
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265 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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266 |
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267 cyg_uint32 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) |
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268 { |
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269 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; |
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270 |
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271 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
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272 |
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273 while( p != NULL ) |
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274 { |
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275 if( p->vector == vector ) |
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276 { |
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277 register cyg_uint32 isr_ret = p->isr(vector, p->data); |
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278 |
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279 if( isr_ret & 2 ) p->post_dsr(); |
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280 |
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281 if( isr_ret & 1 ) break; |
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282 } |
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283 |
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284 p = p->next; |
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285 } |
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286 |
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287 return 0; |
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288 } |
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289 |
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290 #endif |
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291 |
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292 // ------------------------------------------------------------------------- |
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293 // Attach an ISR to an interrupt vector. |
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294 |
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295 void Cyg_Interrupt::attach() |
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296 { |
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297 CYG_REPORT_FUNCTION(); |
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298 |
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299 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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300 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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301 |
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302 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); |
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303 |
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304 HAL_INTERRUPT_SET_LEVEL( vector, priority ); |
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305 |
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306 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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307 |
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308 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); |
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309 |
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310 cyg_uint32 index; |
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311 |
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312 HAL_TRANSLATE_VECTOR( vector, index ); |
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313 |
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314 if( chain_list[index] == NULL ) |
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315 { |
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316 // First Interrupt on this chain, just assign it and register |
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317 // the chain_isr with the HAL. |
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318 |
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319 chain_list[index] = this; |
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320 |
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321 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
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322 } |
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323 else |
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324 { |
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325 // There are already interrupts chained, add this one into the |
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326 // chain in priority order. |
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327 |
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328 Cyg_Interrupt **p = &chain_list[index]; |
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329 |
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330 while( *p != NULL ) |
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331 { |
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332 Cyg_Interrupt *n = *p; |
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333 |
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334 if( n->priority < priority ) break; |
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335 |
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336 p = &n->next; |
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337 } |
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338 next = *p; |
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339 *p = this; |
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340 } |
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341 |
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342 #else |
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343 |
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344 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); |
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345 |
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346 #endif |
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347 } |
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348 |
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349 // ------------------------------------------------------------------------- |
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350 // Detach the ISR from the vector |
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351 |
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352 void Cyg_Interrupt::detach() |
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353 { |
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354 CYG_REPORT_FUNCTION(); |
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355 |
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356 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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357 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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358 |
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359 CYG_INSTRUMENT_INTR(DETACH, vector, 0); |
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360 |
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361 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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362 |
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363 // Remove the interrupt object from the vector chain. |
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364 |
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365 Cyg_Interrupt **p = &chain_list[vector]; |
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366 |
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367 while( *p != NULL ) |
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368 { |
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369 Cyg_Interrupt *n = *p; |
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370 |
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371 if( n == this ) |
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372 { |
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373 *p = next; |
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374 break; |
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375 } |
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376 |
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377 p = &n->next; |
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378 } |
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379 |
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380 // If this was the last one, detach the vector. |
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381 |
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382 if( chain_list[vector] == NULL ) |
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383 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
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384 |
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385 #else |
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386 |
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387 HAL_INTERRUPT_DETACH( vector, isr ); |
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388 |
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389 #endif |
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390 |
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391 } |
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392 |
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393 // ------------------------------------------------------------------------- |
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394 // Get the current service routine |
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395 |
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396 void Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) |
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397 { |
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398 CYG_REPORT_FUNCTION(); |
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399 |
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400 CYG_ASSERT( vector >= CYG_VSR_MIN, "Invalid vector"); |
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401 CYG_ASSERT( vector <= CYG_VSR_MAX, "Invalid vector"); |
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402 |
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403 HAL_VSR_GET( vector, vsr ); |
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404 } |
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405 |
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406 // ------------------------------------------------------------------------- |
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407 // Install a vector service routine |
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408 |
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409 void Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) |
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410 { |
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411 CYG_REPORT_FUNCTION(); |
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412 |
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413 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
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414 |
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415 CYG_ASSERT( vector >= CYG_VSR_MIN, "Invalid vector"); |
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416 CYG_ASSERT( vector <= CYG_VSR_MAX, "Invalid vector"); |
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417 |
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418 CYG_INTERRUPT_STATE old_ints; |
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419 |
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420 HAL_DISABLE_INTERRUPTS(old_ints); |
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421 |
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422 HAL_VSR_SET( vector, vsr, old ); |
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423 |
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424 HAL_RESTORE_INTERRUPTS(old_ints); |
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425 } |
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426 |
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427 // ------------------------------------------------------------------------- |
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428 // Disable interrupts at the CPU |
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429 |
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430 |
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431 void Cyg_Interrupt::disable_interrupts() |
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432 { |
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433 CYG_REPORT_FUNCTION(); |
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434 |
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435 CYG_INSTRUMENT_INTR(DISABLE, 0, 0); |
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436 |
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437 CYG_INTERRUPT_STATE dummy; |
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438 |
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439 HAL_DISABLE_INTERRUPTS(dummy); |
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440 |
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441 // Keep a disable level counter?? |
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442 } |
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443 |
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444 |
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445 // ------------------------------------------------------------------------- |
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446 // Re-enable CPU interrupts |
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447 |
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448 void Cyg_Interrupt::enable_interrupts() |
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449 { |
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450 CYG_REPORT_FUNCTION(); |
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451 |
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452 CYG_INSTRUMENT_INTR(ENABLE, 0, 0); |
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453 |
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454 HAL_ENABLE_INTERRUPTS(); |
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455 } |
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456 |
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457 // ------------------------------------------------------------------------- |
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458 // Mask a specific interrupt in a PIC |
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459 |
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460 void Cyg_Interrupt::mask_interrupt(cyg_vector vector) |
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461 { |
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462 CYG_REPORT_FUNCTION(); |
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463 |
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464 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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465 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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466 |
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467 CYG_INSTRUMENT_INTR(MASK, vector, 0); |
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468 |
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469 HAL_INTERRUPT_MASK( vector ) |
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470 } |
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471 |
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472 // ------------------------------------------------------------------------- |
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473 // Clear PIC mask |
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474 |
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475 void Cyg_Interrupt::unmask_interrupt(cyg_vector vector) |
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476 { |
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477 CYG_REPORT_FUNCTION(); |
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478 |
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479 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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480 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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481 |
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482 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); |
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483 |
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484 HAL_INTERRUPT_UNMASK( vector ); |
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485 } |
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486 |
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487 |
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488 // ------------------------------------------------------------------------- |
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489 // Acknowledge interrupt at PIC |
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490 |
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491 void Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) |
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492 { |
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493 // CYG_REPORT_FUNCTION(); |
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494 |
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495 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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496 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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497 |
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498 CYG_INSTRUMENT_INTR(ACK, vector, 0); |
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499 |
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500 HAL_INTERRUPT_ACKNOWLEDGE( vector ); |
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501 } |
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502 |
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503 // ------------------------------------------------------------------------- |
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504 // Change interrupt detection at PIC |
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505 |
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506 void Cyg_Interrupt::configure_interrupt( |
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507 cyg_vector vector, // vector to control |
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508 cyg_bool level, // level or edge triggered |
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509 cyg_bool up // hi/lo level, rising/falling edge |
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510 ) |
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511 { |
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512 CYG_REPORT_FUNCTION(); |
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513 |
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514 CYG_ASSERT( vector >= CYG_ISR_MIN, "Invalid vector"); |
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515 CYG_ASSERT( vector <= CYG_ISR_MAX, "Invalid vector"); |
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516 |
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517 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); |
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518 |
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519 HAL_INTERRUPT_CONFIGURE( vector, level, up ); |
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520 } |
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521 |
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522 // ------------------------------------------------------------------------- |
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523 // EOF intr/intr.cxx |
