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annotate packages/hal/arm/ebsa285/current/include/hal_cache.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children 6b5f480c6929
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): hmt
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38 // Contributors:hmt
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39 // Date: 1999-07-05
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/hal_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <cyg/infra/cyg_type.h>
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53 //#include <cyg/hal/hal_mmu.h>
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54
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55 //-----------------------------------------------------------------------------
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56 // Cache dimensions
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57
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58 #define HAL_DCACHE_SIZE 0x4000 // Size of data cache in bytes
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59 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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60 #define HAL_DCACHE_WAYS 32 // Associativity of the cache
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61 #define HAL_DCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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62
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63 #define HAL_ICACHE_SIZE 0x4000 // Size of instruction cache in bytes
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64 #define HAL_ICACHE_LINE_SIZE 32 // Size of ins cache line
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65 #define HAL_ICACHE_WAYS 32 // Associativity of the cache
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66 #define HAL_ICACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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67
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68 //-----------------------------------------------------------------------------
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69 // Global control of data cache
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70
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71 // Enable the data cache
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72 #define HAL_DCACHE_ENABLE() \
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73 CYG_MACRO_START \
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74 /* SA-110 manual states that the control reg is read-write */ \
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75 asm volatile ( \
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76 "mrc p15,0,r1,c1,c0,0;" \
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77 "orr r1,r1,#0x000F;" /* ensure MM is enabled */ \
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78 "mcr p15,0,r1,c1,c0,0" \
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79 : \
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80 : \
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81 : "r1" /* Clobber list */ \
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82 ); \
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83 CYG_MACRO_END
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84
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85 // Disable the data cache (and invalidate it, required semanitcs)
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86 #define HAL_DCACHE_DISABLE() \
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87 CYG_MACRO_START \
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88 /* SA-110 manual states that the control reg is read-write */ \
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89 asm volatile ( \
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90 "mrc p15,0,r1,c1,c0,0;" \
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91 "bic r1,r1,#0x000C;" /* but leave MM alone */ \
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92 "mcr p15,0,r1,c1,c0,0;" \
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93 "mov r1, #0;" \
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94 "mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
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95 : \
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96 : \
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97 : "r1" /* Clobber list */ \
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98 ); \
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99 CYG_MACRO_END
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100
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101 // Invalidate the entire cache (and both TLBs, just in case)
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102 #define HAL_DCACHE_INVALIDATE_ALL() \
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103 CYG_MACRO_START \
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104 /* this macro can discard dirty cache lines. */ \
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105 asm volatile ( \
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106 "mov r1, #0;" \
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107 "mcr p15,0,r1,c7,c6,0;" /* clear data cache */ \
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108 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
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109 : \
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110 : \
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111 : "r1" /* Clobber list */ \
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112 ); \
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113 CYG_MACRO_END
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114
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115
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116 // Synchronize the contents of the cache with memory.
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117 #define HAL_DCACHE_SYNC() \
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118 CYG_MACRO_START \
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119 /* This is slightly naff in that the only way to force a dirty */ \
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120 /* line out is by loading other data into its slot, so */ \
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121 /* invalidating that slot. */ \
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122 asm volatile ( \
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123 "mov r0, #0x50000000;" /* 21285~s cache flush region */ \
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124 "add r1, r0, #0x4000;" /* 16MB of fast don~t-care amnesia */ \
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125 "667: " /* We read in 16kB of it */ \
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126 "ldr r2, [r0], #32;" \
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127 "teq r1, r0;" \
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128 "bne 667b;" \
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129 "mov r0, #0;" \
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130 "mcr p15,0,r0,c7,c6,0;" /* clear data cache */ \
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131 "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
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132 "nop;" /* wait for the writethrough to occur... */ \
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133 "nop;" \
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134 "nop;" \
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135 "nop;" \
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136 "nop;" \
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137 "nop" \
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138 : \
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139 : \
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140 : "r0","r1","r2" /* Clobber list */ \
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141 ); \
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142 CYG_MACRO_END
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143
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144 // Query the state of the data cache
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145 #define HAL_DCACHE_IS_ENABLED(_state_) \
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146 CYG_MACRO_START \
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147 /* SA-110 manual states clearly that the control reg is readable */ \
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148 register int reg; \
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149 asm volatile ("mrc p15,0,%0,c1,c0,0" \
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150 : "=r"(reg) \
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151 : \
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152 /*:*/ \
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153 ); \
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154 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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155 CYG_MACRO_END
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156
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157 // Set the data cache refill burst size
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158 //#define HAL_DCACHE_BURST_SIZE(_size_)
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159
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160 // Set the data cache write mode
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161 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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162
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163 #define HAL_DCACHE_WRITETHRU_MODE 0
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164 #define HAL_DCACHE_WRITEBACK_MODE 1
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165
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166 // Get the current writeback mode - or only writeback mode if fixed
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167 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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168 _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
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169 CYG_MACRO_END
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170
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171 // Load the contents of the given address range into the data cache
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172 // and then lock the cache so that it stays there.
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173 //#define HAL_DCACHE_LOCK(_base_, _size_)
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174
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175 // Undo a previous lock operation
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176 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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177
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178 // Unlock entire cache
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179 //#define HAL_DCACHE_UNLOCK_ALL()
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180
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181 //-----------------------------------------------------------------------------
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182 // Data cache line control
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183
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184 // Allocate cache lines for the given address range without reading its
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185 // contents from memory.
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186 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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187
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188 // Write dirty cache lines to memory and invalidate the cache entries
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189 // for the given address range.
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190 // ---- this seems not to work despite the documentation ---
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191 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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192 //CYG_MACRO_START
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193 // HAL_DCACHE_STORE( _base_ , _size_ );
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194 // HAL_DCACHE_INVALIDATE( _base_ , _size_ );
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195 //CYG_MACRO_END
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196
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197 // Invalidate cache lines in the given range without writing to memory.
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198 // ---- this seems not to work despite the documentation ---
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199 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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200 //CYG_MACRO_START
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201 // register int addr, enda;
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202 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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203 // enda = (int)(_base_) + (_size_);
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204 // addr < enda ;
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205 // addr += HAL_DCACHE_LINE_SIZE )
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206 // {
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207 // asm volatile (
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208 // "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
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209 // :
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210 // : "r"(addr)
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211 // : "memory"
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212 // );
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213 // }
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214 //CYG_MACRO_END
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215
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216 // Write dirty cache lines to memory for the given address range.
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217 // ---- this seems not to work despite the documentation ---
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218 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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219 //CYG_MACRO_START
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220 // register int addr, enda;
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221 // for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
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222 // enda = (int)(_base_) + (_size_);
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223 // addr < enda ;
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224 // addr += HAL_DCACHE_LINE_SIZE )
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225 // {
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226 // asm volatile ("mcr p15,0,%0,c7,c10,1" /* push entry to RAM */
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227 // :
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228 // : "r"(addr)
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229 // : "memory"
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230 // );
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231 // }
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232 //CYG_MACRO_END
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233
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234
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235 // Preread the given range into the cache with the intention of reading
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236 // from it later.
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237 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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238
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239 // Preread the given range into the cache with the intention of writing
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240 // to it later.
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241 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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242
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243 // Allocate and zero the cache lines associated with the given range.
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244 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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245
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246 //-----------------------------------------------------------------------------
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247 // Global control of Instruction cache
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248
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249 // Enable the instruction cache
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250 #define HAL_ICACHE_ENABLE() \
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251 CYG_MACRO_START \
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252 /* SA-110 manual states that the control reg is read-write */ \
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253 asm volatile ( \
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254 "mrc p15,0,r1,c1,c0,0;" \
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255 "orr r1,r1,#0x0003;" /* ensure MM is enabled */ \
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256 "orr r1,r1,#0x1000;" /* enable ICache */ \
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257 "mcr p15,0,r1,c1,c0,0" \
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258 : \
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259 : \
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260 : "r1" /* Clobber list */ \
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261 ); \
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262 CYG_MACRO_END
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263
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264 // Disable the instruction cache (and invalidate it, required semanitcs)
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265 #define HAL_ICACHE_DISABLE() \
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266 CYG_MACRO_START \
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267 /* SA-110 manual states that the control reg is read-write */ \
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268 asm volatile ( \
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269 "mrc p15,0,r1,c1,c0,0;" \
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270 "bic r1,r1,#0x1000;" /* but leave MM alone */ \
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271 "mcr p15,0,r1,c1,c0,0;" \
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272 "mov r1, #0;" \
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273 "mcr p15,0,r1,c7,c5,0;" /* clear instruction cache */ \
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274 "nop;" /* next few instructions may be via cache */ \
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275 "nop;" \
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276 "nop;" \
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277 "nop;" \
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278 "nop;" \
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279 "nop" \
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280 : \
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281 : \
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282 : "r1" /* Clobber list */ \
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283 ); \
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284 CYG_MACRO_END
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285
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286 // Invalidate the entire cache
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287 #define HAL_ICACHE_INVALIDATE_ALL() \
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288 CYG_MACRO_START \
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289 /* this macro can discard dirty cache lines (N/A for ICache) */ \
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290 asm volatile ( \
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291 "mov r1, #0;" \
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292 "mcr p15,0,r1,c7,c5,0;" /* clear instruction cache */ \
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293 "mcr p15,0,r1,c8,c5,0;" /* flush I TLB only */ \
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294 "nop;" /* next few instructions may be via cache */ \
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295 "nop;" \
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296 "nop;" \
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297 "nop;" \
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298 "nop;" \
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299 "nop" \
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300 : \
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301 : \
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302 : "r1" /* Clobber list */ \
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303 ); \
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304 CYG_MACRO_END
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305
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306
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307 // Synchronize the contents of the cache with memory.
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308 // (which includes flushing out pending writes)
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309 #define HAL_ICACHE_SYNC() \
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310 CYG_MACRO_START \
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311 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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312 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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313 CYG_MACRO_END
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314
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315 // Query the state of the instruction cache
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316 #define HAL_ICACHE_IS_ENABLED(_state_) \
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317 CYG_MACRO_START \
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318 /* SA-110 manual states clearly that the control reg is readable */ \
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319 register cyg_uint32 reg; \
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320 asm volatile ("mrc p15,0,%0,c1,c0,0" \
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321 : "=r"(reg) \
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322 : \
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323 /*:*/ \
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324 ); \
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325 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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326 CYG_MACRO_END
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327
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328 // Set the instruction cache refill burst size
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329 //#define HAL_ICACHE_BURST_SIZE(_size_)
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330
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331 // Load the contents of the given address range into the instruction cache
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332 // and then lock the cache so that it stays there.
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333 //#define HAL_ICACHE_LOCK(_base_, _size_)
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334
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335 // Undo a previous lock operation
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336 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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337
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338 // Unlock entire cache
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339 //#define HAL_ICACHE_UNLOCK_ALL()
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340
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341 //-----------------------------------------------------------------------------
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342 // Instruction cache line control
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343
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344 // Invalidate cache lines in the given range without writing to memory.
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345 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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346
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347 //-----------------------------------------------------------------------------
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348 #endif // ifndef CYGONCE_HAL_CACHE_H
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349 // End of hal_cache.h