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annotate packages/hal/arm/ebsa285/current/src/ebsa285_misc.c @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children 84e4bde58b26
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1 //==========================================================================
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2 //
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3 // ebsa285_misc.c
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4 //
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5 // HAL misc board support code for StrongARM EBSA285-1
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-02-20
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37 // Purpose: HAL board support
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38 // Description: Implementations of HAL board interfaces
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/system.h>
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46 #include CYGBLD_HAL_PLATFORM_H
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47
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48 #include <cyg/infra/cyg_type.h> // base types
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49 #include <cyg/infra/cyg_trac.h> // tracing macros
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50 #include <cyg/infra/cyg_ass.h> // assertion macros
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51
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52 #include <cyg/hal/hal_io.h> // IO macros
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53 #include <cyg/hal/hal_arch.h> // Register state info
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54 #include <cyg/hal/hal_diag.h>
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55 #include <cyg/hal/hal_intr.h> // Interrupt names
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56 #include <cyg/hal/hal_cache.h>
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57 #include <cyg/hal/hal_ebsa285.h> // Hardware definitions
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58
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59 #include <cyg/infra/diag.h> // diag_printf
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60
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61 /*
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62 * Toggle LED for debugging purposes.
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63 */
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64 /*
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65 * EBSA-285 Soft I/O Register
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66 */
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67 #define EBSA_285_SOFT_IO_REGISTER ((cyg_uint32 *)0x40012000)
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68
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69 /*
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70 * EBSA-285 Soft I/O Register Bit Field definitions
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71 */
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72 #define EBSA_285_SOFT_IO_TOGGLE 0x80
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73 #define EBSA_285_SOFT_IO_RED_LED 0x04
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74 #define EBSA_285_SOFT_IO_GREEN_LED 0x02
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75 #define EBSA_285_SOFT_IO_AMBER_LED 0x01
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76 #define EBSA_285_SOFT_IO_J9_9_10_MASK 0x40
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77 #define EBSA_285_SOFT_IO_J9_11_12_MASK 0x20
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78 #define EBSA_285_SOFT_IO_J9_13_14_MASK 0x10
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79 #define EBSA_285_SOFT_IO_SWITCH_L_MASK 0x0F
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80
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81 static void
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82 hal_bsp_mmu_init(int sdram_size);
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83
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84 // Some initialization has already been done before we get here.
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85 //
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86 // Set up the interrupt environment.
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87 // Set up the MMU so that we can use caches.
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88 // Enable caches.
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89 // - All done!
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90
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91
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92 void hal_hardware_init(void)
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93 {
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94 // Disable all interrupt sources:
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95 *SA110_IRQCONT_IRQENABLECLEAR = 0xffffffff;
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96 *SA110_IRQCONT_FIQENABLECLEAR = 0xffffffff; // including FIQ
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97 // Disable the timers
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98 *SA110_TIMER1_CONTROL = 0;
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99 *SA110_TIMER2_CONTROL = 0;
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100 *SA110_TIMER3_CONTROL = 0;
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101 *SA110_TIMER4_CONTROL = 0;
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102
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103 *SA110_TIMER1_CLEAR = 0; // Clear any pending interrupt
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104 *SA110_TIMER2_CLEAR = 0; // (Data: don't care)
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105 *SA110_TIMER3_CLEAR = 0;
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106 *SA110_TIMER4_CLEAR = 0;
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107
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108 // Set up MMU so that we can use caches
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109 hal_bsp_mmu_init( hal_dram_size );
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110
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111 // Enable caches
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112 HAL_DCACHE_ENABLE();
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113 HAL_ICACHE_ENABLE();
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114
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115 #ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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116 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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117 // then enable the interrupt for incoming characters and break
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118 // into the stub ROM if the char is a ^C.
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119 HAL_INTERRUPT_UNMASK( CYG_DIAG_DEV_INT );
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120 // hal_diag.c: hal_ctrlc_isr( CYG_ADDRWORD vector, CYG_ADDRWORD data)
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121 // is polled from the default ISR so it's OK just to enable this.
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122 #endif
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123 #endif
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124 }
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125
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126 // -------------------------------------------------------------------------
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127 // MMU initialization:
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128
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129 static void
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130 hal_bsp_mmu_init(int sdram_size)
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131 {
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132 unsigned long ttb_base = ((unsigned long)0x4000); // could be external
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133 unsigned long i;
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134
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135 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_RED_LED; // Red LED on
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136
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137
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138 // For if we assign the ttb base dynamically:
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139 // if ((ttb_base & ARM_TRANSLATION_TABLE_MASK) != ttb_base) {
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140 // // we cannot do this:
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141 // while ( 1 ) {
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142 // *EBSA_285_SOFT_IO_REGISTER = 0; // All LEDs on
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143 // for ( i = 100000; i > 0 ; i++ ) ;
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144 // *EBSA_285_SOFT_IO_REGISTER = 7; // All LEDs off
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145 // for ( i = 100000; i > 0 ; i++ ) ;
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146 //#ifdef CYG_HAL_STARTUP_RAM
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147 // return; // Do not bother looping forever...
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148 //#endif
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149 // }
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150 // }
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151
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152 /*
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153 * Set the TTB register
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154 */
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155 asm volatile ("mcr p15,0,%0,c2,c0,0"
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156 :
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157 : "r"(ttb_base)
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158 /*:*/
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159 );
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160 /*
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161 * Set the Domain Access Control Register
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162 */
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163 i = ARM_ACCESS_TYPE_MANAGER(0) |
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164 ARM_ACCESS_TYPE_NO_ACCESS(1) |
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165 ARM_ACCESS_TYPE_NO_ACCESS(2) |
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166 ARM_ACCESS_TYPE_NO_ACCESS(3) |
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167 ARM_ACCESS_TYPE_NO_ACCESS(4) |
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168 ARM_ACCESS_TYPE_NO_ACCESS(5) |
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169 ARM_ACCESS_TYPE_NO_ACCESS(6) |
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170 ARM_ACCESS_TYPE_NO_ACCESS(7) |
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171 ARM_ACCESS_TYPE_NO_ACCESS(8) |
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172 ARM_ACCESS_TYPE_NO_ACCESS(9) |
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173 ARM_ACCESS_TYPE_NO_ACCESS(10) |
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174 ARM_ACCESS_TYPE_NO_ACCESS(11) |
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175 ARM_ACCESS_TYPE_NO_ACCESS(12) |
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176 ARM_ACCESS_TYPE_NO_ACCESS(13) |
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177 ARM_ACCESS_TYPE_NO_ACCESS(14) |
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178 ARM_ACCESS_TYPE_NO_ACCESS(15);
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179
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180 asm volatile ("mcr p15,0,%0,c3,c0,0"
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181 :
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182 : "r"(i)
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183 /*:*/
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184 );
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185
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186 /*
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187 * First clear all TT entries - ie Set them to Faulting
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188 */
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189 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
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190
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191 /*
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192 * We only do direct mapping for the EBSA board. That is, all
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193 * virt_addr == phys_addr.
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194 */
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195
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196 /*
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197 * Actual Base = 0x000(00000)
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198 * Virtual Base = 0x000(00000)
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199 * Size = Max SDRAM
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200 * SDRAM
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201 */
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202 for (i = 0x000; i < (sdram_size >> 20); i++) {
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203 ARM_MMU_SECTION(ttb_base, i, i,
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204 ARM_CACHEABLE, ARM_BUFFERABLE,
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205 ARM_ACCESS_PERM_RW_RW);
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206 }
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207
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208 #ifdef CYGPKG_IO_PCI
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209 /*
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210 * Actual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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211 * Virtual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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212 * Size = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE
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213 * Memory accessible from PCI space. Overrides part of the above mapping.
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214 */
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215 for (i = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE >> 20;
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216 i < ((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE+CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE) >> 20);
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217 i++) {
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218 ARM_MMU_SECTION(ttb_base, i, i,
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219 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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220 ARM_ACCESS_PERM_RW_RW);
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221 }
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222 #endif
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223
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224 /*
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225 * Actual Base = 0x400(00000)
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226 * Virtual Base = 0x400(00000)
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227 * Size = 1M
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228 * 21285 Registers
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229 *
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230 * Actual Base = 0x400(10000)
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231 * Virtual Base = 0x400(10000)
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232 * Size = 1M
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233 * Soft I/O port and XBus IO
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234 */
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235 ARM_MMU_SECTION(ttb_base, 0x400, 0x400,
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236 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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237 ARM_ACCESS_PERM_RW_RW);
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238
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239 /*
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240 * Actual Base = 0x410(00000) - 0x413(FFFFF)
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241 * Virtual Base = 0x410(00000) - 0x413(FFFFF)
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242 * Size = 4M
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243 * FLASH ROM
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244 */
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245 for (i = 0x410; i <= 0x413; i++) {
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246 ARM_MMU_SECTION(ttb_base, i, i,
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247 ARM_CACHEABLE, ARM_UNBUFFERABLE,
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248 ARM_ACCESS_PERM_RW_RW);
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249 }
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250
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251 /*
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252 * Actual Base = 0x420(00000)
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253 * Virtual Base = 0x420(00000)
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254 * Size = 1M
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255 * 21285 CSR Space
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256 */
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257 ARM_MMU_SECTION(ttb_base, 0x420, 0x420,
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258 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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259 ARM_ACCESS_PERM_RW_RW);
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260
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261 /*
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262 * Actual Base = 0x500(00000)-0x50F(FFFFF)
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263 * Virtual Base = 0x500(00000)-0x50F(FFFFF)
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264 * Size = 16M
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265 * Zeros (Cache Clean) Bank
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266 */
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267 for (i = 0x500; i <= 0x50F; i++) {
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268 ARM_MMU_SECTION(ttb_base, i, i,
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269 ARM_CACHEABLE, ARM_BUFFERABLE,
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270 ARM_ACCESS_PERM_RW_RW);
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271 }
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272
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273 /*
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274 * Actual Base = 0x780(00000)-0x78F(FFFFF)
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275 * Virtual Base = 0x780(00000)-0x78F(FFFFF)
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276 * Size = 16M
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277 * Outbound Write Flush
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278 */
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279 for (i = 0x780; i <= 0x78F; i++) {
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280 ARM_MMU_SECTION(ttb_base, i, i,
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281 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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282 ARM_ACCESS_PERM_RW_RW);
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283 }
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284
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285 /*
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286 * Actual Base = 0x790(00000)-0x7C0(FFFFF)
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287 * Virtual Base = 0x790(00000)-0x7C0(FFFFF)
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288 * Size = 65M
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289 * PCI IACK/Config/IO Space
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290 */
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291 for (i = 0x790; i <= 0x7C0; i++) {
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292 ARM_MMU_SECTION(ttb_base, i, i,
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293 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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294 ARM_ACCESS_PERM_RW_RW);
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295 }
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296
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297 /*
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298 * Actual Base = 0x800(00000) - 0xFFF(FFFFF)
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299 * Virtual Base = 0x800(00000) - 0xFFF(FFFFF)
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300 * Size = 2G
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301 * PCI Memory Space
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302 */
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303 for (i = 0x800; i <= 0xFFF; i++) {
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304 ARM_MMU_SECTION(ttb_base, i, i,
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305 ARM_UNCACHEABLE, ARM_BUFFERABLE,
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306 ARM_ACCESS_PERM_RW_RW);
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307 }
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308
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309 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_AMBER_LED; // AmberLED on
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310
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311 }
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312
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313 // -------------------------------------------------------------------------
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314 static cyg_uint32 _period;
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315
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316 void hal_clock_initialize(cyg_uint32 period)
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317 {
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318 _period = period;
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319
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320 *SA110_TIMER3_CONTROL = 0; // Disable while we are setting up
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321
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322 *SA110_TIMER3_LOAD = period; // Reload value
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323
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324 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt
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325 // (Data: don't care)
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326
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327 *SA110_TIMER3_CONTROL = 0x000000cc; // Enable, Periodic (auto-reload),
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328 // External clock (3.68MHz on irq_in_l[2] for Timer 3)
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329
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330 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt again
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331
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332 // That's all.
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333 }
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334
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335 // This routine is called during a clock interrupt.
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336
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337 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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338 {
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339 *SA110_TIMER3_CLEAR = period; // Clear any pending interrupt (Data: don't care)
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340 }
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341
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342 // Read the current value of the clock, returning the number of hardware
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343 // "ticks" that have occurred (i.e. how far away the current value is from
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344 // the start)
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345
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346 void hal_clock_read(cyg_uint32 *pvalue)
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347 {
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348 *pvalue = (cyg_uint32)(_period) - *SA110_TIMER3_VALUE;
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349 }
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350
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351 // -------------------------------------------------------------------------
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352
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353 // This routine is called to respond to a hardware interrupt (IRQ). It
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354 // should interrogate the hardware and return the IRQ vector number.
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355 int hal_IRQ_handler(void)
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356 {
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357 int sources;
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358 int index;
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359
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360 #if 0 // test FIQ and print alert if active - really for debugging
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361 sources = *SA110_IRQCONT_FIQSTATUS;
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362 if ( 0 != sources )
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363 diag_printf( "FIQ source active!!! - fiqstatus %08x irqstatus %08x\n",
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364 sources, *SA110_IRQCONT_IRQSTATUS );
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365 else
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366 #endif // Scan FIQ sources also
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367
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368 sources = *SA110_IRQCONT_IRQSTATUS;
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369
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370 // if we come to support FIQ properly...
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371 // if ( 0 == sources )
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372 // sources = *SA110_IRQCONT_FIQSTATUS;
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373
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374 // Nothing wrong with scanning them in the order provided...
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375 // and it'll make the serial device steal fewer cycles.
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376 // So, knowing this is an ARM:
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377 if ( sources & 0xff )
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378 index = 0;
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379 else if ( sources & 0xff00 )
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380 index = 8;
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381 else if ( sources & 0xff0000 )
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382 index = 16;
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383 else // if ( sources & 0xff000000 )
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384 index = 24;
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385
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386 do {
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387 if ( (1 << index) & sources )
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388 return index;
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389 index++;
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390 } while ( index & 7 );
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391
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392 return CYGNUM_HAL_INTERRUPT_reserved0; // This shouldn't happen!
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393 }
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394
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395 //
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396 // Interrupt control
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397 //
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398
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399 void hal_interrupt_mask(int vector)
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400 {
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401 *SA110_IRQCONT_IRQENABLECLEAR = 1 << vector;
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402 }
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403
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404 void hal_interrupt_unmask(int vector)
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405 {
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406 *SA110_IRQCONT_IRQENABLESET = 1 << vector;
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407 }
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408
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409 void hal_interrupt_acknowledge(int vector)
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410 {
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411 // Nothing to do here.
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412 }
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413
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414 void hal_interrupt_configure(int vector, int level, int up)
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415 {
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416 // No interrupts are configurable on this hardware
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417 }
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418
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419 void hal_interrupt_set_level(int vector, int level)
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420 {
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421 // No interrupts are configurable on this hardware
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422 }
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423
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424 /*------------------------------------------------------------------------*/
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425 // EOF ebsa285_misc.c