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annotate packages/hal/mips/vr4300/current/include/variant.inc @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children 9160a8005d76
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## VR4300 assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): nickg
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37 ## Contributors: nickg
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38 ## Date: 1999-04-06
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39 ## Purpose: VR4300 definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the VR4300 CPU.
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42 ## Usage:
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43 ## #include <cyg/hal/variant.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 .set mips3
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52
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53 #include <cyg/hal/mips.inc>
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54
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55 #include <cyg/hal/platform.inc>
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56
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57 #include <pkgconf/hal.h>
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58
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59 #------------------------------------------------------------------------------
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60 # Set up initial value for config register. Sets endian mode and
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61 # disables the cache on kseg0.
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62
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63 #if defined(CYGPKG_HAL_MIPS_MSBFIRST)
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64 # define INITIAL_CONFIG0 0x00008002
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65 #elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
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66 # define INITIAL_CONFIG0 0x00000002
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67 #else
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68 # error MIPS endianness not set by configuration
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69 #endif
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70
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71 #------------------------------------------------------------------------------
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72 # Set up initial value for FPU FCR31 register. We set the FS bit to flush
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73 # denormalized results to zero.
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74
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75 #ifndef CYG_HAL_MIPS_FCSR_INIT
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76 #define CYG_HAL_MIPS_FCSR_INIT 0x01000000
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77 #endif
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78
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79 #------------------------------------------------------------------------------
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80 # Cache macros.
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81
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82 #ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
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83
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84 .macro hal_cache_init
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85
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86 mfc0 v0,config0 # disable Kseg0 caching in config0 register
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87 nop
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88 nop
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89 la v1,0xfffffff8
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90 and v0,v0,v1
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91 ori v0,v0,2
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92 mtc0 v0,config0
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93 nop
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94 nop
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95 nop
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96
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97 .set mips3 # Set ISA to MIPS 3 to allow cache insns
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98
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99 # Now ensure the caches are invalidated. The caches are NOT cleared or
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100 # invalidated on non-power-up resets and may come up in a random state
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101 # on power-up. Hence they may contain stale or randomly bogus data.
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102 # Here we use the index-store-tag cache operation to clear all the cache
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103 # tags and states to zero. This will render them all invalid on the
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104 # VR4300.
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105
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106 # D-cache:
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107 la t0,0x80000000
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108 addi t1,t0,0x2000
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109 1:
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110 mtc0 zero,$28
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111 mtc0 zero,$29
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112 cache 0x09,0(t0)
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113 addi t0,t0,0x10
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114 sub v0,t1,t0
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115 bgez v0,1b
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116 nop # delay slot
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117
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118 # I-cache:
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119 la a0,0x80000000
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120 addi a1,a0,0x4000
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121 1:
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122 mtc0 zero,$28
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123 mtc0 zero,$29
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124 cache 0x08,0(a0)
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125 addi a0,a0,0x20
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126 sub v0,a1,a0
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127 bgez v0,1b
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128 nop # delay slot
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129
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130 .set mips0 # reset ISA to default
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131
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132 .endm
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133
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134 #define CYGPKG_HAL_MIPS_CACHE_DEFINED
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135
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136 #endif
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137
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138 #------------------------------------------------------------------------------
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139 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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140 # end of variant.inc