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annotate packages/hal/powerpc/arch/current/include/arch.inc @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children e0c0827131d1
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 ##=============================================================================
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2 ##
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3 ## arch.inc
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4 ##
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5 ## PowerPC architecture assembler header file
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6 ##
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7 ##=============================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.1 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://www.redhat.com/
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 ##=============================================================================
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32 #######DESCRIPTIONBEGIN####
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33 ##
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34 ## Author(s): nickg
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35 ## Contributors:nickg
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36 ## Date: 1997-10-16
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37 ## Purpose: PowerPC definitions.
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38 ## Description: This file contains various definitions and macros that are
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39 ## useful for writing assembly code for the PowerPC
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40 ## It also includes the variant assembly header file.
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41 ## Usage:
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42 ## #include <cyg/hal/arch.inc>
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43 ## ...
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44 ##
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45 ##
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46 ######DESCRIPTIONEND####
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47 ##
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48 ##=============================================================================
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49
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50 #include <cyg/hal/variant.inc>
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51 #include <cyg/hal/ppc_offsets.inc>
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52
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53 #------------------------------------------------------------------------------
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54 # Easier to read names for the registers
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55
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56 .equ r0, 0
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57 .equ r1, 1
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58 .equ r2, 2
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59 .equ r3, 3
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60 .equ r4, 4
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61 .equ r5, 5
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62 .equ r6, 6
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63 .equ r7, 7
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64 .equ r8, 8
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65 .equ r9, 9
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66 .equ r10, 10
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67 .equ r11, 11
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68 .equ r12, 12
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69 .equ r13, 13
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70 .equ r14, 14
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71 .equ r15, 15
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72 .equ r16, 16
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73 .equ r17, 17
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74 .equ r18, 18
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75 .equ r19, 19
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76 .equ r20, 20
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77 .equ r21, 21
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78 .equ r22, 22
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79 .equ r23, 23
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80 .equ r24, 24
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81 .equ r25, 25
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82 .equ r26, 26
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83 .equ r27, 27
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84 .equ r28, 28
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85 .equ r29, 29
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86 .equ r30, 30
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87 .equ r31, 31
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88
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89 .equ sp, r1
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90
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91 #------------------------------------------------------------------------------
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92 # Some useful coding macros
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93
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94 # Load immediate word, has to be done with 2 instructions
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95 .macro lwi reg,val
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96 lis \reg,\val@H
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97 ori \reg,\reg,\val@L
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98 .endm
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99
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100 #ifdef CYGPKG_HAL_POWERPC_PPC603
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101 # Move from HID0 hw control register
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102 .macro mfhid0 reg
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103 mfspr \reg,HID0
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104 .endm
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105 #endif
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106
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107 #define FUNC_START(name) \
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108 .type name,@function; \
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109 .globl name; \
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110 name:
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111
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112 #define FUNC_END(name) \
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113 /* nothing for now */
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114
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115 ##-----------------------------------------------------------------------------
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116 ## PowerPC FPU state handling
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117 ## Empty for now.
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118
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119 .macro hal_fpu_save regs
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120 .endm
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121
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122 .macro hal_fpu_load regs
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123 .endm
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124
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125 ##-----------------------------------------------------------------------------
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126 ## CPU specific macros. These provide a common assembler interface to
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127 ## operations that may have CPU specific implementations on different
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128 ## variants of the architecture.
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129
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130 # Enable interrupts
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131 .macro hal_cpu_int_enable
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132 mfmsr r0
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133 ori r3,r3,0x8000
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134 rlwimi r0,r3,0,16,16
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135 sync
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136 mtmsr r0
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137 sync
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138 .endm
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139
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140 # Disable interrupts
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141 .macro hal_cpu_int_disable
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142 mfmsr r0
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143 li r3,0
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144 rlwimi r0,r3,0,16,16
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145 sync
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146 mtmsr r0
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147 sync
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148 .endm
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149
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150 # Merge the interrupt enable state of the status register in
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151 # \sr with the current sr.
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152 .macro hal_cpu_int_merge sr
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153 mfmsr r0
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154 rlwimi r0,\sr,0,16,16
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155 sync
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156 mtmsr r0
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157 sync
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158 .endm
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159
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160 #------------------------------------------------------------------------------
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161 # end of arch.inc