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annotate packages/hal/sh/arch/current/include/sh_regs.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 59d97b6ba612
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_HAL_SH_REGS_H
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2 #define CYGONCE_HAL_SH_REGS_H
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3
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4 //=============================================================================
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5 //
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6 // sh_regs.h
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7 //
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8 // SH CPU definitions
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors:jskov
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39 // Date: 1999-04-24
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40 // Purpose: Define CPU memory mapped registers etc.
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41 // Usage: #include <cyg/hal/sh_regs.h>
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42
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43 //
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44 //####DESCRIPTIONEND####
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45 //
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46 //=============================================================================
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47
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48 //#include <pkgconf/hal.h>
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49
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50 //--------------------------------------------------------------------------
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51 // Status register
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52 #define CYGARC_REG_SR_MD 0x40000000
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53 #define CYGARC_REG_SR_RB 0x20000000
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54 #define CYGARC_REG_SR_BL 0x10000000
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55 #define CYGARC_REG_SR_M 0x00000200
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56 #define CYGARC_REG_SR_Q 0x00000100
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57 #define CYGARC_REG_SR_IMASK 0x000000f0
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58 #define CYGARC_REG_SR_I3 0x00000080
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59 #define CYGARC_REG_SR_I2 0x00000040
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60 #define CYGARC_REG_SR_I1 0x00000020
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61 #define CYGARC_REG_SR_I0 0x00000010
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62 #define CYGARC_REG_SR_S 0x00000002
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63 #define CYGARC_REG_SR_T 0x00000001
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64
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65
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66 //--------------------------------------------------------------------------
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67 // Cache registers
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68 #define CYGARC_REG_CCR 0xffffffec
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69
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70 #define CYGARC_REG_CCR_RA 0x00000020
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71 #define CYGARC_REG_CCR_CF 0x00000008
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72 #define CYGARC_REG_CCR_CB 0x00000004
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73 #define CYGARC_REG_CCR_WT 0x00000002
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74 #define CYGARC_REG_CCR_CE 0x00000001
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75
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76 #ifdef CYGPKG_HAL_SH_EDK7708
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77 // way: bits 12 - 10
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78 // entry: bits 10 - 4
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79 #define CYGARC_REG_CACHE_ADDRESS_BASE 0xf0000000
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80 #define CYGARC_REG_CACHE_ADDRESS_TOP 0xf0002000
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81 #define CYGARC_REG_CACHE_ADDRESS_STEP 0x00000010
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82 // U : bit 1
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83 // V : bit 0
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84 // Writing zero to both forces a flush of the line if it was dirty.
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85 #define CYGARC_REG_CACHE_ADDRESS_FLUSH 0x00000000
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86
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87 #endif
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88
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89 //--------------------------------------------------------------------------
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90 // MMU control registers
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91 #define CYGARC_REG_MMUCR 0xffffffe0
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92
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93 #define CYGARC_REG_MMUCR_SV 0x00000100
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94 #define CYGARC_REG_MMUCR_RC_MASK 0x000000c0
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95 #define CYGARC_REG_MMUCR_TF 0x00000004
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96 #define CYGARC_REG_MMUCR_IX 0x00000002
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97 #define CYGARC_REG_MMUCR_AT 0x00000001
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98
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99 //--------------------------------------------------------------------------
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100 // Bus State Control
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101 #define CYGARC_REG_BCR1 0xffffff60
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102 #define CYGARC_REG_BCR2 0xffffff62
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103 #define CYGARC_REG_WCR1 0xffffff64
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104 #define CYGARC_REG_WCR2 0xffffff66
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105 #define CYGARC_REG_MCR 0xffffff68
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106 #define CYGARC_REG_DCR 0xffffff6a
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107 #define CYGARC_REG_PCR 0xffffff6c
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108 #define CYGARC_REG_RTCSR 0xffffff6e
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109 #define CYGARC_REG_RTCNT 0xffffff70
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110 #define CYGARC_REG_RTCOR 0xffffff72
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111 #define CYGARC_REG_RFCR 0xffffff74
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112 #define CYGARC_REG_SDMR_AREA2_BASE 0xffffd000
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113 #define CYGARC_REG_SDMR_AREA3_BASE 0xffffe000
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114
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115 #define CYGARC_REG_BCR1_DRAMTP2 0x0010
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116 #define CYGARC_REG_BCR1_DRAMTP1 0x0008
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117 #define CYGARC_REG_BCR1_DRAMTP0 0x0004
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118
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119
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120 //--------------------------------------------------------------------------
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121 // User Break Control
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122 #define CYGARC_REG_BRCR 0xffffff98 // 16 bit
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123
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124 #define CYGARC_REG_BARA 0xffffffb0 // 32 bit
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125 #define CYGARC_REG_BAMRA 0xffffffb4 // 8 bit
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126 #define CYGARC_REG_BBRA 0xffffffb8 // 16 bit
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127 #define CYGARC_REG_BASRA 0xffffffe4 // 8 bit
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128
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129 #define CYGARC_REG_BARB 0xffffffa0 // 32 bit
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130 #define CYGARC_REG_BAMRB 0xffffffa4 // 8 bit
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131 #define CYGARC_REG_BASRB 0xffffffe8 // 8 bit
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132 #define CYGARC_REG_BBRB 0xffffffa8 // 16 bit
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133 #define CYGARC_REG_BDRB 0xffffff90 // 32 bit
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134 #define CYGARC_REG_BDMRB 0xffffff94 // 32 bit
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135
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136
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137 #define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A
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138 #define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B
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139 #define CYGARC_REG_BRCR_PCBA 0x0400 // PC break select A
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140 #define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B
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141 #define CYGARC_REG_BRCR_PCBB 0x0040 // PC break select B
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142 #define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select
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143
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144
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145
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146 //--------------------------------------------------------------------------
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147 // Oscillator control registers
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148 #define CYGARC_REG_FRQCR 0xffffff80
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149 #define CYGARC_REG_WTCNT 0xffffff84 // read 8bit, write 16bit
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150 #define CYGARC_REG_WTCSR 0xffffff86 // read 8bit, write 16bit
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151
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152 #define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write
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153
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154 #define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write
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155 #define CYGARC_REG_WTCSR_TME 0x80 // timer enable
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156 #define CYGARC_REG_WTCSR_WT_IT 0x40 // watchdog(1)/interval(0)
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157 #define CYGARC_REG_WTCSR_RSTS 0x20 // manual(1)/poweron(0)
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158 #define CYGARC_REG_WTCSR_WOVF 0x10 // watchdog overflow
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159 #define CYGARC_REG_WTCSR_IOVF 0x08 // interval overflow
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160 #define CYGARC_REG_WTCSR_CKS2 0x04 // clock select 2
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161 #define CYGARC_REG_WTCSR_CKS1 0x02 // clock select 1
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162 #define CYGARC_REG_WTCSR_CKS0 0x01 // clock select 0
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163 #define CYGARC_REG_WTCSR_CKSx_MASK 0x07 // clock select mask
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164 // This is the period (in us) between watchdog reset and overflow.
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165 // (used by the watchdog driver - board specific)
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166 // Based on a 15MHz clock with max delay: 15Mhz/(4096 * 256)
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167 #define CYGARC_REG_WTCSR_CKSx_SETTING 0x07 // max delay
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168 #define CYGARC_REG_WTCSR_PERIOD 69905067 // ~69.9 ms
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169
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170 //--------------------------------------------------------------------------
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171 // TMU registers
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172 #define CYGARC_REG_TOCR 0xfffffe90 // 8 bit
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173 #define CYGARC_REG_TSTR 0xfffffe92 // 8 bit
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174 #define CYGARC_REG_TCOR0 0xfffffe94 // 32 bit
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175 #define CYGARC_REG_TCNT0 0xfffffe98 // 32 bit
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176 #define CYGARC_REG_TCR0 0xfffffe9c // 16 bit
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177 #define CYGARC_REG_TCOR1 0xfffffea0 // 32 bit
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178 #define CYGARC_REG_TCNT1 0xfffffea4 // 32 bit
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179 #define CYGARC_REG_TCR1 0xfffffea8 // 16 bit
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180 #define CYGARC_REG_TCOR2 0xfffffeac // 32 bit
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181 #define CYGARC_REG_TCNT2 0xfffffeb0 // 32 bit
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182 #define CYGARC_REG_TCR2 0xfffffeb4 // 16 bit
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183 #define CYGARC_REG_TCPR2 0xfffffeb8 // 32 bit
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184
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185 // TSTR
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186 #define CYGARC_REG_TSTR_STR0 0x0001
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187 #define CYGARC_REG_TSTR_STR1 0x0002
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188 #define CYGARC_REG_TSTR_STR2 0x0004
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189
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190 // TCR0/1/2
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191 #define CYGARC_REG_TCR_TPSC0 0x0001
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192 #define CYGARC_REG_TCR_TPSC1 0x0002
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193 #define CYGARC_REG_TCR_TPSC2 0x0004
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194 #define CYGARC_REG_TCR_CKEG0 0x0008
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195 #define CYGARC_REG_TCR_CKEG1 0x0010
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196 #define CYGARC_REG_TCR_UNIE 0x0020
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197 #define CYGARC_REG_TCR_UNF 0x0100
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198
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199 // TCR2 additional bits
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200 #define CYGARC_REG_TCR_ICPE0 0x0040
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201 #define CYGARC_REG_TCR_ICPE1 0x0080
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202 #define CYGARC_REG_TCR_ICPF 0x0200
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203
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204 //--------------------------------------------------------------------------
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205 // Interrupt registers
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206 #define CYGARC_REG_EXCEVT 0xffffffd4
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207 #define CYGARC_REG_INTEVT 0xffffffd8
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208
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209 #define CYGARC_REG_ICR 0xfffffee0
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210 #define CYGARC_REG_IPRA 0xfffffee2
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211 #define CYGARC_REG_IPRB 0xfffffee4
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212
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213 #define CYGARC_REG_IPRA_TMU0_MASK 0xf000
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214 #define CYGARC_REG_IPRA_TMU0_PRI1 0x1000
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215 #define CYGARC_REG_IPRA_TMU1_MASK 0x0f00
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216 #define CYGARC_REG_IPRA_TMU1_PRI1 0x0100
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217 #define CYGARC_REG_IPRA_TMU2_MASK 0x00f0
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218 #define CYGARC_REG_IPRA_TMU2_PRI1 0x0010
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219 #define CYGARC_REG_IPRA_RTC_MASK 0x000f
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220 #define CYGARC_REG_IPRA_RTC_PRI1 0x0001
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221
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222 #define CYGARC_REG_IPRB_WDT_MASK 0xf000
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223 #define CYGARC_REG_IPRB_WDT_PRI1 0x1000
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224 #define CYGARC_REG_IPRB_REF_MASK 0x0f00
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225 #define CYGARC_REG_IPRB_REF_PRI1 0x0100
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226 #define CYGARC_REG_IPRB_SCI_MASK 0x00f0
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227 #define CYGARC_REG_IPRB_SCI_PRI1 0x0010
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228
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229
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230
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231
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232 //--------------------------------------------------------------------------
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233 // Serial registers. All 8 bit registers.
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234 #define CYGARC_REG_SCSMR 0xfffffe80 // serial mode register
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235 #define CYGARC_REG_SCBRR 0xfffffe82 // bit rate register
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236 #define CYGARC_REG_SCSCR 0xfffffe84 // serial control register
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237 #define CYGARC_REG_SCTDR 0xfffffe86 // transmit data register
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238 #define CYGARC_REG_SCSSR 0xfffffe88 // serial status register
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239 #define CYGARC_REG_SCRDR 0xfffffe8a // receive data register
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240 #define CYGARC_REG_SCSPTR 0xfffffe7c // serial port register
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241
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242 // Serial Mode Register
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243 #define CYGARC_REG_SCSMR_CA 0x80 // communication mode
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244 #define CYGARC_REG_SCSMR_CHR 0x40 // character length (7 if set)
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245 #define CYGARC_REG_SCSMR_PE 0x20 // parity enable
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246 #define CYGARC_REG_SCSMR_OE 0x10 // parity mode
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247 #define CYGARC_REG_SCSMR_STOP 0x08 // stop bit length
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248 #define CYGARC_REG_SCSMR_MP 0x04 // multiprocessor mode
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249 #define CYGARC_REG_SCSMR_CKS1 0x02 // clock select 1
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250 #define CYGARC_REG_SCSMR_CKS0 0x01 // clock select 0
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251 #define CYGARC_REG_SCSMR_CKSx_MASK 0x03 // mask
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252
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253 // Serial Control Register
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254 #define CYGARC_REG_SCSCR_TIE 0x80 // transmit interrupt enable
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255 #define CYGARC_REG_SCSCR_RIE 0x40 // receive interrupt enable
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256 #define CYGARC_REG_SCSCR_TE 0x20 // transmit enable
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257 #define CYGARC_REG_SCSCR_RE 0x10 // receive enable
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258 #define CYGARC_REG_SCSCR_MPIE 0x08 // multiprocessor interrupt enable
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259 #define CYGARC_REG_SCSCR_TEIE 0x04 // transmit-end interrupt enable
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260 #define CYGARC_REG_SCSCR_CKE1 0x02 // clock enable 1
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261 #define CYGARC_REG_SCSCR_CKE0 0x01 // clock enable 0
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262
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263 // Serial Status Register
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264 #define CYGARC_REG_SCSSR_TDRE 0x80 // transmit data register empty
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265 #define CYGARC_REG_SCSSR_RDRF 0x40 // receive data register full
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266 #define CYGARC_REG_SCSSR_ORER 0x20 // overrun error
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267 #define CYGARC_REG_SCSSR_FER 0x10 // framing error
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268 #define CYGARC_REG_SCSSR_PER 0x08 // parity error
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269 #define CYGARC_REG_SCSSR_TEND 0x04 // transmit end
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270 #define CYGARC_REG_SCSSR_MPB 0x02 // multiprocessor bit
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271 #define CYGARC_REG_SCSSR_MPBT 0x01 // multiprocessor bit transfer
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272
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273 // When clearing the status register, always write the value:
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274 // CYGARC_REG_SCSSR_CLEARMASK & ~bit
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275 // to prevent other bits than the one of interest to be cleared.
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276 #define CYGARC_REG_SCSSR_CLEARMASK 0xf8
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277
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278
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279 // Baud rate values calculated for peripheral clock = 15MHz (Pf = 15).
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280 // n is CKS setting (0-3)
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281 // N = (Pf/(64^(n-1)*B))*10^6-1
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282 // E(%) = ((Pf*10^6/((N+1)*B*(64^(n-1)))-1)*100
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283 #define CYGARC_REG_SCBRR_50
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284 #define CYGARC_REG_CKSx_50
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285 #define CYGARC_REG_SCBRR_75
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286 #define CYGARC_REG_CKSx_75
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287 #define CYGARC_REG_SCBRR_110
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288 #define CYGARC_REG_CKSx_110
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289 #define CYGARC_REG_SCBRR_134_5
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290 #define CYGARC_REG_CKSx_134_5
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291 #define CYGARC_REG_SCBRR_150
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292 #define CYGARC_REG_CKSx_150
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293 #define CYGARC_REG_SCBRR_200
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294 #define CYGARC_REG_CKSx_200
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295 #define CYGARC_REG_SCBRR_300
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296 #define CYGARC_REG_CKSx_300
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297 #define CYGARC_REG_SCBRR_600
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298 #define CYGARC_REG_CKSx_600
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299 #define CYGARC_REG_SCBRR_1200
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300 #define CYGARC_REG_CKSx_1200
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301 #define CYGARC_REG_SCBRR_1800
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302 #define CYGARC_REG_CKSx_1800
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303 #define CYGARC_REG_SCBRR_2400
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304 #define CYGARC_REG_CKSx_2400
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305 #define CYGARC_REG_SCBRR_3600
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306 #define CYGARC_REG_CKSx_3600
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307 #define CYGARC_REG_SCBRR_4800 97
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308 #define CYGARC_REG_CKSx_4800 0
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309 #define CYGARC_REG_SCBRR_7200
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310 #define CYGARC_REG_CKSx_7200
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311 #define CYGARC_REG_SCBRR_9600 48
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312 #define CYGARC_REG_CKSx_9600 0
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313 #define CYGARC_REG_SCBRR_14400 32
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314 #define CYGARC_REG_CKSx_14400 0
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315 #define CYGARC_REG_SCBRR_19200 23
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316 #define CYGARC_REG_CKSx_19200 0
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317 #define CYGARC_REG_SCBRR_38400 11
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318 #define CYGARC_REG_CKSx_38400 0
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319 #define CYGARC_REG_SCBRR_57600 7
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320 #define CYGARC_REG_CKSx_57600 0
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321 #define CYGARC_REG_SCBRR_115200 3
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322 #define CYGARC_REG_CKSx_115200 0
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323 #define CYGARC_REG_SCBRR_234000
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324 #define CYGARC_REG_CKSx_234000
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325
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326 #endif // ifndef CYGONCE_HAL_SH_REGS_H