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1 #ifndef CYGONCE_HAL_ARCH_H |
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2 #define CYGONCE_HAL_ARCH_H |
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3 |
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4 //========================================================================== |
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5 // |
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6 // hal_arch.h |
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7 // |
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8 // Architecture specific abstractions |
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9 // |
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10 //========================================================================== |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //========================================================================== |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg, gthomas |
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36 // Contributors: nickg, gthomas |
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37 // Date: 1999-02-20 |
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38 // Purpose: Define architecture abstractions |
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39 // Usage: #include <cyg/hal/hal_arch.h> |
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40 |
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41 // |
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42 //####DESCRIPTIONEND#### |
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43 // |
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44 //========================================================================== |
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45 |
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46 #include <pkgconf/hal.h> // To decide on stack usage |
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47 #include <cyg/infra/cyg_type.h> |
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48 |
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49 // |
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50 // CPSR Register defines |
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51 // |
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52 |
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53 #define CPSR_IRQ_DISABLE 0x80 // IRQ disabled when =1 |
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54 #define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 |
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55 #define CPSR_UNDEF_MODE 0x1D |
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56 #define CPSR_SUPERVISOR_MODE 0x13 |
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57 #define CPSR_IRQ_MODE 0x12 |
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58 |
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59 #define CPSR_MODE_BITS 0x1F |
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60 |
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61 #define CPSR_INITIAL (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) |
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62 #define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE) |
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63 |
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64 //-------------------------------------------------------------------------- |
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65 // Processor saved states: |
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66 // The layout of this structure is also defined in "arm.inc", for assembly |
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67 // code, which will be generated automatically if this file changes. |
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68 |
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69 #define HAL_THREAD_CONTEXT_FIRST 0 |
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70 #define HAL_THREAD_CONTEXT_R0 (0-HAL_THREAD_CONTEXT_FIRST) |
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71 #define HAL_THREAD_CONTEXT_R4 (4-HAL_THREAD_CONTEXT_FIRST) |
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72 #define HAL_THREAD_CONTEXT_R10 (10-HAL_THREAD_CONTEXT_FIRST) |
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73 #define HAL_THREAD_CONTEXT_LAST 10 |
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74 #define HAL_NUM_THREAD_CONTEXT_REGS (HAL_THREAD_CONTEXT_LAST - \ |
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75 HAL_THREAD_CONTEXT_FIRST+1) |
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76 |
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77 // It seems that r0-r3,r12 are considered scratch by function calls |
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78 |
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79 typedef struct |
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80 { |
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81 // These are common to all saved states |
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82 cyg_uint32 d[HAL_NUM_THREAD_CONTEXT_REGS] ; // Data regs (r0..r10) |
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83 cyg_uint32 fp; // (r11) Frame pointer |
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84 cyg_uint32 sp; // (r13) Stack pointer |
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85 cyg_uint32 lr; // (r14) Link Reg |
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86 cyg_uint32 pc; // (r15) PC place holder |
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87 // (never used) |
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88 cyg_uint32 cpsr; // Condition Reg |
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89 cyg_uint32 ip; // (r12) Previous stack |
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90 // pointer |
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91 // These are only saved for exceptions and interrupts |
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92 cyg_uint32 vector; // Vector number |
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93 cyg_uint32 msr; // Machine State Reg |
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94 |
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95 } HAL_SavedRegisters; |
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96 |
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97 //------------------------------------------------------------------------- |
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98 // Exception handling function. |
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99 // This function is defined by the kernel according to this prototype. It is |
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100 // invoked from the HAL to deal with any CPU exceptions that the HAL does |
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101 // not want to deal with itself. It usually invokes the kernel's exception |
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102 // delivery mechanism. |
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103 |
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104 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); |
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105 |
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106 //------------------------------------------------------------------------- |
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107 // Bit manipulation macros |
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108 |
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109 externC int hal_lsbindex(int); |
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110 externC int hal_msbindex(int); |
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111 |
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112 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask) |
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113 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask) |
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114 |
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115 //------------------------------------------------------------------------- |
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116 // Context Initialization |
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117 // Initialize the context of a thread. |
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118 // Arguments: |
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119 // _sparg_ name of variable containing current sp, will be changed to new sp |
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120 // _thread_ thread object address, passed as argument to entry point |
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121 // _entry_ entry point address. |
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122 // _id_ bit pattern used in initializing registers, for debugging. |
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123 |
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124 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ |
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125 CYG_MACRO_START \ |
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126 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ |
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127 register HAL_SavedRegisters *_regs_; \ |
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128 int _i_; \ |
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129 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \ |
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130 for( _i_ = HAL_THREAD_CONTEXT_FIRST; _i_ <= HAL_THREAD_CONTEXT_LAST; \ |
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131 _i_++ ) \ |
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132 (_regs_)->d[_i_] = (_id_)|_i_; \ |
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133 (_regs_)->d[00] = (CYG_WORD)(_thread_); /* R0 = arg1 = thread ptr */ \ |
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134 (_regs_)->sp = (CYG_WORD)(_sp_); /* SP = top of stack */ \ |
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135 (_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \ |
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136 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */\ |
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137 (_regs_)->cpsr = (CPSR_THREAD_INITIAL); /* PSR = Interrupt enabled */ \ |
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138 _sparg_ = (CYG_ADDRESS)_regs_; \ |
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139 CYG_MACRO_END |
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140 |
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141 //-------------------------------------------------------------------------- |
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142 // Context switch macros. |
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143 // The arguments are pointers to locations where the stack pointer |
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144 // of the current thread is to be stored, and from where the sp of the |
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145 // next thread is to be fetched. |
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146 |
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147 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); |
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148 externC void hal_thread_load_context( CYG_ADDRESS to ) |
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149 __attribute__ ((noreturn)); |
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150 |
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151 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ |
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152 hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ |
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153 (CYG_ADDRESS)_fspptr_); |
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154 |
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155 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ |
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156 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); |
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157 |
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158 //-------------------------------------------------------------------------- |
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159 // Execution reorder barrier. |
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160 // When optimizing the compiler can reorder code. In multithreaded systems |
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161 // where the order of actions is vital, this can sometimes cause problems. |
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162 // This macro may be inserted into places where reordering should not happen. |
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163 |
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164 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) |
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165 |
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166 //-------------------------------------------------------------------------- |
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167 // Breakpoint support |
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168 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen |
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169 // if executed. |
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170 // HAL_BREAKINST is the value of the breakpoint instruction and |
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171 // HAL_BREAKINST_SIZE is its size in bytes. |
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172 |
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173 #define HAL_BREAKPOINT(_label_) \ |
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174 asm volatile (" .globl " #_label_ ";" \ |
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175 #_label_":" \ |
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176 " .word 0xE7FFDEFE" \ |
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177 ); |
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178 |
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179 //#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7} |
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180 #define HAL_BREAKINST 0xE7FFDEFE |
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181 #define HAL_BREAKINST_SIZE 4 |
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182 |
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183 //-------------------------------------------------------------------------- |
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184 // Thread register state manipulation for GDB support. |
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185 |
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186 // FIX ME!! What does GDB expect? |
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187 |
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188 // GDB expects the registers in this structure: |
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189 // r0..r10, fp, ip, sp, lr, pc - 4 bytes each |
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190 // f0..f7 - 12 bytes each (N/A on ARM7) |
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191 // fps - 4 bytes (N/A on ARM7) |
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192 // ps - 4 bytes |
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193 |
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194 // Translate a stack pointer as saved by the thread context macros above into |
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195 // a pointer to a HAL_SavedRegisters structure. |
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196 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ |
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197 (_regs_) = (HAL_SavedRegisters *)(_sp_) |
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198 |
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199 // Copy a set of registers from a HAL_SavedRegisters structure into a |
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200 // GDB ordered array. |
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201 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ |
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202 CYG_MACRO_START \ |
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203 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
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204 int _i_; \ |
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205 \ |
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206 for( _i_ = 0; _i_ <= 10; _i_++ ) \ |
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207 _regval_[_i_] = (_regs_)->d[_i_]; \ |
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208 \ |
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209 _regval_[11] = (_regs_)->fp; \ |
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210 _regval_[12] = (_regs_)->ip; \ |
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211 _regval_[13] = (_regs_)->sp; \ |
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212 _regval_[14] = (_regs_)->lr; \ |
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213 _regval_[15] = (_regs_)->pc; \ |
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214 _regval_[25] = (_regs_)->cpsr; \ |
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215 for( _i_ = 0; _i_ < 8; _i_++ ) \ |
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216 _regval_[_i_+16] = 0; \ |
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217 CYG_MACRO_END |
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218 |
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219 // Copy a GDB ordered array into a HAL_SavedRegisters structure. |
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220 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ |
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221 CYG_MACRO_START \ |
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222 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
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223 int _i_; \ |
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224 \ |
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225 for( _i_ = 0; _i_ <= 10; _i_++ ) \ |
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226 (_regs_)->d[_i_] = _regval_[_i_]; \ |
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227 \ |
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228 (_regs_)->fp = _regval_[11]; \ |
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229 (_regs_)->ip = _regval_[12]; \ |
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230 (_regs_)->sp = _regval_[13]; \ |
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231 (_regs_)->lr = _regval_[14]; \ |
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232 (_regs_)->pc = _regval_[15]; \ |
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233 (_regs_)->cpsr = _regval_[25]; \ |
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234 CYG_MACRO_END |
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235 |
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236 //-------------------------------------------------------------------------- |
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237 // HAL setjmp |
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238 |
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239 #define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over |
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240 |
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241 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; |
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242 |
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243 externC int hal_setjmp(hal_jmp_buf env); |
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244 externC void hal_longjmp(hal_jmp_buf env, int val); |
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245 |
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246 |
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247 //-------------------------------------------------------------------------- |
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248 // Idle thread code. |
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249 // This macro is called in the idle thread loop, and gives the HAL the |
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250 // chance to insert code. Typical idle thread behaviour might be to halt the |
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251 // processor. |
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252 |
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253 externC void hal_idle_thread_action(cyg_uint32 loop_count); |
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254 |
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255 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) |
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256 |
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257 //--------------------------------------------------------------------------- |
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258 |
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259 // Minimal and sensible stack sizes: the intention is that applications |
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260 // will use these to provide a stack size in the first instance prior to |
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261 // proper analysis. Idle thread stack should be this big. |
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262 |
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263 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. |
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264 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. |
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265 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! |
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266 |
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267 // This is not a config option because it should not be adjusted except |
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268 // under "enough rope" sort of disclaimers. |
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269 |
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270 // A minimal, optimized stack frame, rounded up - no autos |
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271 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20) |
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272 |
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273 // Stack needed for a context switch: this is implicit in the estimate for |
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274 // interrupts so not explicitly used below: |
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275 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20) |
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276 |
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277 // Interrupt + call to ISR, interrupt_end() and the DSR |
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278 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ |
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279 ((4 * 20) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) |
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280 |
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281 // Space for the maximum number of nested interrupts, plus room to call functions |
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282 #define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4 |
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283 |
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284 #define CYGNUM_HAL_STACK_SIZE_MINIMUM \ |
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285 (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \ |
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286 2 * CYGNUM_HAL_STACK_FRAME_SIZE) |
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287 |
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288 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ |
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289 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ |
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290 16 * CYGNUM_HAL_STACK_FRAME_SIZE) |
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291 |
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292 //----------------------------------------------------------------------------- |
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293 |
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294 #endif // CYGONCE_HAL_ARCH_H |
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295 // End of hal_arch.h |
