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1 #ifndef CYGONCE_HAL_HAL_INTR_H |
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2 #define CYGONCE_HAL_HAL_INTR_H |
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3 |
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4 //========================================================================== |
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5 // |
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6 // hal_intr.h |
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7 // |
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8 // HAL Interrupt and clock support |
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9 // |
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10 //========================================================================== |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //========================================================================== |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg, jskov, |
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37 // gthomas, jlarmour |
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38 // Date: 1999-02-16 |
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39 // Purpose: Define Interrupt support |
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40 // Description: The macros defined here provide the HAL APIs for handling |
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41 // interrupts and the clock. |
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42 // |
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43 // Usage: |
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44 // #include <cyg/hal/hal_intr.h> |
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45 // ... |
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46 // |
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47 // |
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48 //####DESCRIPTIONEND#### |
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49 // |
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50 //========================================================================== |
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51 |
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52 #include <pkgconf/hal.h> |
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53 |
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54 #include <cyg/infra/cyg_type.h> |
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55 #include <cyg/hal/hal_io.h> |
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56 |
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57 //-------------------------------------------------------------------------- |
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58 // MIPS vectors. |
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59 |
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60 // These are the exception codes presented in the Cause register and |
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61 // correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET |
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62 |
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63 // External interrupt |
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64 #define CYGNUM_HAL_VECTOR_INTERRUPT 0 |
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65 // TLB modification exception |
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66 #define CYGNUM_HAL_VECTOR_TLB_MOD 1 |
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67 // TLB miss (Load or IFetch) |
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68 #define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2 |
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69 // TLB miss (Store) |
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70 #define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3 |
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71 // Address error (Load or Ifetch) |
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72 #define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4 |
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73 // Address error (store) |
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74 #define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5 |
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75 // Bus error (Ifetch) |
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76 #define CYGNUM_HAL_VECTOR_IBE 6 |
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77 // Bus error (data load or store) |
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78 #define CYGNUM_HAL_VECTOR_DBE 7 |
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79 // System call |
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80 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8 |
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81 // Break point |
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82 #define CYGNUM_HAL_VECTOR_BREAKPOINT 9 |
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83 // Reserved instruction |
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84 #define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10 |
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85 // Coprocessor unusable |
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86 #define CYGNUM_HAL_VECTOR_COPROCESSOR 11 |
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87 // Arithmetic overflow |
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88 #define CYGNUM_HAL_VECTOR_OVERFLOW 12 |
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89 // Reserved |
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90 #define CYGNUM_HAL_VECTOR_RESERVED_13 13 |
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91 // Floating point exception - not applicable yet |
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92 // #define CYGNUM_HAL_VECTOR_FPE 15 |
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93 |
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94 #define CYGNUM_HAL_VSR_MIN 0 |
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95 #define CYGNUM_HAL_VSR_MAX 13 |
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96 #define CYGNUM_HAL_VSR_COUNT 14 |
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97 |
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98 // Exception vectors. These are the values used when passed out to an |
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99 // external exception handler using cyg_hal_deliver_exception() |
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100 |
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101 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD |
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102 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \ |
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103 CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL |
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104 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \ |
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105 CYGNUM_HAL_VECTOR_TLB_STORE_REFILL |
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106 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ |
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107 CYGNUM_HAL_VECTOR_LOAD_ADDRESS |
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108 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \ |
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109 CYGNUM_HAL_VECTOR_STORE_ADDRESS |
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110 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE |
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111 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE |
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112 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL |
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113 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT |
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114 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ |
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115 CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION |
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116 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR |
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117 #define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW |
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118 |
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119 // Min/Max exception numbers and how many there are |
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120 #define CYGNUM_HAL_EXCEPTION_MIN 1 |
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121 #define CYGNUM_HAL_EXCEPTION_MAX 13 |
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122 #define CYGNUM_HAL_EXCEPTION_COUNT 13 |
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123 |
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124 // Interrupt vectors. |
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125 |
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126 #if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) |
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127 |
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128 // These are decoded via the IP bits of the cause |
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129 // register when an external interrupt is delivered. |
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130 |
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131 #define CYGNUM_HAL_INTERRUPT_1 0 |
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132 #define CYGNUM_HAL_INTERRUPT_2 1 |
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133 #define CYGNUM_HAL_INTERRUPT_3 2 |
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134 #define CYGNUM_HAL_INTERRUPT_4 3 |
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135 #define CYGNUM_HAL_INTERRUPT_5 4 |
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136 #define CYGNUM_HAL_INTERRUPT_6 5 |
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137 #define CYGNUM_HAL_INTERRUPT_7 6 |
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138 #define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7 |
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139 #define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8 |
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140 #define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9 |
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141 #define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10 |
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142 #define CYGNUM_HAL_INTERRUPT_SIO_0 11 |
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143 #define CYGNUM_HAL_INTERRUPT_SIO_1 12 |
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144 #define CYGNUM_HAL_INTERRUPT_TMR_0 13 |
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145 #define CYGNUM_HAL_INTERRUPT_TMR_1 14 |
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146 #define CYGNUM_HAL_INTERRUPT_TMR_2 15 |
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147 #define CYGNUM_HAL_INTERRUPT_0 16 |
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148 |
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149 // Min/Max ISR numbers and how many there are |
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150 #define CYGNUM_HAL_ISR_MIN 0 |
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151 #define CYGNUM_HAL_ISR_MAX 16 |
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152 #define CYGNUM_HAL_ISR_COUNT 17 |
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153 |
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154 // The vector used by the Real time clock |
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155 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0 |
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156 |
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157 #endif |
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158 |
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159 //-------------------------------------------------------------------------- |
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160 // Static data used by HAL |
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161 |
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162 // ISR tables |
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163 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
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164 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; |
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165 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; |
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166 |
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167 // VSR table |
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168 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; |
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169 |
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170 //-------------------------------------------------------------------------- |
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171 // Default ISR |
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172 |
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173 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); |
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174 |
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175 //-------------------------------------------------------------------------- |
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176 // Interrupt state storage |
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177 |
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178 typedef cyg_uint32 CYG_INTERRUPT_STATE; |
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179 |
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180 //-------------------------------------------------------------------------- |
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181 // Interrupt control macros |
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182 // Beware of the nops in this code. These fill load/store delay slots to |
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183 // prevent following code being run in the wrong state. |
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184 |
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185 #define HAL_DISABLE_INTERRUPTS(_old_) \ |
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186 { \ |
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187 asm volatile ( \ |
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188 "mfc0 $8,$12; nop;" \ |
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189 "move %0,$8;" \ |
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190 "and $8,$8,0XFFFFFFFE;" \ |
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191 "mtc0 $8,$12;" \ |
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192 "nop; nop; nop;" \ |
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193 "and %0,%0,0X1;" \ |
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194 : "=r"(_old_) \ |
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195 : \ |
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196 : "$8" \ |
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197 ); \ |
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198 } |
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199 |
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200 #define HAL_ENABLE_INTERRUPTS() \ |
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201 { \ |
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202 asm volatile ( \ |
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203 "mfc0 $8,$12; nop;" \ |
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204 "or $8,$8,1;" \ |
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205 "mtc0 $8,$12;" \ |
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206 "nop; nop; nop;" \ |
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207 : \ |
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208 : \ |
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209 : "$8" \ |
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210 ); \ |
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211 } |
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212 |
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213 #define HAL_RESTORE_INTERRUPTS(_old_) \ |
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214 { \ |
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215 asm volatile ( \ |
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216 "mfc0 $8,$12; nop;" \ |
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217 "and %0,%0,0x1;" \ |
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218 "or $8,$8,%0;" \ |
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219 "mtc0 $8,$12;" \ |
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220 "nop; nop; nop;" \ |
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221 : \ |
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222 : "r"(_old_) \ |
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223 : "$8" \ |
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224 ); \ |
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225 } |
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226 |
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227 #define HAL_QUERY_INTERRUPTS( _state_ ) \ |
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228 { \ |
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229 asm volatile ( \ |
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230 "mfc0 %0,$12; nop;" \ |
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231 "and %0,%0,0x1;" \ |
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232 : "=r"(_state_) \ |
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233 : \ |
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234 : "$8" \ |
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235 ); \ |
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236 } |
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237 |
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238 //-------------------------------------------------------------------------- |
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239 // Vector translation. |
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240 // For chained interrupts we only have a single vector though which all |
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241 // are passed. For unchained interrupts we have a vector per interrupt. |
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242 |
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243 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
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244 |
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245 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 |
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246 |
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247 #else |
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248 |
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249 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) |
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250 |
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251 #endif |
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252 |
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253 //-------------------------------------------------------------------------- |
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254 // Interrupt and VSR attachment macros |
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255 |
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256 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
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257 CYG_MACRO_START \ |
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258 cyg_uint32 _index_; \ |
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259 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
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260 \ |
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261 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ |
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262 (_state_) = 0; \ |
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263 else \ |
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264 (_state_) = 1; \ |
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265 CYG_MACRO_END |
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266 |
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267 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ |
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268 { \ |
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269 cyg_uint32 _index_; \ |
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270 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ |
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271 \ |
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272 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ |
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273 { \ |
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274 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ |
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275 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ |
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276 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ |
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277 } \ |
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278 } |
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279 |
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280 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ |
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281 { \ |
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282 cyg_uint32 _index_; \ |
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283 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ |
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284 \ |
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285 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ |
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286 { \ |
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287 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \ |
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288 hal_interrupt_data[_index_] = 0; \ |
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289 hal_interrupt_objects[_index_] = 0; \ |
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290 } \ |
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291 } |
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292 |
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293 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ |
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294 *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; |
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295 |
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296 |
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297 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ |
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298 if( _poldvsr_ != NULL) \ |
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299 *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ |
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300 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ |
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301 CYG_MACRO_END |
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302 |
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303 // This is an ugly name, but what it means is: grab the VSR back to eCos |
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304 // internal handling, or if you like, the default handler. But if |
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305 // cooperating with GDB and CygMon, the default behaviour is to pass most |
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306 // exceptions to CygMon. This macro undoes that so that eCos handles the |
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307 // exception. So use it with care. |
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308 |
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309 externC void __default_exception_vsr(void); |
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310 externC void __default_interrupt_vsr(void); |
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311 |
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312 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ |
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313 HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ |
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314 ? (CYG_ADDRESS)__default_interrupt_vsr \ |
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315 : (CYG_ADDRESS)__default_exception_vsr, \ |
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316 _poldvsr_ ); \ |
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317 CYG_MACRO_END |
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318 |
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319 //-------------------------------------------------------------------------- |
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320 // Interrupt controller access |
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321 |
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322 #if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) |
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323 |
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324 #define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010 |
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325 #define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000 |
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326 |
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327 // Array which stores the configured priority levels for the configured |
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328 // interrupts. |
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329 externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; |
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330 |
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331 |
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332 #define HAL_INTERRUPT_MASK( _vector_ ) \ |
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333 { \ |
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334 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ |
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335 CYG_WORD32 _ilr_; \ |
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336 _reg_ += (_vector_)&0xC; \ |
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337 HAL_READ_UINT32( _reg_, _ilr_ ); \ |
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338 _ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \ |
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339 HAL_WRITE_UINT32( _reg_, _ilr_ ); \ |
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340 } |
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341 |
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342 #define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
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343 { \ |
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344 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ |
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345 CYG_WORD32 _ilr_; \ |
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346 _reg_ += (_vector_)&0xC; \ |
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347 HAL_READ_UINT32( _reg_, _ilr_ ); \ |
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348 _ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \ |
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349 HAL_WRITE_UINT32( _reg_, _ilr_ ); \ |
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350 } |
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351 |
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352 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
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353 { \ |
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354 if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ |
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355 _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ |
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356 { \ |
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357 cyg_uint32 _val_ = _vector_ + 1; \ |
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358 if( _val_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _val_ = 0; \ |
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359 HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _val_); \ |
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360 } \ |
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361 } |
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362 |
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363 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ |
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364 { \ |
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365 if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ |
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366 _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ |
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367 { \ |
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368 cyg_uint32 _val_ = 0; \ |
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369 if( _up_ ) _val_ |= 1; \ |
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370 if( !(_level_) ) _val_ |= 2; \ |
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371 HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _val_ ); \ |
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372 } \ |
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373 } |
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374 |
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375 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ |
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376 { \ |
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377 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \ |
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378 CYG_WORD32 _ilr_; \ |
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379 _reg_ += (_vector_)&0xC; \ |
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380 HAL_READ_UINT32( _reg_, _ilr_ ); \ |
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381 _ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \ |
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382 HAL_WRITE_UINT32( _reg_, _ilr_ ); \ |
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383 hal_interrupt_level[_vector_] = _level_; \ |
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384 } |
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385 |
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386 #else |
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387 |
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388 #error Unspecified platform for MIPS |
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389 |
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390 #endif |
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391 |
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392 //-------------------------------------------------------------------------- |
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393 // Clock control |
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394 |
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395 #if defined(CYG_HAL_MIPS_TX3904) || defined(CYG_HAL_MIPS_SIM) |
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396 |
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397 #define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000 |
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398 #define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00) |
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399 #define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04) |
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400 #define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08) |
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401 #define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10) |
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402 #define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20) |
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403 #define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0) |
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0
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404 |
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2
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405 #define HAL_CLOCK_INITIALIZE( _period_ ) \ |
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406 { \ |
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407 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \ |
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408 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \ |
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409 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ |
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410 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \ |
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411 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \ |
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412 } |
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413 |
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414 #define HAL_CLOCK_RESET( _vector_, _period_ ) \ |
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415 { \ |
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416 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \ |
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0
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417 } |
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418 |
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2
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419 #if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \ |
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420 !defined(CYG_HAL_MIPS_SIM) |
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421 |
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422 // We need to sync and check the coprocessor 0 condition - this indicates |
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423 // whether data is present in the write buffer. We need to wait until |
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424 // that data to be written is flushed out. This works around a tx39 bug. |
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425 // gcc will insert a NOP after the asm insns. |
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0
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426 |
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2
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427 # define HAL_CLOCK_READ( _pvalue_ ) \ |
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428 CYG_MACRO_START \ |
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429 asm volatile ( \ |
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430 "sync; nop; 1: ; bc0f 1b" \ |
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431 : \ |
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432 : \ |
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433 : "$0" \ |
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434 ); \ |
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435 HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ |
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436 CYG_MACRO_END |
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437 |
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438 #else |
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439 |
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440 # define HAL_CLOCK_READ( _pvalue_ ) \ |
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441 CYG_MACRO_START \ |
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442 HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \ |
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443 CYG_MACRO_END |
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444 |
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445 #endif |
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446 |
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447 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY |
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448 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) |
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449 #endif |
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0
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450 |
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451 #else |
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452 |
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453 #error Unspecified platform for MIPS |
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454 |
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455 #endif |
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456 |
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2
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457 //-------------------------------------------------------------------------- |
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458 // Timeout exception support. This is only enabled on the real TX39 hardware. |
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459 |
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460 #if defined(CYG_HAL_MIPS_TX3904) |
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461 |
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462 #define HAL_TX39_DEBUG_TOE_ENABLE() \ |
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463 { \ |
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464 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ |
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465 CYG_WORD32 _cconr_; \ |
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466 HAL_READ_UINT32( _reg_, _cconr_); \ |
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467 _cconr_ |= 0x04000000; \ |
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468 HAL_WRITE_UINT32( _reg_, _cconr_); \ |
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469 } |
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470 |
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471 #define HAL_TX39_DEBUG_TOE_DISABLE() \ |
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472 { \ |
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473 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \ |
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474 CYG_WORD32 _cconr_; \ |
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475 HAL_READ_UINT32( _reg_, _cconr_); \ |
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476 _cconr_ &= 0xFBFFFFFF; \ |
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477 HAL_WRITE_UINT32( _reg_, _cconr_); \ |
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478 } |
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479 |
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480 #else |
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481 |
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482 #define HAL_TX39_DEBUG_TOE_ENABLE() |
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483 |
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484 #define HAL_TX39_DEBUG_TOE_DISABLE() |
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485 |
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486 #endif |
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487 |
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488 //-------------------------------------------------------------------------- |
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0
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489 #endif // ifndef CYGONCE_HAL_HAL_INTR_H |
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490 // End of hal_intr.h |
