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1 #ifndef CYGONCE_HAL_CACHE_H |
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2 #define CYGONCE_HAL_CACHE_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // hal_cache.h |
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7 // |
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8 // HAL cache control API |
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9 // |
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10 //============================================================================= |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //============================================================================= |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1998-02-17 |
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38 // Purpose: Cache control API |
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39 // Description: The macros defined here provide the HAL APIs for handling |
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40 // cache control operations. |
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41 // Usage: |
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42 // #include <cyg/hal/hal_cache.h> |
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43 // ... |
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44 // |
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45 // |
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46 //####DESCRIPTIONEND#### |
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47 // |
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48 //============================================================================= |
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49 |
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50 #include <pkgconf/hal.h> |
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51 #include <cyg/infra/cyg_type.h> |
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52 |
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53 //============================================================================= |
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54 // MN10300 Simulator |
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55 |
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56 #if defined(CYG_HAL_MN10300_SIM) |
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57 |
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58 //----------------------------------------------------------------------------- |
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59 // Cache dimensions |
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60 |
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61 // Data cache |
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62 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
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63 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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64 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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65 |
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66 // Instruction cache |
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67 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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68 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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69 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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70 |
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71 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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72 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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73 |
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74 //----------------------------------------------------------------------------- |
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75 // Global control of data cache |
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76 |
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77 // Enable the data cache |
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78 #define HAL_DCACHE_ENABLE() |
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79 |
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80 // Disable the data cache |
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81 #define HAL_DCACHE_DISABLE() |
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82 |
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83 // Invalidate the entire cache |
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84 #define HAL_DCACHE_INVALIDATE_ALL() |
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85 |
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86 // Synchronize the contents of the cache with memory. |
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87 #define HAL_DCACHE_SYNC() |
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88 |
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89 // Set the data cache refill burst size |
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90 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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91 |
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92 // Set the data cache write mode |
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93 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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94 |
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95 // Load the contents of the given address range into the data cache |
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96 // and then lock the cache so that it stays there. |
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97 //#define HAL_DCACHE_LOCK(_base_, _size_) |
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98 |
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99 // Undo a previous lock operation |
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100 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
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101 |
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102 // Unlock entire cache |
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103 //#define HAL_DCACHE_UNLOCK_ALL() |
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104 |
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105 //----------------------------------------------------------------------------- |
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106 // Data cache line control |
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107 |
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108 // Allocate cache lines for the given address range without reading its |
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109 // contents from memory. |
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110 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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111 |
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112 // Write dirty cache lines to memory and invalidate the cache entries |
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113 // for the given address range. |
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114 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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115 |
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116 // Invalidate cache lines in the given range without writing to memory. |
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117 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
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118 |
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119 // Write dirty cache lines to memory for the given address range. |
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120 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
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121 |
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122 // Preread the given range into the cache with the intention of reading |
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123 // from it later. |
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124 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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125 |
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126 // Preread the given range into the cache with the intention of writing |
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127 // to it later. |
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128 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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129 |
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130 // Allocate and zero the cache lines associated with the given range. |
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131 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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132 |
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133 //----------------------------------------------------------------------------- |
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134 // Global control of Instruction cache |
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135 |
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136 // Enable the instruction cache |
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137 #define HAL_ICACHE_ENABLE() |
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138 |
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139 // Disable the instruction cache |
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140 #define HAL_ICACHE_DISABLE() |
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141 |
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142 // Invalidate the entire cache |
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143 #define HAL_ICACHE_INVALIDATE_ALL() |
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144 |
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145 // Synchronize the contents of the cache with memory. |
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146 #define HAL_ICACHE_SYNC() |
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147 |
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148 // Set the instruction cache refill burst size |
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149 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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150 |
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151 // Load the contents of the given address range into the instruction cache |
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152 // and then lock the cache so that it stays there. |
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153 //#define HAL_ICACHE_LOCK(_base_, _size_) |
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154 |
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155 // Undo a previous lock operation |
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156 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
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157 |
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158 // Unlock entire cache |
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159 //#define HAL_ICACHE_UNLOCK_ALL() |
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160 |
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161 //----------------------------------------------------------------------------- |
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162 // Instruction cache line control |
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163 |
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164 // Invalidate cache lines in the given range without writing to memory. |
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165 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
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166 |
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167 #endif |
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168 |
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169 |
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170 //============================================================================= |
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171 // MN103002 implementation |
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172 |
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173 #if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002) |
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174 |
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175 //----------------------------------------------------------------------------- |
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176 // Cache dimensions |
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177 |
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178 |
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179 // Data cache |
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180 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
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181 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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182 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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183 |
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184 // Instruction cache |
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185 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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186 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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187 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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188 |
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189 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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190 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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191 |
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192 //----------------------------------------------------------------------------- |
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193 // Control registers |
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194 |
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195 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070) |
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196 |
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197 #define HAL_CHCTR_ICEN 0x0001 |
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198 #define HAL_CHCTR_DCEN 0x0002 |
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199 #define HAL_CHCTR_ICBUSY 0x0004 |
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200 #define HAL_CHCTR_DCBUSY 0x0008 |
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201 #define HAL_CHCTR_ICINV 0x0010 |
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202 #define HAL_CHCTR_DCINV 0x0020 |
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203 #define HAL_CHCTR_DCWTMD 0x0040 |
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204 #define HAL_CHCTR_ICWMD 0x0300 |
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205 #define HAL_CHCTR_DCWMD 0x3000 |
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206 |
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207 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000) |
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208 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000) |
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209 |
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210 //----------------------------------------------------------------------------- |
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211 // Global control of data cache |
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212 |
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213 // Enable the data cache |
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214 #define HAL_DCACHE_ENABLE() \ |
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215 { \ |
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216 CYG_ADDRWORD chctr = *HAL_CHCTR; \ |
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217 chctr |= HAL_CHCTR_DCEN; \ |
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218 *HAL_CHCTR = chctr; \ |
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219 } |
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220 |
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221 // Disable the data cache |
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222 #define HAL_DCACHE_DISABLE() \ |
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223 { \ |
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224 CYG_ADDRWORD chctr = *HAL_CHCTR; \ |
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225 chctr &= ~HAL_CHCTR_DCEN; \ |
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226 *HAL_CHCTR = chctr; \ |
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227 } |
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228 |
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229 // Invalidate the entire cache |
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230 #define HAL_DCACHE_INVALIDATE_ALL() \ |
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231 { \ |
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232 CYG_ADDRWORD chctr, chctr1; \ |
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233 chctr = chctr1 = *HAL_CHCTR; \ |
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234 chctr &= ~HAL_CHCTR_DCEN; \ |
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235 *HAL_CHCTR = chctr; \ |
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236 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \ |
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237 chctr |= HAL_CHCTR_DCINV; \ |
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238 *HAL_CHCTR = chctr; \ |
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239 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \ |
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240 *HAL_CHCTR = chctr1; \ |
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241 } |
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242 |
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243 // Synchronize the contents of the cache with memory. |
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244 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS ) |
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245 |
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246 // Set the data cache refill burst size |
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247 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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248 |
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249 // Set the data cache write mode |
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250 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \ |
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251 { \ |
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252 CYG_ADDRWORD chctr; \ |
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253 chctr = *HAL_CHCTR; \ |
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254 HAL_DCACHE_DISABLE(); \ |
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255 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \ |
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256 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \ |
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257 *HAL_CHCTR = chctr; \ |
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258 } |
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259 |
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260 #define HAL_DCACHE_WRITEBACK_MODE 0 |
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261 #define HAL_DCACHE_WRITETHRU_MODE 1 |
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262 |
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263 // Load the contents of the given address range into the data cache |
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264 // and then lock the cache so that it stays there. |
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265 //#define HAL_DCACHE_LOCK(_base_, _size_) |
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266 |
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267 // Undo a previous lock operation |
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268 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
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269 |
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270 // Unlock entire cache |
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271 //#define HAL_DCACHE_UNLOCK_ALL() |
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272 |
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273 //----------------------------------------------------------------------------- |
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274 // Data cache line control |
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275 |
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276 // Allocate cache lines for the given address range without reading its |
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277 // contents from memory. |
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278 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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279 |
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280 // Write dirty cache lines to memory and invalidate the cache entries |
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281 // for the given address range. |
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282 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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283 |
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284 // Invalidate cache lines in the given range without writing to memory. |
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285 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
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286 |
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287 // Write dirty cache lines to memory for the given address range. |
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288 #define HAL_DCACHE_STORE( _base_ , _size_ ) \ |
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289 { \ |
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290 volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0; \ |
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291 volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1; \ |
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292 int i; \ |
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293 register CYG_ADDRWORD chctr; \ |
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294 chctr = *HAL_CHCTR; \ |
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295 HAL_DCACHE_DISABLE(); \ |
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296 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \ |
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297 \ |
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298 way0 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \ |
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299 way1 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \ |
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300 for( i = 0; i < (_size_) ; i += HAL_DCACHE_LINE_SIZE ) \ |
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301 { \ |
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302 *(CYG_ADDRWORD *)way0 = 0; \ |
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303 *(CYG_ADDRWORD *)way1 = 0; \ |
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304 way0 += HAL_DCACHE_LINE_SIZE; \ |
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305 way1 += HAL_DCACHE_LINE_SIZE; \ |
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306 } \ |
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307 *HAL_CHCTR = chctr; \ |
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308 } |
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309 |
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310 // Preread the given range into the cache with the intention of reading |
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311 // from it later. |
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312 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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313 |
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314 // Preread the given range into the cache with the intention of writing |
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315 // to it later. |
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316 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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317 |
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318 // Allocate and zero the cache lines associated with the given range. |
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319 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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320 |
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321 //----------------------------------------------------------------------------- |
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322 // Global control of Instruction cache |
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323 |
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324 // Enable the instruction cache |
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325 #define HAL_ICACHE_ENABLE() \ |
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326 { \ |
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327 CYG_ADDRWORD chctr = *HAL_CHCTR; \ |
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328 chctr |= HAL_CHCTR_ICEN; \ |
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329 *HAL_CHCTR = chctr; \ |
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330 } |
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331 |
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332 // Disable the instruction cache |
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333 #define HAL_ICACHE_DISABLE() \ |
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334 { \ |
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335 CYG_ADDRWORD chctr = *HAL_CHCTR; \ |
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336 chctr &= ~HAL_CHCTR_ICEN; \ |
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337 *HAL_CHCTR = chctr; \ |
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338 } |
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339 |
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340 // Invalidate the entire cache |
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341 #define HAL_ICACHE_INVALIDATE_ALL() \ |
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342 { \ |
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343 CYG_ADDRWORD chctr, chctr1; \ |
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344 chctr1 = *HAL_CHCTR; \ |
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345 HAL_ICACHE_DISABLE(); \ |
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346 while( *HAL_CHCTR & HAL_CHCTR_ICBUSY ); \ |
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347 chctr = *HAL_CHCTR; \ |
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348 chctr |= HAL_CHCTR_ICINV; \ |
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349 *HAL_CHCTR = chctr; \ |
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350 while( *HAL_CHCTR & HAL_CHCTR_ICBUSY ); \ |
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351 *HAL_CHCTR = chctr1; \ |
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352 } |
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353 |
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354 // Synchronize the contents of the cache with memory. |
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355 #define HAL_ICACHE_SYNC() |
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356 |
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357 // Set the instruction cache refill burst size |
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358 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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359 |
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360 // Load the contents of the given address range into the instruction cache |
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361 // and then lock the cache so that it stays there. |
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362 //#define HAL_ICACHE_LOCK(_base_, _size_) |
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363 |
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364 // Undo a previous lock operation |
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365 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
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366 |
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367 // Unlock entire cache |
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368 //#define HAL_ICACHE_UNLOCK_ALL() |
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369 |
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370 //----------------------------------------------------------------------------- |
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371 // Instruction cache line control |
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372 |
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373 // Invalidate cache lines in the given range without writing to memory. |
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374 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
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375 |
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376 #endif |
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377 |
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378 //----------------------------------------------------------------------------- |
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379 // Check that a supported configuration has actually defined some macros. |
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380 |
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381 #ifndef HAL_DCACHE_ENABLE |
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382 |
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383 #error Unsupported MN10300 configuration |
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384 |
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385 #endif |
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386 |
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387 //----------------------------------------------------------------------------- |
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388 #endif // ifndef CYGONCE_HAL_CACHE_H |
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389 // End of hal_cache.h |
