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1 #ifndef CYGONCE_HAL_CACHE_H |
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2 #define CYGONCE_HAL_CACHE_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // hal_cache.h |
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7 // |
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8 // HAL cache control API |
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9 // |
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10 //============================================================================= |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //============================================================================= |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1998-02-17 |
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38 // Purpose: Cache control API |
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39 // Description: The macros defined here provide the HAL APIs for handling |
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40 // cache control operations. |
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41 // Usage: |
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42 // #include <cyg/hal/hal_cache.h> |
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43 // ... |
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44 // |
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45 // |
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46 //####DESCRIPTIONEND#### |
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47 // |
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48 //============================================================================= |
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49 |
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50 #include <pkgconf/hal.h> |
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51 #include <cyg/infra/cyg_type.h> |
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52 |
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53 #include <cyg/hal/ppc_regs.h> |
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54 |
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55 //============================================================================= |
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56 // Memory mapping |
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57 typedef struct { |
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58 CYG_ADDRESS virtual_addr; |
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59 CYG_ADDRESS physical_addr; |
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60 cyg_int32 size; |
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61 cyg_uint8 flags; |
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62 } cyg_memdesc_t; |
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63 |
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64 #define CYGARC_MEMDESC_CI 1 // cache inhibit |
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65 #define CYGARC_MEMDESC_GUARDED 2 // guarded |
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66 |
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67 //============================================================================= |
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68 // PowerPC simulator |
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69 |
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70 #ifdef CYG_HAL_POWERPC_SIM |
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71 |
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72 //----------------------------------------------------------------------------- |
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73 // Cache dimensions |
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74 |
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75 // Data cache |
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76 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
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77 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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78 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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79 |
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80 // Instruction cache |
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81 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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82 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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83 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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84 |
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85 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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86 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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87 |
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88 //----------------------------------------------------------------------------- |
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89 // Global control of data cache |
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90 |
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91 // Enable the data cache |
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92 #define HAL_DCACHE_ENABLE() |
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93 |
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94 // Disable the data cache |
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95 #define HAL_DCACHE_DISABLE() |
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96 |
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97 // Invalidate the entire cache |
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98 #define HAL_DCACHE_INVALIDATE_ALL() |
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99 |
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100 // Synchronize the contents of the cache with memory. |
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101 #define HAL_DCACHE_SYNC() |
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102 |
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103 // Query the state of the data cache |
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104 #define HAL_DCACHE_IS_ENABLED(_state_) \ |
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105 CYG_MACRO_START \ |
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106 (_state_) = 0; \ |
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107 CYG_MACRO_END |
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108 |
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109 // Set the data cache refill burst size |
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110 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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111 |
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112 // Set the data cache write mode |
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113 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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114 |
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115 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
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116 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
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117 |
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118 // Load the contents of the given address range into the data cache |
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119 // and then lock the cache so that it stays there. |
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120 //#define HAL_DCACHE_LOCK(_base_, _size_) |
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121 |
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122 // Undo a previous lock operation |
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123 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
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124 |
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125 // Unlock entire cache |
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126 //#define HAL_DCACHE_UNLOCK_ALL() |
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127 |
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128 //----------------------------------------------------------------------------- |
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129 // Data cache line control |
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130 |
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131 // Allocate cache lines for the given address range without reading its |
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132 // contents from memory. |
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133 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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134 |
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135 // Write dirty cache lines to memory and invalidate the cache entries |
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136 // for the given address range. |
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137 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
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138 |
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139 // Invalidate cache lines in the given range without writing to memory. |
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140 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
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141 |
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142 // Write dirty cache lines to memory for the given address range. |
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143 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
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144 |
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145 // Preread the given range into the cache with the intention of reading |
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146 // from it later. |
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147 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
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148 |
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149 // Preread the given range into the cache with the intention of writing |
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150 // to it later. |
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151 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
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152 |
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153 // Allocate and zero the cache lines associated with the given range. |
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154 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
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155 |
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156 //----------------------------------------------------------------------------- |
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157 // Global control of Instruction cache |
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158 |
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159 // Enable the instruction cache |
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160 #define HAL_ICACHE_ENABLE() |
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161 |
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162 // Disable the instruction cache |
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163 #define HAL_ICACHE_DISABLE() |
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164 |
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165 // Invalidate the entire cache |
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166 #define HAL_ICACHE_INVALIDATE_ALL() |
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167 |
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168 // Synchronize the contents of the cache with memory. |
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169 #define HAL_ICACHE_SYNC() |
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170 |
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171 // Query the state of the instruction cache |
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172 #define HAL_ICACHE_IS_ENABLED(_state_) \ |
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173 CYG_MACRO_START \ |
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174 (_state_) = 0; \ |
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175 CYG_MACRO_END |
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176 |
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177 // Set the instruction cache refill burst size |
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178 //#define HAL_ICACHE_BURST_SIZE(_size_) |
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179 |
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180 // Load the contents of the given address range into the instruction cache |
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181 // and then lock the cache so that it stays there. |
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182 //#define HAL_ICACHE_LOCK(_base_, _size_) |
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183 |
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184 // Undo a previous lock operation |
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185 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
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186 |
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187 // Unlock entire cache |
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188 //#define HAL_ICACHE_UNLOCK_ALL() |
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189 |
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190 //----------------------------------------------------------------------------- |
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191 // Instruction cache line control |
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192 |
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193 // Invalidate cache lines in the given range without writing to memory. |
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194 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
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195 |
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196 |
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197 //============================================================================= |
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198 // Motorola MPC8xx |
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199 |
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200 #elif defined(CYG_HAL_POWERPC_MPC8xx) |
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201 |
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202 //----------------------------------------------------------------------------- |
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203 // Cache dimensions |
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204 |
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205 #if defined(CYG_HAL_POWERPC_MPC860) |
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206 // Data cache |
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207 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
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208 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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209 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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210 |
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211 // Instruction cache |
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212 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
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213 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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214 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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215 #endif // defined(CYG_HAL_POWERPC_MPC860) |
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216 |
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217 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) |
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218 // Data cache |
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219 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes |
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220 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
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221 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
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222 |
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223 // Instruction cache |
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224 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes |
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225 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
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226 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
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227 #endif // defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) |
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228 |
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229 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
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230 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
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231 |
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232 //----------------------------------------------------------------------------- |
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233 // Global control of data cache |
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234 |
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235 // Enable the data cache |
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236 #define HAL_DCACHE_ENABLE() \ |
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237 asm volatile ("sync;" \ |
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238 "mtspr %0, %1;" \ |
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239 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) |
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240 |
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241 // Disable the data cache |
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242 #define HAL_DCACHE_DISABLE() \ |
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243 asm volatile ("sync;" \ |
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244 "mtspr %0, %1;" \ |
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245 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) |
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246 |
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247 // Invalidate the entire cache |
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248 // Note: Any locked lines will not be invalidated. |
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249 #define HAL_DCACHE_INVALIDATE_ALL() \ |
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250 asm volatile ("sync;" \ |
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251 "mtspr %0, %1;" \ |
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252 : : "I" (CYGARC_REG_DC_CST), \ |
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253 "r" (CYGARC_REG_DC_CMD_IA)) |
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254 |
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255 // Synchronize the contents of the cache with memory. |
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256 #define HAL_DCACHE_SYNC() \ |
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257 CYG_MACRO_START \ |
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258 cyg_int32 i; \ |
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259 for (i = 0; i < HAL_DCACHE_SETS; i++){ \ |
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260 asm volatile ("sync;" \ |
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261 "mtspr %0, %2;" \ |
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262 "mtspr %1, %4;" \ |
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263 "mtspr %0, %3;" \ |
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264 "mtspr %1, %4;" \ |
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265 : /* no output */ \ |
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266 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ |
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267 /* %1 */ "I" (CYGARC_REG_DC_CST), \ |
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268 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ |
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269 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ |
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270 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ |
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271 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ |
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272 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ |
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273 } \ |
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274 CYG_MACRO_END |
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275 |
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276 // Query the state of the data cache |
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277 #define HAL_DCACHE_IS_ENABLED(_state_) \ |
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278 asm volatile ("mfspr %0, %1;" \ |
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279 "rlwinm %0,%0,1,31,31;" \ |
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280 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) |
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281 |
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282 // Set the data cache refill burst size |
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283 //#define HAL_DCACHE_BURST_SIZE(_size_) |
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284 |
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285 // Set the data cache write mode |
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286 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
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287 |
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288 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
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289 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
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290 |
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291 |
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292 // Load the contents of the given address range into the data cache |
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293 // and then lock the cache so that it stays there. |
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294 |
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295 // Restrictions: This implementation only allows a single area to be |
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296 // locked at any one time. This area must be 2kB or less in size. |
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297 |
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298 // Implementation: Flush entire cache, then invalidate it. This |
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299 // ensures that the fetched data go into way0. |
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300 |
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301 #define HAL_DCACHE_LOCK(_base_, _size_) \ |
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302 CYG_MACRO_START \ |
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303 cyg_int32 __scratch; \ |
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304 cyg_uint32 __base = (cyg_uint32)(_base_); \ |
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305 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ |
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306 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ |
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307 HAL_DCACHE_DISABLE(); \ |
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308 HAL_DCACHE_SYNC (); \ |
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309 HAL_DCACHE_INVALIDATE_ALL (); \ |
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310 HAL_DCACHE_ENABLE(); \ |
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311 do { \ |
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312 asm volatile ("lbz %0,0(%1);" \ |
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313 "sync;" \ |
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314 "mtspr %2, %4;" \ |
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315 "mtspr %3, %5;" \ |
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316 : /* %0 */ "=r" (__scratch) \ |
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317 : /* %1 */ "b" (__base), \ |
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318 /* %2 */ "I" (CYGARC_REG_DC_ADR), \ |
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319 /* %3 */ "I" (CYGARC_REG_DC_CST), \ |
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320 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ |
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321 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ |
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322 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ |
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323 __l++; \ |
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324 __base += HAL_DCACHE_LINE_SIZE; \ |
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325 } while (__count--); \ |
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326 CYG_MACRO_END |
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327 |
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328 |
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329 // Undo a previous lock operation |
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330 |
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331 // Implementation: Unlocks entire cache. |
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332 |
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333 #define HAL_DCACHE_UNLOCK(_base_, _size_) \ |
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334 HAL_DCACHE_UNLOCK_ALL() |
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335 |
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336 |
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337 // Unlock entire cache |
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338 #define HAL_DCACHE_UNLOCK_ALL() \ |
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339 CYG_MACRO_START \ |
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340 asm volatile ("sync;" \ |
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341 "mtspr %0, %1;" \ |
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342 : : "I" (CYGARC_REG_DC_CST), \ |
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343 "r" (CYGARC_REG_DC_CMD_UA)); \ |
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344 CYG_MACRO_END |
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345 |
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346 |
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347 |
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348 //----------------------------------------------------------------------------- |
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349 // Data cache line control |
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350 |
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351 // Allocate cache lines for the given address range without reading its |
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352 // contents from memory. |
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353 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
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354 |
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355 // Write dirty cache lines to memory and invalidate the cache entries |
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356 // for the given address range. |
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357 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ |
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358 CYG_MACRO_START \ |
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359 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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360 cyg_int32 __size = (cyg_int32) (_size_); \ |
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361 while (__size > 0) { \ |
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362 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ |
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363 __base += HAL_DCACHE_LINE_SIZE; \ |
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364 __size -= HAL_DCACHE_LINE_SIZE; \ |
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365 } \ |
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366 CYG_MACRO_END |
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367 |
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368 // Invalidate cache lines in the given range without writing to memory. |
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369 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ |
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370 CYG_MACRO_START \ |
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371 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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372 cyg_int32 __size = (cyg_int32) (_size_); \ |
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373 while (__size > 0) { \ |
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374 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ |
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375 __base += HAL_DCACHE_LINE_SIZE; \ |
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376 __size -= HAL_DCACHE_LINE_SIZE; \ |
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377 } \ |
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378 CYG_MACRO_END |
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379 |
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380 // Write dirty cache lines to memory for the given address range. |
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381 #define HAL_DCACHE_STORE( _base_ , _size_ ) \ |
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382 CYG_MACRO_START \ |
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383 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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384 cyg_int32 __size = (cyg_int32) (_size_); \ |
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385 while (__size > 0) { \ |
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386 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ |
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387 __base += HAL_DCACHE_LINE_SIZE; \ |
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388 __size -= HAL_DCACHE_LINE_SIZE; \ |
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389 } \ |
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390 CYG_MACRO_END |
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391 |
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392 // Preread the given range into the cache with the intention of reading |
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393 // from it later. |
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394 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ |
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395 CYG_MACRO_START \ |
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396 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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397 cyg_int32 __size = (cyg_int32) (_size_); \ |
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398 while (__size > 0) { \ |
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399 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ |
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400 __base += HAL_DCACHE_LINE_SIZE; \ |
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401 __size -= HAL_DCACHE_LINE_SIZE; \ |
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402 } \ |
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403 CYG_MACRO_END |
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404 |
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405 // Preread the given range into the cache with the intention of writing |
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406 // to it later. |
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407 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ |
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408 CYG_MACRO_START \ |
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409 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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410 cyg_int32 __size = (cyg_int32) (_size_); \ |
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411 while (__size > 0) { \ |
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412 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ |
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413 __base += HAL_DCACHE_LINE_SIZE; \ |
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414 __size -= HAL_DCACHE_LINE_SIZE; \ |
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415 } \ |
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416 CYG_MACRO_END |
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0
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417 |
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418 // Allocate and zero the cache lines associated with the given range. |
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2
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419 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \ |
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420 CYG_MACRO_START \ |
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421 cyg_uint32 __base = (cyg_uint32) (_base_); \ |
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422 cyg_int32 __size = (cyg_int32) (_size_); \ |
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423 while (__size > 0) { \ |
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424 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ |
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425 __base += HAL_DCACHE_LINE_SIZE; \ |
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426 __size -= HAL_DCACHE_LINE_SIZE; \ |
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427 } \ |
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428 CYG_MACRO_END |
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0
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429 |
|
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430 //----------------------------------------------------------------------------- |
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431 // Global control of Instruction cache |
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432 |
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433 // Enable the instruction cache |
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2
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434 #define HAL_ICACHE_ENABLE() \ |
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435 asm volatile ("isync;" \ |
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436 "mtspr %0, %1;" \ |
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437 "isync" \ |
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438 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) |
|
0
|
439 |
|
|
440 // Disable the instruction cache |
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2
|
441 #define HAL_ICACHE_DISABLE() \ |
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442 asm volatile ("isync;" \ |
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443 "mtspr %0, %1;" \ |
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444 "isync" \ |
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445 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) |
|
0
|
446 |
|
|
447 // Invalidate the entire cache |
|
2
|
448 #define HAL_ICACHE_INVALIDATE_ALL() \ |
|
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449 asm volatile ("isync;" \ |
|
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450 "mtspr %0, %1;" \ |
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451 "isync" \ |
|
|
452 : : "I" (CYGARC_REG_IC_CST), \ |
|
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453 "r" (CYGARC_REG_IC_CMD_IA)) |
|
0
|
454 |
|
|
455 // Synchronize the contents of the cache with memory. |
|
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456 #define HAL_ICACHE_SYNC() |
|
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457 |
|
2
|
458 // Query the state of the instruction cache |
|
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459 #define HAL_ICACHE_IS_ENABLED(_state_) \ |
|
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460 asm volatile ("mfspr %0, %1;" \ |
|
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461 "rlwinm %0,%0,1,31,31;" \ |
|
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462 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) |
|
0
|
463 |
|
|
464 // Set the instruction cache refill burst size |
|
|
465 //#define HAL_ICACHE_BURST_SIZE(_size_) |
|
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466 |
|
2
|
467 |
|
0
|
468 // Load the contents of the given address range into the instruction cache |
|
|
469 // and then lock the cache so that it stays there. |
|
2
|
470 |
|
|
471 // Restrictions: This implementation only allows a single area to be |
|
|
472 // locked at any one time. This area must be 2kB or less in size. |
|
|
473 |
|
|
474 // Implementation: Flush entire cache, then invalidate it. This |
|
|
475 // ensures that the fetched data go into way0. |
|
|
476 |
|
|
477 #define HAL_ICACHE_LOCK(_base_, _size_) \ |
|
|
478 CYG_MACRO_START \ |
|
|
479 unsigned long __base = \ |
|
|
480 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ |
|
|
481 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ |
|
|
482 do { \ |
|
|
483 asm volatile ("mtspr %0, %2;" \ |
|
|
484 "mtspr %1, %3;" \ |
|
|
485 "isync;" \ |
|
|
486 : /* no output */ \ |
|
|
487 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ |
|
|
488 /* %1 */ "I" (CYGARC_REG_IC_CST), \ |
|
|
489 /* %2 */ "r" (__base), \ |
|
|
490 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ |
|
|
491 __base += HAL_ICACHE_LINE_SIZE; \ |
|
|
492 } while (__count--); \ |
|
|
493 CYG_MACRO_END |
|
0
|
494 |
|
|
495 // Undo a previous lock operation |
|
2
|
496 |
|
|
497 // Implementation: Unlocks entire cache. |
|
|
498 #define HAL_ICACHE_UNLOCK(_base_, _size_) \ |
|
|
499 HAL_ICACHE_UNLOCK_ALL() |
|
|
500 |
|
|
501 // Unlock entire cache |
|
|
502 #define HAL_ICACHE_UNLOCK_ALL() \ |
|
|
503 CYG_MACRO_START \ |
|
|
504 asm volatile ("sync;" \ |
|
|
505 "mtspr %0, %1;" \ |
|
|
506 : : "I" (CYGARC_REG_IC_CST), \ |
|
|
507 "r" (CYGARC_REG_IC_CMD_UA)); \ |
|
|
508 CYG_MACRO_END |
|
0
|
509 |
|
|
510 //----------------------------------------------------------------------------- |
|
|
511 // Instruction cache line control |
|
|
512 |
|
|
513 // Invalidate cache lines in the given range without writing to memory. |
|
|
514 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
|
|
515 |
|
|
516 #endif |
|
|
517 |
|
|
518 //----------------------------------------------------------------------------- |
|
|
519 #endif // ifndef CYGONCE_HAL_CACHE_H |
|
|
520 // End of hal_cache.h |
