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1 ##========================================================================== |
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2 ## |
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3 ## vectors.S |
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4 ## |
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5 ## PowerPC exception vectors |
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6 ## |
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7 ##========================================================================== |
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8 #####COPYRIGHTBEGIN#### |
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9 # |
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10 # ------------------------------------------- |
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11 # The contents of this file are subject to the Cygnus eCos Public License |
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12 # Version 1.0 (the "License"); you may not use this file except in |
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13 # compliance with the License. You may obtain a copy of the License at |
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14 # http://sourceware.cygnus.com/ecos |
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15 # |
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16 # Software distributed under the License is distributed on an "AS IS" |
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 # License for the specific language governing rights and limitations under |
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19 # the License. |
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20 # |
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21 # The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 # September 30, 1998. |
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23 # |
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24 # The Initial Developer of the Original Code is Cygnus. Portions created |
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25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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26 # ------------------------------------------- |
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27 # |
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28 #####COPYRIGHTEND#### |
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29 ##========================================================================== |
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30 #######DESCRIPTIONBEGIN#### |
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31 ## |
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32 ## Author(s): nickg, jskov |
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33 ## Contributors: nickg, jskov |
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34 ## Date: 1999-02-20 |
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35 ## Purpose: PowerPC exception vectors |
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36 ## Description: This file defines the code placed into the exception |
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37 ## vectors. It also contains the first level default VSRs |
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38 ## that save and restore state for both exceptions and |
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39 ## interrupts. |
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40 ## |
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41 ######DESCRIPTIONEND#### |
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42 ## |
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43 ##========================================================================== |
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44 |
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45 #include <pkgconf/hal.h> |
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46 |
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47 #ifdef CYGPKG_KERNEL |
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48 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT |
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49 #endif |
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50 |
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51 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
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52 #include "cyg/hal/ppc_regs.h" |
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53 #include "cyg/hal/ppc.inc" |
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54 |
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55 #define FUNC_START(name) \ |
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56 .type name,@function; \ |
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57 .globl name; \ |
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58 name: |
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59 |
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60 #=========================================================================== |
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61 |
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62 .file "vectors.S" |
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63 |
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64 .extern hal_interrupt_handlers |
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65 .extern hal_interrupt_data |
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66 .extern hal_interrupt_objects |
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67 |
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68 .extern cyg_instrument |
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69 |
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70 .extern hal_hardware_init |
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71 |
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72 #=========================================================================== |
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73 # MSR initialization value |
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74 # zero all bits except: |
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75 # FP = floating point available |
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76 # ME = machine check enabled |
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77 # IP = vectors at 0xFFFxxxxx (ROM startup only) |
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78 # IR = instruction address translation |
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79 # DR = data address translation |
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80 # RI = recoverable interrupt |
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81 |
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82 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) |
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83 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) |
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84 #define CYG_MSR (CYG_MSR_COMMON | MSR_IP) |
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85 #endif |
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86 #ifdef CYG_HAL_STARTUP_RAM |
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87 #define CYG_MSR CYG_MSR_COMMON |
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88 #endif |
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89 #ifdef CYG_HAL_POWERPC_SIM |
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90 # When building for SIM, don't enable MMU -- it's not needed since caches |
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91 # are disabled, and there is a runtime simulation overhead. |
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92 #undef CYG_MSR |
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93 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR)) |
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94 #endif |
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95 |
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96 #=========================================================================== |
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97 # If the following option is enabled, we only save registers up to R12. |
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98 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do |
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99 # not need to save them when calling C functions. |
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100 |
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101 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT |
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102 |
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103 #define MAX_SAVE_REG 12 |
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104 |
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105 #else |
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106 |
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107 #define MAX_SAVE_REG 31 |
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108 |
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109 #endif |
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110 |
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111 #=========================================================================== |
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112 # Start by defining the exceptions vectors that must be placed at |
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113 # locations 0xFFF00000 and 0x00000000. The following code will normally |
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114 # be located at 0xFFF00000 in the ROM. It may optionally be copied out |
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115 # to 0x00000000 if we want to use the RAM vectors. For this reason this code |
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116 # MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may |
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117 # be placed at 0x00000000 during loading. |
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118 |
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119 .section ".vectors","ax" |
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120 |
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121 #--------------------------------------------------------------------------- |
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122 # Unused first vector. |
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123 |
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124 rom_vectors: |
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125 lwi r3,_start |
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126 mtlr r3 |
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127 blr |
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128 |
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129 .byte 0x11 |
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130 .byte 0x22 |
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131 .byte 0x33 |
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132 .byte 0x44 |
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133 |
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134 #--------------------------------------------------------------------------- |
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135 # Reset vector. |
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136 |
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137 .p2align 8 |
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138 .globl reset_vector |
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139 |
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140 reset_vector: |
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141 lwi r3,_start |
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142 mtlr r3 |
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143 blr |
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144 |
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145 #--------------------------------------------------------------------------- |
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146 # Macro for generating an exception vector service routine |
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147 |
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148 .macro exception_vector name |
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149 .p2align 8 |
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150 .globl __exception_\name |
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151 __exception_\name: |
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152 mtspr SPRG1,r3 # stash some work registers away |
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153 mtspr SPRG2,r4 |
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154 mtspr SPRG3,r5 |
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155 mfcr r4 # stash CR |
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156 li r5,__exception_\name@L # load low half of vector address |
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157 srwi r5,r5,6 # shift right by 6 |
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158 lwi r3,hal_vsr_table # table base |
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159 lwzx r3,r3,r5 # address of vsr |
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160 mflr r5 # save link register |
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161 mtlr r3 # put vsr address into it |
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162 li r3,__exception_\name@L # reload low half of vector address |
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163 blr # go to common code |
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164 .endm |
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165 |
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166 #--------------------------------------------------------------------------- |
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167 # Define the exception vectors. |
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168 |
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169 # These are the architecture defined vectors that |
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170 # are always present. |
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171 |
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172 exception_vector machine_check |
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173 exception_vector data_storage |
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174 exception_vector instruction_storage |
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175 exception_vector external |
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176 exception_vector alignment |
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177 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) \ |
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178 || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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179 exception_vector program |
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180 #else |
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181 # Provide a crude hook to the GDB exception handler in ROM. |
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182 # This allows the testing infrastructure to rely on breakpoints |
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183 # to terminate tests, even when the tests are compiled without |
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184 # the GDB stub. |
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185 # It is _not_ a generic solution to the problem; in particular it |
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186 # is not possible to continue after a breakpoint is hit. |
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187 .p2align 8 |
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188 .globl __exception_program |
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189 __exception_program: |
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190 bl _init_CPU # disable caches. |
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191 lwi r3,0xfff00700 # address of trap handler |
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192 mtlr r3 # in ROM. |
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193 blr # jump to it. |
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194 |
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195 #endif |
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196 exception_vector floatingpoint_unavailable |
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197 exception_vector decrementer |
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198 exception_vector reserved_00a00 |
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199 exception_vector reserved_00b00 |
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200 exception_vector system_call |
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201 exception_vector trace |
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202 exception_vector floatingpoint_assist |
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203 exception_vector reserved_00f00 |
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204 |
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205 # There are some additional vectors defined |
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206 # on various implementations. |
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207 |
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208 #ifdef CYG_HAL_POWERPC_MPC8xx |
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209 # MPC8xx vectors |
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210 |
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211 exception_vector software_emu |
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212 exception_vector instruction_tlb_miss |
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213 exception_vector data_tlb_miss |
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214 exception_vector instruction_tlb_error |
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215 exception_vector data_tlb_error |
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216 exception_vector reserved_01500 |
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217 exception_vector reserved_01600 |
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218 exception_vector reserved_01700 |
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219 exception_vector reserved_01800 |
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220 exception_vector reserved_01900 |
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221 exception_vector reserved_01A00 |
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222 exception_vector reserved_01B00 |
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223 exception_vector data_breakpoint |
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224 exception_vector instruction_breakpoint |
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225 exception_vector peripheral_breakpoint |
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226 exception_vector NMI_port |
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227 |
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228 #endif |
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229 rom_vectors_end: |
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230 |
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231 #=========================================================================== |
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232 # Real startup code. We jump here from the various reset vectors to set up |
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233 # the world. |
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234 |
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235 .text |
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236 .globl _start |
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237 |
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238 _start: |
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239 # Initialize CPU |
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240 bl _init_CPU |
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241 |
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242 #ifdef CYG_HAL_POWERPC_MPC8xx |
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243 # Disable special MPC8xx "development support" which |
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244 # suppresses trace exceptions. The CPU seems to hang, not |
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245 # executing from offset 0x1e00(?) as expected. |
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246 li r3,0 |
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247 mtspr DER, r3 |
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248 #endif |
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249 |
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250 # Set up global offset table |
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251 lwi r2,_GLOBAL_OFFSET_TABLE_ |
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252 |
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253 # set up time base register to zero |
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254 xor r3,r3,r3 |
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255 mtspr TBL_W,r3 |
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256 xor r4,r4,r4 |
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257 mtspr TBU_W,r4 |
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258 |
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259 # Call platform specific hardware initialization |
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260 # This may include memory controller initialization. It is not |
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261 # safe to access RAM until after this point. |
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262 bl hal_hardware_init |
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263 |
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264 # set up stack |
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265 lwi sp,__interrupt_stack |
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266 mtspr SPRG0,sp # save in sprg0 for later use |
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267 |
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268 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) |
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269 |
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270 # Copy data from ROM to ram |
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271 lwi r3,__rom_data_start # r3 = rom start |
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272 lwi r4,__ram_data_start # r4 = ram start |
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273 lwi r5,__ram_data_end # r5 = ram end |
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274 |
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275 cmplw r4,r5 # skip if no data |
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276 beq 2f |
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277 |
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278 1: |
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279 lwz r0,0(r3) # get word from ROM |
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280 stw r0,0(r4) # store in RAM |
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281 addi r3,r3,4 # increment by 1 word |
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282 addi r4,r4,4 # increment by 1 word |
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283 cmplw r4,r5 # compare |
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284 blt 1b # loop if not yet done |
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285 2: |
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286 |
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287 #ifdef CYG_HAL_POWERPC_COPY_VECTORS |
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288 # Copy RAM exception vectors from ROM to RAM |
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289 lwi r3,rom_vectors # r3 = rom start |
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290 lwi r4,0 # r4 = ram start |
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291 lwi r5,rom_vectors_end # r5 = rom end |
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292 |
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293 cmplw r3,r5 # skip if no vectors |
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294 beq 2f |
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295 |
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296 1: |
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297 lwz r0,0(r3) # get word from ROM |
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298 stw r0,0(r4) # store in RAM |
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299 addi r3,r3,4 # increment by 1 word |
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300 addi r4,r4,4 # increment by 1 word |
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301 cmplw r3,r5 # compare |
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302 blt 1b # loop if not yet done |
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303 2: |
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304 #endif |
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305 |
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306 #endif |
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307 |
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308 # clear BSS |
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309 .extern __bss_start |
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310 .extern __bss_end |
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311 lwi r3,__bss_start # r3 = start |
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312 lwi r4,__bss_end # r4 = end |
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313 li r0,0 # r0 = 0 |
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314 cmplw r3,r4 # skip if no bss |
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315 beq 2f |
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316 |
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317 1: stw r0,0(r3) # store zero |
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318 addi r3,r3,4 # increment by 1 word |
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319 cmplw r3,r4 # compare |
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320 blt 1b # loop if not yet done |
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321 2: |
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322 |
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323 # clear SBSS |
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324 .extern __sbss_start |
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325 .extern __sbss_end |
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326 lwi r3,__sbss_start # r3 = start |
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327 lwi r4,__sbss_end # r4 = end |
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328 cmplw r3,r4 # skip if no sbss |
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329 beq 2f |
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330 |
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331 1: stw r0,0(r3) # store zero |
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332 addi r3,r3,4 # increment by 1 word |
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333 cmplw r3,r4 # compare |
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334 blt 1b # loop if not yet done |
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335 2: |
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336 |
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337 # It is now safe to call C functions which may rely on initialized |
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338 # data. |
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339 |
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340 # Set up stack for calls to C code. |
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341 subi sp,sp,12 # make space on stack |
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342 li r0,0 |
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343 stw r0,0(sp) # clear back chain |
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344 stw r0,8(sp) # zero return pc |
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345 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame |
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346 |
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347 # Initialize MMU. |
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348 .extern hal_MMU_init |
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349 bl hal_MMU_init |
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350 |
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351 # Enable MMU it so we can safely enable caches. |
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352 lwi r3,CYG_MSR |
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353 sync |
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354 mtmsr r3 |
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355 sync |
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356 |
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357 # Enable caches |
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358 .extern hal_enable_caches |
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359 bl hal_enable_caches |
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360 |
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361 # call c++ constructors |
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362 .extern cyg_hal_invoke_constructors |
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363 bl cyg_hal_invoke_constructors |
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364 |
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365 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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366 .extern initialize_stub |
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367 bl initialize_stub |
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368 #endif |
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369 |
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370 .extern cyg_start |
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371 bl cyg_start # call cyg_start |
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372 9: |
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373 b 9b # if we return, loop |
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374 |
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375 #--------------------------------------------------------------------------- |
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376 # This code handles the common part of all exception handlers. |
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377 # It saves the machine state onto the stack and then calls |
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378 # a "C" routine to do the rest of the work. This work may result |
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379 # in thread switches, and changes to the saved state. When we return |
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380 # here the saved state is restored and execution is continued. |
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381 |
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382 .text |
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383 |
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384 .extern __default_exception_vsr |
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385 __default_exception_vsr: |
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386 |
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387 # We come here with all register containing their |
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388 # pre-exception values except: |
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389 # R3 = ls 16 bits of vector address |
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390 # R4 = saved CR |
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391 # R5 = saved LR |
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392 # LR = VSR address |
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393 # SPRG1 = old R3 |
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394 # SPRG2 = old R4 |
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395 # SPRG3 = old R5 |
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396 # SRR0 = old PC |
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397 # SRR1 = old MSR and the exception cause (the POW state is lost!) |
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398 |
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399 subi r1,r1,ppc_exception_decrement |
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400 # leave space for registers and |
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401 # a safety margin |
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402 |
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403 # First, save away some registers |
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404 stw r3,ppcreg_vector(r1) # stash vector |
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405 stw r4,ppcreg_cr(r1) # stash CR |
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406 stw r5,ppcreg_lr(r1) # stash LR |
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407 |
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408 # Enable MMU. |
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409 lwi r3,CYG_MSR |
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410 sync |
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411 mtmsr r3 |
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412 sync |
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413 |
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414 mfspr r3,SPRG1 # save original R3 |
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415 stw r3,ppcreg_regs+3*4(r1) |
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416 mfspr r4,SPRG2 # save original R4 |
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417 stw r4,ppcreg_regs+4*4(r1) |
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418 mfspr r5,SPRG3 # save original R5 |
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419 stw r5,ppcreg_regs+5*4(r1) |
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420 |
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421 stw r0,ppcreg_regs(r1) # save R0 |
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422 stw r2,ppcreg_regs+2*4(r1) # save R2 |
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423 |
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424 mr r3,r1 # recreate original R1 |
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425 addi r3,r3,ppc_exception_decrement |
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426 stw r3,ppcreg_regs+1*4(r1) # and save it in state |
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427 |
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428 # Save registers r6..r12/r31 |
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429 .set _reg,6 |
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430 .rept MAX_SAVE_REG+1-6 |
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431 stw _reg,(ppcreg_regs+_reg*4)(r1) |
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432 .set _reg,_reg+1 |
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433 .endr |
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434 |
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435 # Save registers used in vsr (r14+r15) |
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436 stw r14,(ppcreg_regs+14*4)(r1) |
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437 stw r15,(ppcreg_regs+15*4)(r1) |
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438 |
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439 # get remaining CPU registers |
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440 mfxer r3 |
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441 mfctr r5 |
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442 mfdar r6 |
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443 mfdsisr r7 |
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444 mfpvr r8 |
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445 mfsrr0 r9 |
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446 mfsrr1 r10 |
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447 |
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448 # and store them |
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449 stw r3,ppcreg_xer(r1) |
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450 stw r5,ppcreg_ctr(r1) |
|
|
451 stw r6,ppcreg_dar(r1) |
|
|
452 stw r7,ppcreg_dsisr(r1) |
|
|
453 stw r8,ppcreg_pvr(r1) |
|
|
454 stw r9,ppcreg_pc(r1) |
|
|
455 stw r10,ppcreg_msr(r1) |
|
|
456 |
|
|
457 # The entire CPU state is now stashed on the stack, |
|
|
458 # call into C to do something with it. |
|
|
459 |
|
|
460 mr r3,sp # R3 = register dump |
|
|
461 |
|
|
462 subi sp,sp,ppc_stack_frame_size # make a null frame |
|
|
463 |
|
|
464 li r0,0 # R0 = 0 |
|
|
465 stw r0,0(sp) # backchain = 0 |
|
|
466 stw r0,8(sp) # return pc = 0 |
|
|
467 |
|
|
468 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame |
|
|
469 # where C code can save LR |
|
|
470 |
|
|
471 lwi r5,restore_state # get return link |
|
|
472 mtlr r5 # to link register |
|
|
473 |
|
2
|
474 .extern cyg_hal_exception_handler |
|
|
475 b cyg_hal_exception_handler # call C code, r3 = registers |
|
0
|
476 |
|
|
477 # When the call returns it will go to restore_state below. |
|
|
478 |
|
|
479 |
|
2
|
480 ##-------------------------------------------------------------------------- |
|
|
481 ## The following macros are defined depending on whether the Interrupt |
|
|
482 ## system is using isr tables or chaining, and depending on the interrupt |
|
|
483 ## controller in the system. |
|
|
484 |
|
|
485 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. |
|
|
486 |
|
|
487 #ifdef CYG_HAL_POWERPC_MPC8xx |
|
|
488 |
|
|
489 ## First level decoding of MPC8xx SIU interrupt controller. |
|
|
490 |
|
|
491 #define CYG_ISR_TABLE_SIZE 59 |
|
|
492 |
|
|
493 # decode the interrupt |
|
|
494 .macro decode_interrupt dreg,state |
|
|
495 lwz \dreg,ppcreg_vector(\state) # retrieve vector number, |
|
|
496 rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21 |
|
|
497 beq 0f # done if decrementer (vec 0) |
|
|
498 lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU |
|
|
499 lbz \dreg,0(\dreg) # vector. |
|
|
500 srwi \dreg,\dreg,2 |
|
|
501 addi \dreg,\dreg,1 # Skip decrementer vector |
|
|
502 0: stw \dreg,ppcreg_vector(\state) # update vector in state frame. |
|
|
503 slwi \dreg,\dreg,2 # convert to byte offset. |
|
|
504 .endm |
|
|
505 |
|
|
506 #else |
|
|
507 |
|
|
508 ## This is the simple version. No interrupt controller, ppcreg_vector |
|
|
509 ## is updated with the decoded interrupt vector. Isr tables/chaining |
|
|
510 ## use same interrupt decoder. |
|
|
511 ## Bit 21 biffers between decrementer (0) and external (1). |
|
|
512 |
|
|
513 #define CYG_ISR_TABLE_SIZE 2 |
|
|
514 |
|
|
515 # decode the interrupt |
|
|
516 .macro decode_interrupt dreg,state |
|
|
517 lwz \dreg,ppcreg_vector(\state) # retrieve vector number, |
|
|
518 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update |
|
|
519 stw \dreg,ppcreg_vector(\state) # vector in state frame. |
|
|
520 slwi \dreg,\dreg,2 # convert to word offset. |
|
|
521 .endm |
|
|
522 |
|
|
523 #endif |
|
|
524 |
|
|
525 #--------------------------------------------------------------------------- |
|
0
|
526 # Common interrupt handling code. |
|
|
527 |
|
|
528 .extern __default_interrupt_vsr |
|
|
529 __default_interrupt_vsr: |
|
|
530 |
|
|
531 # We come here with all register containing their |
|
|
532 # pre-exception values except: |
|
|
533 # R3 = ls 16 bits of vector address |
|
|
534 # R4 = saved CR |
|
|
535 # R5 = saved LR |
|
|
536 # LR = VSR address |
|
|
537 # SPRG1 = old R3 |
|
|
538 # SPRG2 = old R4 |
|
|
539 # SPRG3 = old R5 |
|
|
540 # SRR0 = old PC |
|
|
541 # SRR1 = old MSR |
|
|
542 |
|
|
543 |
|
|
544 subi r1,r1,ppc_exception_decrement |
|
|
545 # leave space for registers and |
|
|
546 # a safety margin |
|
|
547 |
|
|
548 stw r3,ppcreg_vector(r1) # stash vector |
|
|
549 stw r4,ppcreg_cr(r1) # stash CR |
|
|
550 stw r5,ppcreg_lr(r1) # stash LR |
|
|
551 |
|
2
|
552 # Enable MMU. |
|
|
553 lwi r3,CYG_MSR |
|
|
554 sync |
|
|
555 mtmsr r3 |
|
|
556 sync |
|
|
557 |
|
|
558 mfspr r3,SPRG1 # save original R3 |
|
0
|
559 stw r3,ppcreg_regs+3*4(r1) |
|
2
|
560 mfspr r4,SPRG2 # save original R4 |
|
0
|
561 stw r4,ppcreg_regs+4*4(r1) |
|
2
|
562 mfspr r5,SPRG3 # save original R5 |
|
0
|
563 stw r5,ppcreg_regs+5*4(r1) |
|
|
564 |
|
|
565 stw r0,ppcreg_regs(r1) # save R0 |
|
|
566 stw r2,ppcreg_regs+2*4(r1) # save R2 |
|
|
567 |
|
|
568 mr r3,r1 # recreate original R1 |
|
|
569 addi r3,r3,ppc_exception_decrement |
|
|
570 stw r3,ppcreg_regs+1*4(r1) # and save it in state |
|
|
571 |
|
2
|
572 # Save registers r6..r12/r31 |
|
0
|
573 .set _reg,6 |
|
|
574 .rept MAX_SAVE_REG+1-6 |
|
|
575 stw _reg,(ppcreg_regs+_reg*4)(r1) |
|
|
576 .set _reg,_reg+1 |
|
|
577 .endr |
|
|
578 |
|
2
|
579 # Save registers used in vsr (r14+r15) |
|
|
580 stw r14,(ppcreg_regs+14*4)(r1) |
|
|
581 stw r15,(ppcreg_regs+15*4)(r1) |
|
|
582 |
|
0
|
583 # get remaining CPU registers |
|
|
584 mfxer r3 |
|
|
585 mfctr r5 |
|
|
586 mfsrr0 r6 |
|
|
587 mfsrr1 r7 |
|
|
588 |
|
|
589 # and store them |
|
|
590 stw r3,ppcreg_xer(r1) |
|
|
591 stw r5,ppcreg_ctr(r1) |
|
|
592 stw r6,ppcreg_pc(r1) |
|
|
593 stw r7,ppcreg_msr(r1) |
|
|
594 |
|
|
595 # The entire CPU state is now stashed on the stack, |
|
|
596 # increment the scheduler lock and call the ISR |
|
|
597 # for this vector. |
|
|
598 |
|
|
599 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT |
|
2
|
600 .extern cyg_scheduler_sched_lock |
|
|
601 lwi r3,cyg_scheduler_sched_lock |
|
0
|
602 lwz r4,0(r3) |
|
|
603 addi r4,r4,1 |
|
|
604 stw r4,0(r3) |
|
|
605 #endif |
|
|
606 |
|
2
|
607 mr r14,sp # r14 = register dump |
|
0
|
608 |
|
|
609 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
|
|
610 lwi r3,__interrupt_stack # stack top |
|
|
611 lwi r4,__interrupt_stack_base # stack base |
|
|
612 sub. r5,sp,r4 # sp - base |
|
|
613 blt 1f # if < 0 - not on istack |
|
|
614 sub. r5,r3,sp # top - sp |
|
|
615 bgt 2f # if > 0 - already on istack |
|
|
616 |
|
|
617 1: mr sp,r3 # switch to istack |
|
|
618 |
|
2
|
619 2: stwu r14,-4(sp) # save old SP on stack |
|
0
|
620 |
|
|
621 #endif |
|
|
622 |
|
|
623 subi sp,sp,ppc_stack_frame_size # make a null frame |
|
|
624 |
|
|
625 li r0,0 # R0 = 0 |
|
|
626 stw r0,0(sp) # backchain = 0 |
|
|
627 stw r0,8(sp) # return pc = 0 |
|
|
628 |
|
|
629 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame |
|
|
630 # where C code can save LR |
|
|
631 |
|
|
632 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) |
|
|
633 |
|
|
634 lwi r3,0x0301 # r3 = type = INTR,RAISE |
|
2
|
635 lwz r4,ppcreg_vector(r14) # arg1 = vector address |
|
0
|
636 srwi r4,r4,8 # arg1 = vector number |
|
|
637 xor r5,r5,r5 # arg2 = 0 |
|
|
638 bl cyg_instrument # call instrument function |
|
|
639 |
|
|
640 #endif |
|
|
641 |
|
2
|
642 decode_interrupt r15,r14 # get table index |
|
|
643 |
|
0
|
644 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
|
|
645 .extern cyg_hal_gdb_isr |
|
2
|
646 lwz r3,ppcreg_pc(r14) # for serial receive irq. |
|
|
647 bl cyg_hal_gdb_isr # (arg1 is PC) |
|
0
|
648 cmpwi r3,0x0000 # Call ISR proper? |
|
|
649 beq 2f # (r3 is 0 when skipping |
|
|
650 # to avoid DSR call) |
|
|
651 1: |
|
|
652 #endif |
|
|
653 |
|
2
|
654 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
|
0
|
655 |
|
2
|
656 #ifdef CYG_HAL_POWERPC_MPC8xx |
|
|
657 # The CPM controller allows nested interrupts. However, |
|
|
658 # it sits on the back of the SIU controller which has no |
|
|
659 # HW support for this. In effect, SW masking of lower |
|
|
660 # priority IRQs in the SIU would be required for this to work. |
|
|
661 #endif |
|
|
662 |
|
|
663 #endif |
|
|
664 |
|
|
665 lwz r3,ppcreg_vector(r14) # retrieve decoded vector # |
|
0
|
666 |
|
|
667 lwi r6,hal_interrupt_handlers # get interrupt handler table |
|
|
668 lwzx r6,r6,r15 # load routine pointer |
|
|
669 |
|
|
670 lwi r4,hal_interrupt_data # get interrupt data table |
|
|
671 lwzx r4,r4,r15 # load data pointer |
|
|
672 # R4 = data argument |
|
|
673 |
|
|
674 mtctr r6 # put isr address in ctr |
|
|
675 |
|
|
676 bctrl # branch to ctr reg and link |
|
|
677 |
|
|
678 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
|
|
679 # If interrupt was caused by GDB, the ISR call above |
|
|
680 # is skipped by jumping here. |
|
|
681 2: |
|
|
682 #endif |
|
|
683 |
|
|
684 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
|
|
685 |
|
|
686 # If we are returning from the last nested interrupt, move back |
|
|
687 # to the thread stack. interrupt_end() must be called on the |
|
|
688 # thread stack since it potentially causes a context switch. |
|
|
689 # Since we have arranged for the top of stack location to |
|
|
690 # contain the sp we need to go back to here, just pop it off |
|
|
691 # and put it in SP. |
|
|
692 |
|
|
693 |
|
|
694 lwz sp,ppc_stack_frame_size*2(sp) # sp = *sp |
|
|
695 |
|
|
696 subi sp,sp,ppc_stack_frame_size # make a null frame |
|
|
697 |
|
|
698 li r0,0 # R0 = 0 |
|
|
699 stw r0,0(sp) # backchain = 0 |
|
|
700 stw r0,8(sp) # return pc = 0 |
|
|
701 |
|
|
702 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame |
|
|
703 # where C code can save LR |
|
|
704 #endif |
|
|
705 |
|
|
706 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT |
|
|
707 |
|
|
708 # We only need to call _interrupt_end() when there is a kernel |
|
|
709 # present to do any tidying up. |
|
|
710 |
|
|
711 # on return r3 bit 1 will indicate whether a DSR is |
|
|
712 # to be posted. Pass this together with a pointer to |
|
|
713 # the interrupt object we have just used to the |
|
|
714 # interrupt tidy up routine. |
|
|
715 |
|
2
|
716 # Note that r14 and r15 are defined to be preserved across |
|
0
|
717 # calls by the calling convention, so they still contain |
|
|
718 # the register dump and the vector number respectively. |
|
2
|
719 |
|
|
720 # Note: The instructions restoring the msr mask out the POW bit. |
|
|
721 # When eCos gets power management aware, this bit will have to be |
|
|
722 # set to the correct state rather than just cleared. |
|
0
|
723 |
|
|
724 lwi r4,hal_interrupt_objects # get interrupt object table |
|
|
725 lwzx r4,r4,r15 # load object pointer |
|
|
726 |
|
2
|
727 lwz r6,ppcreg_msr(r14) # restore msr, including |
|
|
728 lis r5,0xfffe # interrupt enable. |
|
|
729 andc r6,r6,r5 # mask out reserved bits |
|
|
730 sync # (and POW!) |
|
|
731 mtmsr r6 |
|
|
732 sync |
|
0
|
733 |
|
2
|
734 mr r5,r14 # arg3 = saved register dump |
|
0
|
735 |
|
|
736 .extern interrupt_end |
|
|
737 bl interrupt_end # call into C to finish off |
|
|
738 #endif |
|
|
739 |
|
|
740 restore_state: |
|
|
741 # All done, restore CPU state and continue |
|
|
742 |
|
|
743 addi sp,sp,ppc_stack_frame_size*2 # retrieve CPU state pointer |
|
|
744 |
|
|
745 # get sprs we want to restore |
|
|
746 lwz r3,ppcreg_cr(sp) |
|
|
747 lwz r4,ppcreg_pc(sp) |
|
|
748 lwz r5,ppcreg_msr(sp) |
|
|
749 lwz r6,ppcreg_xer(sp) |
|
|
750 lwz r7,ppcreg_lr(sp) |
|
|
751 lwz r8,ppcreg_ctr(sp) |
|
|
752 |
|
|
753 |
|
|
754 # stuff some of them into the CPU |
|
|
755 mtxer r6 |
|
|
756 mtlr r7 |
|
|
757 mtctr r8 |
|
|
758 |
|
|
759 # restore R0 and R2 |
|
|
760 lwz r0,ppcreg_regs(sp) |
|
|
761 lwz r2,ppcreg_regs+2*4(sp) |
|
|
762 |
|
2
|
763 # Restore registers used in vsr (r14+r15) |
|
|
764 lwz r14,(ppcreg_regs+14*4)(r1) |
|
|
765 lwz r15,(ppcreg_regs+15*4)(r1) |
|
|
766 |
|
|
767 # restore registers r6..r12/r31 |
|
0
|
768 .set _reg,6 |
|
|
769 .rept MAX_SAVE_REG+1-6 |
|
|
770 lwz _reg,(ppcreg_regs+_reg*4)(r1) |
|
|
771 .set _reg,_reg+1 |
|
|
772 .endr |
|
|
773 |
|
|
774 # Here all the registers are loaded except |
|
|
775 # r1 = ppcregs |
|
|
776 # r3 = ccr |
|
|
777 # r4 = srr0 = pc |
|
|
778 # r5 = srr1 = msr |
|
|
779 |
|
|
780 # We have to disable interrupts while srr0 and |
|
|
781 # srr1 are loaded, since another interrupt will |
|
|
782 # destroy them. |
|
|
783 |
|
|
784 mtcr r3 # set ccr |
|
|
785 |
|
2
|
786 lwi r3,CYG_MSR # do rest with ints disabled |
|
|
787 sync |
|
0
|
788 mtmsr r3 |
|
2
|
789 sync |
|
0
|
790 |
|
|
791 mtsrr0 r4 # load old pc |
|
|
792 mtsrr1 r5 # load old msr |
|
|
793 |
|
|
794 lwz r3,ppcreg_regs+3*4(r1) # load r3 value |
|
|
795 lwz r4,ppcreg_regs+4*4(r1) # load r4 value |
|
|
796 lwz r5,ppcreg_regs+5*4(r1) # load r5 value |
|
|
797 lwz r1,ppcreg_regs+1*4(r1) # restore r1 |
|
|
798 |
|
|
799 sync # settle things down |
|
|
800 isync |
|
|
801 rfi # and return |
|
|
802 |
|
2
|
803 #--------------------------------------------------------------------------- |
|
|
804 # Code for putting the CPU in a post-reset state; disabling MMU and caches. |
|
|
805 _init_CPU: |
|
|
806 #ifdef CYG_HAL_POWERPC_MPC8xx |
|
|
807 lwi r3,CYGARC_REG_DC_CMD_CD |
|
|
808 sync |
|
|
809 mtspr CYGARC_REG_DC_CST,r3 |
|
|
810 lwi r3,CYGARC_REG_IC_CMD_CD |
|
|
811 isync |
|
|
812 mtspr CYGARC_REG_IC_CST,r3 |
|
|
813 isync |
|
|
814 #endif |
|
|
815 |
|
|
816 # Set up MSR (disable MMU for now) |
|
|
817 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) |
|
|
818 sync |
|
|
819 mtmsr r3 |
|
|
820 sync |
|
|
821 blr |
|
|
822 |
|
|
823 #--------------------------------------------------------------------------- |
|
0
|
824 # This table contains a VSR pointer for each defined exception. |
|
|
825 # All of these except 5 and 9 point to the __default_exception_vsr |
|
|
826 # above, 5 and 9 point to the __default_interrupt_vsr. Entries in |
|
|
827 # this table may be changed using Cyg_Interrupt::set_vsr(). |
|
|
828 |
|
|
829 .data |
|
|
830 |
|
|
831 .globl hal_vsr_table |
|
|
832 hal_vsr_table: |
|
|
833 # Architecture defined vectors |
|
|
834 .long __default_exception_vsr # reserved |
|
|
835 .long __default_exception_vsr # system reset |
|
|
836 .long __default_exception_vsr # machine check |
|
|
837 .long __default_exception_vsr # data storage |
|
|
838 .long __default_exception_vsr # instruction storage |
|
|
839 |
|
|
840 .long __default_interrupt_vsr # external interrupt |
|
|
841 |
|
|
842 .long __default_exception_vsr # alignment |
|
|
843 .long __default_exception_vsr # program |
|
|
844 .long __default_exception_vsr # floating point unavailable |
|
|
845 |
|
|
846 .long __default_interrupt_vsr # decrementer |
|
|
847 |
|
|
848 .long __default_exception_vsr # reserved 0x0a00 |
|
|
849 .long __default_exception_vsr # reserved 0x0b00 |
|
|
850 .long __default_exception_vsr # system call |
|
|
851 .long __default_exception_vsr # trace |
|
|
852 .long __default_exception_vsr # floating point assist |
|
|
853 .long __default_exception_vsr # reserved 0x0f00 |
|
|
854 |
|
2
|
855 #ifdef CYG_HAL_POWERPC_MPC8xx |
|
0
|
856 |
|
|
857 # Implementation defined vectors |
|
|
858 .long __default_exception_vsr # software emulation |
|
|
859 .long __default_exception_vsr # instruction TLB miss |
|
|
860 .long __default_exception_vsr # data TLB miss |
|
|
861 .long __default_exception_vsr # instruction TLB error |
|
|
862 .long __default_exception_vsr # data TLB error |
|
|
863 .long __default_exception_vsr # reserved 0x1500 |
|
|
864 .long __default_exception_vsr # reserved 0x1600 |
|
|
865 .long __default_exception_vsr # reserved 0x1700 |
|
|
866 .long __default_exception_vsr # reserved 0x1800 |
|
|
867 .long __default_exception_vsr # reserved 0x1900 |
|
|
868 .long __default_exception_vsr # reserved 0x1a00 |
|
|
869 .long __default_exception_vsr # reserved 0x1b00 |
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|
870 .long __default_exception_vsr # data breakpoint |
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871 .long __default_exception_vsr # instruction breakpoint |
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872 .long __default_exception_vsr # peripheral breakpoint |
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873 .long __default_exception_vsr # non maskable development port |
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874 #endif |
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875 |
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2
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876 #--------------------------------------------------------------------------- |
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0
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877 # Interrupt vector tables. |
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878 # These tables contain the isr, data and object pointers used to deliver |
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879 # interrupts to user code. |
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2
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880 |
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881 #if (CYG_ISR_TABLE_SIZE > 2) |
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0
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882 .data |
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2
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883 #else |
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884 .section ".sdata","aw" |
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|
885 #endif |
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0
|
886 |
|
|
887 .extern hal_default_isr |
|
|
888 |
|
|
889 .globl hal_interrupt_handlers |
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|
890 hal_interrupt_handlers: |
|
2
|
891 .rept CYG_ISR_TABLE_SIZE |
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0
|
892 .long hal_default_isr |
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893 .endr |
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894 |
|
|
895 .globl hal_interrupt_data |
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|
896 hal_interrupt_data: |
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2
|
897 .rept CYG_ISR_TABLE_SIZE |
|
0
|
898 .long 0 |
|
|
899 .endr |
|
|
900 |
|
|
901 .globl hal_interrupt_objects |
|
|
902 hal_interrupt_objects: |
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2
|
903 .rept CYG_ISR_TABLE_SIZE |
|
0
|
904 .long 0 |
|
|
905 .endr |
|
|
906 |
|
2
|
907 #--------------------------------------------------------------------------- |
|
0
|
908 ## Temporary interrupt stack |
|
|
909 |
|
|
910 .section ".bss" |
|
|
911 |
|
|
912 .balign 16 |
|
|
913 __interrupt_stack_base: |
|
|
914 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE |
|
|
915 .byte 0 |
|
|
916 .endr |
|
|
917 .balign 16 |
|
|
918 __interrupt_stack: |
|
|
919 |
|
|
920 .long 0,0,0,0,0,0,0,0 |
|
|
921 |
|
2
|
922 #--------------------------------------------------------------------------- |
|
0
|
923 # end of vectors.S |
