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annotate packages/hal/mips/arch/current/src/mipsfp.c @ 26:4741a3c3496a ecos-sw-1999-07-23

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Merge from eCos master repository on 1999-07-23-05:47:06-BST
author jlarmour
date Fri, 23 Jul 1999 15:20:15 +0000
parents
children 641b639be825
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1 //==========================================================================
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2 //
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3 // mipsfp.c
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4 //
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5 // HAL miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Cygnus eCos Public License
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12 // Version 1.0 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://sourceware.cygnus.com/ecos
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released
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22 // September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Cygnus. Portions created
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25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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26 // -------------------------------------------
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27 //
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28 //####COPYRIGHTEND####
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29 //==========================================================================
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30 //#####DESCRIPTIONBEGIN####
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31 //
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32 // Author(s): jlarmour
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33 // Contributors: jlarmour
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34 // Date: 1999-07-13
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35 // Purpose: Emulate unimplemented FP operations on MIPS architectures
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36 // Description: This catches the unimplemented operation excetion only,
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37 // and if possible deals with it so processing can continue
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38 // as if the MIPS had a proper IEEE FPU
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39 //
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //========================================================================*/
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44
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45 // CONFIGURATION
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46
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47 #include <pkgconf/hal.h>
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48
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49 #ifdef CYGHWR_HAL_MIPS_FPU
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50
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51 // INCLUDES
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52
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53 #include <cyg/infra/cyg_type.h> // Standard eCos types
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54 #include <cyg/infra/cyg_ass.h> // Standard eCos assertion support
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55 #include <cyg/infra/cyg_trac.h> // Standard eCos tracing support
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56 #include <cyg/hal/hal_intr.h> // HAL interrupt vectors
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57 #include <cyg/hal/hal_arch.h> // Architecture types such as
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58 // HAL_SavedRegisters
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59 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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60 #include <cyg/hal/mips-regs.h> // MIPS register and bitmask definitions
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61
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62 // TYPES
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63
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64 // The following types were taken from <sys/ieeefp.h> from libm.
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65
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66 #if (CYG_BYTEORDER == CYG_MSBFIRST) // Big endian
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67
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68 // Note: there do not seem to be any current machines which are Big Endian but
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69 // have a mixed up double layout.
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70
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71 typedef union
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72 {
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73 cyg_int32 asi32[2];
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74
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75 cyg_int64 asi64;
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76
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77 double value;
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78
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79 struct
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80 {
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81 unsigned int sign : 1;
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82 unsigned int exponent: 11;
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83 unsigned int fraction0:4;
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84 unsigned int fraction1:16;
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85 unsigned int fraction2:16;
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86 unsigned int fraction3:16;
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87
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88 } number;
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89
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90 struct
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91 {
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92 unsigned int sign : 1;
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93 unsigned int exponent: 11;
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94 unsigned int quiet:1;
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95 unsigned int function0:3;
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96 unsigned int function1:16;
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97 unsigned int function2:16;
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98 unsigned int function3:16;
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99 } nan;
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100
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101 struct
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102 {
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103 cyg_uint32 msw;
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104 cyg_uint32 lsw;
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105 } parts;
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106
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107
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108 } Cyg_libm_ieee_double_shape_type;
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109
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110
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111 typedef union
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112 {
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113 cyg_int32 asi32;
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114
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115 float value;
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116
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117 struct
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118 {
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119 unsigned int sign : 1;
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120 unsigned int exponent: 8;
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121 unsigned int fraction0: 7;
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122 unsigned int fraction1: 16;
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123 } number;
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124
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125 struct
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126 {
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127 unsigned int sign:1;
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128 unsigned int exponent:8;
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129 unsigned int quiet:1;
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130 unsigned int function0:6;
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131 unsigned int function1:16;
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132 } nan;
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133
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134 } Cyg_libm_ieee_float_shape_type;
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135
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136
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137 #else // Little endian
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138
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139 typedef union
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140 {
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141 cyg_int32 asi32[2];
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142
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143 cyg_int64 asi64;
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144
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145 double value;
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146
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147 struct
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148 {
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149 #if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) // Big endian
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150 unsigned int fraction1:16;
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151 unsigned int fraction0: 4;
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152 unsigned int exponent :11;
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153 unsigned int sign : 1;
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154 unsigned int fraction3:16;
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155 unsigned int fraction2:16;
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156 #else
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157 unsigned int fraction3:16;
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158 unsigned int fraction2:16;
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159 unsigned int fraction1:16;
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160 unsigned int fraction0: 4;
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161 unsigned int exponent :11;
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162 unsigned int sign : 1;
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163 #endif
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164 } number;
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165
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166 struct
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167 {
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168 #if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) // Big endian
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169 unsigned int function1:16;
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170 unsigned int function0:3;
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171 unsigned int quiet:1;
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172 unsigned int exponent: 11;
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173 unsigned int sign : 1;
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174 unsigned int function3:16;
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175 unsigned int function2:16;
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176 #else
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177 unsigned int function3:16;
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178 unsigned int function2:16;
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179 unsigned int function1:16;
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180 unsigned int function0:3;
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181 unsigned int quiet:1;
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182 unsigned int exponent: 11;
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183 unsigned int sign : 1;
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184 #endif
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185 } nan;
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186
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187 struct
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188 {
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189 #if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) // Big endian
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190 cyg_uint32 msw;
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191 cyg_uint32 lsw;
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192 #else
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193 cyg_uint32 lsw;
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194 cyg_uint32 msw;
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195 #endif
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196 } parts;
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197
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198 } Cyg_libm_ieee_double_shape_type;
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199
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200
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201 typedef union
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202 {
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203 cyg_int32 asi32;
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204
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205 float value;
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206
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207 struct
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208 {
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209 unsigned int fraction0: 7;
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210 unsigned int fraction1: 16;
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211 unsigned int exponent: 8;
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212 unsigned int sign : 1;
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213 } number;
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214
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215 struct
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216 {
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217 unsigned int function1:16;
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218 unsigned int function0:6;
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219 unsigned int quiet:1;
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220 unsigned int exponent:8;
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221 unsigned int sign:1;
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222 } nan;
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223
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224 } Cyg_libm_ieee_float_shape_type;
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225
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226 #endif // little-endian
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227
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228 typedef enum {
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229 ADD_INSN=0, // 0
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230 SUB_INSN,
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231 MUL_INSN,
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232 DIV_INSN,
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233 SQRT_INSN,
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234 ABS_INSN, // 5
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235 MOV_INSN,
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236 NEG_INSN,
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237 ROUNDL_INSN,
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238 TRUNCL_INSN,
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239 CEILL_INSN, // 10
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240 FLOORL_INSN,
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241 ROUNDW_INSN,
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242 TRUNCW_INSN,
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243 CEILW_INSN,
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244 FLOORW_INSN, // 15
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245 // ...
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246 CVTS_INSN=32,
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247 CVTD_INSN,
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248 // ...
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249 CVTW_INSN=36,
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250 CVTL_INSN,
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251 // ...
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252 //
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253 // 48-63 are floating point compare - treated separately
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254
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255 } fp_operation;
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256
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257 typedef enum {
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258 S_FORMAT=16,
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259 D_FORMAT=17,
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260 W_FORMAT=20,
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261 L_FORMAT=21
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262 } fp_format;
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263
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264 // FUNCTIONS
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265
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266 #define issubnormal(_x_) ((_x_)->number.exponent == 0)
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267
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268 // This function returns non-zero if the exception has been handled
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269 // successfully.
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270
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271 // FIXME: Arguably we should raise underflow exceptions in some of the cases
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272 // below e.g. sqrt(subnormal). And perhaps we should round appropriately to
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273 // +/- 2^^Emin if round to +/- infinity is enabled, as per the FS bit. Not sure.
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274
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275 externC cyg_uint8
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276 cyg_hal_mips_process_fpe( HAL_SavedRegisters *regs )
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277 {
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278 CYG_WORD insn;
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279 CYG_HAL_FPU_REG *srcreg1, *srcreg2, *dstreg;
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280 cyg_uint8 handled=0;
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281 fp_format format;
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282 cyg_uint8 fp64bit=0; // true if format is 64bit, false if 32bit
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283 cyg_uint8 fixedpoint=0; // true if format is fixed point, false if
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284 // floating point
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285 cyg_uint8 computational_insn=1; // computational FP instruction
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286 cyg_bool delay_slot; // did it happen in a delay slot
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287
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288 CYG_CHECK_DATA_PTR( regs,
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289 "cyg_hal_mips_process_fpe() called with invalid regs ptr");
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290
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291 CYG_PRECONDITION( (regs->vector>>2) == CYGNUM_HAL_VECTOR_FPE,
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292 "Asked to process non-FPE exception");
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293
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diff changeset
294 CYG_REPORT_FUNCNAMETYPE("cyg_hal_mips_process_fpe", "returning %d");
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jlarmour
parents:
diff changeset
295
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jlarmour
parents:
diff changeset
296 // First of all, we only handle the unimplemented operation exception
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jlarmour
parents:
diff changeset
297 // here, so if we don't have that, we just exit
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parents:
diff changeset
298 if ((regs->fcr31 & FCR31_CAUSE_E) == 0) {
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parents:
diff changeset
299 CYG_REPORT_RETVAL(0);
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jlarmour
parents:
diff changeset
300 return 0;
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jlarmour
parents:
diff changeset
301 }
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jlarmour
parents:
diff changeset
302
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jlarmour
parents:
diff changeset
303 // Get the contents of the instruction that caused the exception. This
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jlarmour
parents:
diff changeset
304 // may have been in a branch delay slot however, so we have to check
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jlarmour
parents:
diff changeset
305 // the BD bit in the cause register first.
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jlarmour
parents:
diff changeset
306 if (regs->cause & CAUSE_BD) {
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jlarmour
parents:
diff changeset
307 insn = *(((CYG_WORD *) regs->pc) + 1);
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parents:
diff changeset
308 delay_slot = true;
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jlarmour
parents:
diff changeset
309 } else {
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jlarmour
parents:
diff changeset
310 insn = *(CYG_WORD *) regs->pc;
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jlarmour
parents:
diff changeset
311 delay_slot = false;
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jlarmour
parents:
diff changeset
312 }
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jlarmour
parents:
diff changeset
313
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diff changeset
314 CYG_TRACE2(true, "exception at pc %08x containing %08x", regs->pc, insn);
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diff changeset
315
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diff changeset
316 CYG_ASSERT( (insn>>26) == 0x11,
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diff changeset
317 "Instruction at pc doesn't have expected opcode COP1");
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diff changeset
318
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jlarmour
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diff changeset
319 // Determine the format
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diff changeset
320 format = (insn >> 21) & 0x1f;
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jlarmour
parents:
diff changeset
321
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jlarmour
parents:
diff changeset
322 switch (format)
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jlarmour
parents:
diff changeset
323 {
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jlarmour
parents:
diff changeset
324 case S_FORMAT:
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jlarmour
parents:
diff changeset
325 break;
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jlarmour
parents:
diff changeset
326 case D_FORMAT:
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jlarmour
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diff changeset
327 fp64bit++;
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jlarmour
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diff changeset
328 break;
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jlarmour
parents:
diff changeset
329 case W_FORMAT:
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jlarmour
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diff changeset
330 fixedpoint++;
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jlarmour
parents:
diff changeset
331 break;
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jlarmour
parents:
diff changeset
332 case L_FORMAT:
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jlarmour
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diff changeset
333 fixedpoint++;
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jlarmour
parents:
diff changeset
334 fp64bit++;
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jlarmour
parents:
diff changeset
335 break;
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jlarmour
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diff changeset
336 default:
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jlarmour
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diff changeset
337 computational_insn=0;
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jlarmour
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diff changeset
338 break;
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jlarmour
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diff changeset
339 } // switch
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jlarmour
parents:
diff changeset
340
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jlarmour
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diff changeset
341 // This module only emulates computational floating point instructions
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jlarmour
parents:
diff changeset
342 if (computational_insn && !fixedpoint) {
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jlarmour
parents:
diff changeset
343
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diff changeset
344 // Decode the registers used
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diff changeset
345 dstreg = &regs->f[ (insn >> 6) & 0x1f ];
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diff changeset
346 srcreg1 = &regs->f[ (insn >> 11) & 0x1f ];
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diff changeset
347 srcreg2 = &regs->f[ (insn >> 16) & 0x1f ];
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diff changeset
348
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jlarmour
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diff changeset
349 // Determine the operation requested
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jlarmour
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diff changeset
350 switch (insn & 0x3f)
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diff changeset
351 {
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jlarmour
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diff changeset
352 case ADD_INSN:
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diff changeset
353 case SUB_INSN:
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jlarmour
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diff changeset
354 case MUL_INSN:
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diff changeset
355 case DIV_INSN:
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jlarmour
parents:
diff changeset
356
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diff changeset
357 if (fp64bit) {
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diff changeset
358 Cyg_libm_ieee_double_shape_type *s1, *s2;
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diff changeset
359
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diff changeset
360 s1 = (Cyg_libm_ieee_double_shape_type *)srcreg1;
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diff changeset
361 s2 = (Cyg_libm_ieee_double_shape_type *)srcreg2;
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diff changeset
362
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diff changeset
363 if (issubnormal(s1)) { // flush to 0 and restart
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diff changeset
364 s1->value=0.0;
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diff changeset
365 handled++;
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diff changeset
366 }
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jlarmour
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diff changeset
367
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diff changeset
368 // We could try flushing both to 0 at the same time, but
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jlarmour
parents:
diff changeset
369 // that's inadvisable if both numbers are very small.
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jlarmour
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diff changeset
370 // Particularly if this is DIV_INSN, when we could therefore
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jlarmour
parents:
diff changeset
371 // get 0/0 even when the program explicitly checked for
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jlarmour
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diff changeset
372 // denominator != 0. That's also why we check s1 first.
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diff changeset
373
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diff changeset
374 else if (issubnormal(s2)) { // flush to 0 and restart
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diff changeset
375 s2->value=0.0;
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diff changeset
376 handled++;
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jlarmour
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diff changeset
377 }
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jlarmour
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diff changeset
378 } else { // 32-bit
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jlarmour
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diff changeset
379 Cyg_libm_ieee_float_shape_type *s1, *s2;
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jlarmour
parents:
diff changeset
380
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diff changeset
381 s1 = (Cyg_libm_ieee_float_shape_type *)srcreg1;
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diff changeset
382 s2 = (Cyg_libm_ieee_float_shape_type *)srcreg2;
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jlarmour
parents:
diff changeset
383
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jlarmour
parents:
diff changeset
384 if (issubnormal(s1)) { // flush to 0 and restart
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jlarmour
parents:
diff changeset
385 s1->value=0.0;
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jlarmour
parents:
diff changeset
386 handled++;
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jlarmour
parents:
diff changeset
387 }
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jlarmour
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diff changeset
388 else if (issubnormal(s2)) { // flush to 0 and restart
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jlarmour
parents:
diff changeset
389 s2->value=0.0;
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jlarmour
parents:
diff changeset
390 handled++;
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jlarmour
parents:
diff changeset
391 }
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jlarmour
parents:
diff changeset
392 }
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jlarmour
parents:
diff changeset
393 break;
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jlarmour
parents:
diff changeset
394
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jlarmour
parents:
diff changeset
395 case SQRT_INSN:
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jlarmour
parents:
diff changeset
396 if (fp64bit) {
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jlarmour
parents:
diff changeset
397 Cyg_libm_ieee_double_shape_type *d, *s;
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jlarmour
parents:
diff changeset
398
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jlarmour
parents:
diff changeset
399 d = (Cyg_libm_ieee_double_shape_type *)dstreg;
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parents:
diff changeset
400 s = (Cyg_libm_ieee_double_shape_type *)srcreg1;
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jlarmour
parents:
diff changeset
401
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jlarmour
parents:
diff changeset
402 if (issubnormal(s)) { // Sqrt of something tiny is 0
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jlarmour
parents:
diff changeset
403 // if this is a delay slot, we can't restart properly
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jlarmour
parents:
diff changeset
404 // so clear the source register instead
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jlarmour
parents:
diff changeset
405 if (delay_slot)
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
406 s->value=0.0;
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jlarmour
parents:
diff changeset
407 else {
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jlarmour
parents:
diff changeset
408 d->value=0.0;
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jlarmour
parents:
diff changeset
409 regs->pc += 4; // We've dealt with this so move on
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
410 }
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jlarmour
parents:
diff changeset
411 handled++;
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
412 }
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
413
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
414 } else { // 32-bit
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jlarmour
parents:
diff changeset
415 Cyg_libm_ieee_float_shape_type *d, *s;
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jlarmour
parents:
diff changeset
416
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jlarmour
parents:
diff changeset
417 d = (Cyg_libm_ieee_float_shape_type *)dstreg;
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parents:
diff changeset
418 s = (Cyg_libm_ieee_float_shape_type *)srcreg1;
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jlarmour
parents:
diff changeset
419
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jlarmour
parents:
diff changeset
420 if (issubnormal(s)) { // Sqrt of something tiny is 0
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jlarmour
parents:
diff changeset
421 // if this is a delay slot, we can't restart properly
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
422 // so clear the source register instead
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jlarmour
parents:
diff changeset
423 if (delay_slot)
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jlarmour
parents:
diff changeset
424 s->value=0.0;
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jlarmour
parents:
diff changeset
425 else {
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jlarmour
parents:
diff changeset
426 d->value=0.0;
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jlarmour
parents:
diff changeset
427 regs->pc += 4; // We've dealt with this so move on
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
428 }
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jlarmour
parents:
diff changeset
429 handled++;
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jlarmour
parents:
diff changeset
430 }
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
431 }
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jlarmour
parents:
diff changeset
432 break;
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jlarmour
parents:
diff changeset
433
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jlarmour
parents:
diff changeset
434 case ABS_INSN:
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jlarmour
parents:
diff changeset
435 // We may as well do this right if we can
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jlarmour
parents:
diff changeset
436 if (fp64bit) {
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jlarmour
parents:
diff changeset
437 Cyg_libm_ieee_double_shape_type *d, *s;
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jlarmour
parents:
diff changeset
438
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jlarmour
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diff changeset
439 d = (Cyg_libm_ieee_double_shape_type *)dstreg;
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jlarmour
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diff changeset
440 s = (Cyg_libm_ieee_double_shape_type *)srcreg1;
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jlarmour
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diff changeset
441
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jlarmour
parents:
diff changeset
442 // if this is a delay slot, we can't restart properly
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jlarmour
parents:
diff changeset
443 // so clear the source register instead
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jlarmour
parents:
diff changeset
444 if (delay_slot) {
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jlarmour
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diff changeset
445 s->value=0.0;
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jlarmour
parents:
diff changeset
446 } else {
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jlarmour
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diff changeset
447 d->asi64 = s->asi64;
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jlarmour
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diff changeset
448 d->number.sign = 0;
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jlarmour
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diff changeset
449 regs->pc += 4;
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jlarmour
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diff changeset
450 }
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jlarmour
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451 } else { // 32-bit
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jlarmour
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diff changeset
452 Cyg_libm_ieee_float_shape_type *d, *s;
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jlarmour
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diff changeset
453
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diff changeset
454 d = (Cyg_libm_ieee_float_shape_type *)dstreg;
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diff changeset
455 s = (Cyg_libm_ieee_float_shape_type *)srcreg1;
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jlarmour
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diff changeset
456
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jlarmour
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diff changeset
457 // if this is a delay slot, we can't restart properly
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jlarmour
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diff changeset
458 // so clear the source register instead
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jlarmour
parents:
diff changeset
459 if (delay_slot) {
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jlarmour
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diff changeset
460 s->value=0.0;
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diff changeset
461 } else {
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diff changeset
462 d->asi32 = s->asi32;
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diff changeset
463 d->number.sign = 0;
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jlarmour
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diff changeset
464 regs->pc += 4;
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jlarmour
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diff changeset
465 }
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jlarmour
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diff changeset
466 }
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jlarmour
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diff changeset
467 handled++;
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jlarmour
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diff changeset
468 break;
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jlarmour
parents:
diff changeset
469
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jlarmour
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diff changeset
470 case NEG_INSN:
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jlarmour
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diff changeset
471 // We may as well do this right if we can
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jlarmour
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diff changeset
472 if (fp64bit) {
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jlarmour
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diff changeset
473 Cyg_libm_ieee_double_shape_type *d, *s;
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jlarmour
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diff changeset
474
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diff changeset
475 d = (Cyg_libm_ieee_double_shape_type *)dstreg;
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diff changeset
476 s = (Cyg_libm_ieee_double_shape_type *)srcreg1;
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jlarmour
parents:
diff changeset
477
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jlarmour
parents:
diff changeset
478 // if this is a delay slot, we can't restart properly
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jlarmour
parents:
diff changeset
479 // so clear the source register instead
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jlarmour
parents:
diff changeset
480 if (delay_slot) {
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jlarmour
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diff changeset
481 s->value=0.0;
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jlarmour
parents:
diff changeset
482 } else {
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jlarmour
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diff changeset
483 d->asi64 = s->asi64;
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jlarmour
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diff changeset
484 d->number.sign = s->number.sign ? 0 : 1;
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jlarmour
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diff changeset
485 regs->pc += 4;
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jlarmour
parents:
diff changeset
486 }
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jlarmour
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diff changeset
487 } else { // 32-bit
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jlarmour
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diff changeset
488 Cyg_libm_ieee_float_shape_type *d, *s;
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jlarmour
parents:
diff changeset
489
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jlarmour
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diff changeset
490 d = (Cyg_libm_ieee_float_shape_type *)dstreg;
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diff changeset
491 s = (Cyg_libm_ieee_float_shape_type *)srcreg1;
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jlarmour
parents:
diff changeset
492
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jlarmour
parents:
diff changeset
493 // if this is a delay slot, we can't restart properly
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jlarmour
parents:
diff changeset
494 // so clear the source register instead
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jlarmour
parents:
diff changeset
495 if (delay_slot) {
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jlarmour
parents:
diff changeset
496 s->value=0.0;
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jlarmour
parents:
diff changeset
497 } else {
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jlarmour
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diff changeset
498 d->asi32 = s->asi32;
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jlarmour
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diff changeset
499 d->number.sign = s->number.sign ? 0 : 1;
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jlarmour
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diff changeset
500 regs->pc += 4;
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jlarmour
parents:
diff changeset
501 }
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jlarmour
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diff changeset
502 }
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jlarmour
parents:
diff changeset
503 handled++;
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jlarmour
parents:
diff changeset
504 break;
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jlarmour
parents:
diff changeset
505
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jlarmour
parents:
diff changeset
506 default:
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jlarmour
parents:
diff changeset
507 break;
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jlarmour
parents:
diff changeset
508 } // switch
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jlarmour
parents:
diff changeset
509
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jlarmour
parents:
diff changeset
510 // As well as all the other opcodes in the enum, there are also all
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jlarmour
parents:
diff changeset
511 // the floating point compare operations between 48 and 63
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jlarmour
parents:
diff changeset
512 }
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jlarmour
parents:
diff changeset
513
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jlarmour
parents:
diff changeset
514 if (handled) {
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jlarmour
parents:
diff changeset
515 // We must clear the cause and flag bits before restoring FPCR31
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jlarmour
parents:
diff changeset
516 regs->fcr31 &= ~(FCR31_CAUSE_E | FCR31_CAUSE_V | FCR31_CAUSE_Z |
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jlarmour
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diff changeset
517 FCR31_CAUSE_O | FCR31_CAUSE_U | FCR31_CAUSE_I |
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jlarmour
parents:
diff changeset
518 FCR31_FLAGS_V | FCR31_FLAGS_Z |
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jlarmour
parents:
diff changeset
519 FCR31_FLAGS_O | FCR31_FLAGS_U | FCR31_FLAGS_I);
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jlarmour
parents:
diff changeset
520
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
521 }
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jlarmour
parents:
diff changeset
522
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jlarmour
parents:
diff changeset
523 CYG_REPORT_RETVAL(handled);
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jlarmour
parents:
diff changeset
524 return handled;
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents:
diff changeset
525 } // cyg_hal_mips_process_fpe()
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jlarmour
parents:
diff changeset
526
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jlarmour
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diff changeset
527 #endif // ifdef CYGHWR_HAL_MIPS_FPU
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jlarmour
parents:
diff changeset
528
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jlarmour
parents:
diff changeset
529 // EOF mipsfp.c