Mercurial > flash_v2

annotate packages/hal/powerpc/ppc40x/current/include/var_intr.h @ 149:52c99470ec11

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Merge from eCos master repository on 2001-01-19-06:43:03-GMT
author jlarmour
date Fri, 19 Jan 2001 07:37:45 +0000
parents a9ac27ec7abc
children 25e238959bae
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1 #ifndef CYGONCE_VAR_INTR_H
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2 #define CYGONCE_VAR_INTR_H
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3 //=============================================================================
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4 //
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5 // var_intr.h
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6 //
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7 // Variant HAL interrupt and clock support
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8 //
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9 //=============================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //=============================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): nickg
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37 // Contributors:nickg, jskov, jlarmour, hmt, gthomas
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38 // Date: 2000-04-02
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39 // Purpose: Variant interrupt support
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40 // Description: The macros defined here provide the HAL APIs for handling
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41 // interrupts and the clock on the PPC40x variant CPUs.
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42 // Usage: Is included via the architecture interrupt header:
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43 // #include <cyg/hal/hal_intr.h>
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44 // ...
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50
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51 // Special handling for additional exceptions
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52
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53 #define CYGNUM_HAL_VECTOR_TIMERS 16 // Note: must handle all 3!
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54 #define CYGNUM_HAL_VECTOR_DATA_TLB_MISS 17
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55 #define CYGNUM_HAL_VECTOR_INSTR_TLB_MISS 18
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56 #define CYGNUM_HAL_VECTOR_DEBUG 32
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57
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58 // No 'trace'/'single step' trap on this processor
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59 #define CYGNUM_HAL_NO_VECTOR_TRACE
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60
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61 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_DEBUG
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62
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63 // Special handling for interrupts
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64
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65 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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66
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67 // Additional interrupt sources which are supported by the 40x
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68 #define CYGNUM_HAL_INTERRUPT_CRITICAL 2
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69 #define CYGNUM_HAL_INTERRUPT_SERIAL_RCV 3
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70 #define CYGNUM_HAL_INTERRUPT_SERIAL_XMT 4
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71 #define CYGNUM_HAL_INTERRUPT_JTAG_RCV 5
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72 #define CYGNUM_HAL_INTERRUPT_JTAG_XMT 6
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73 #define CYGNUM_HAL_INTERRUPT_DMA0 7
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74 #define CYGNUM_HAL_INTERRUPT_DMA1 8
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75 #define CYGNUM_HAL_INTERRUPT_DMA2 9
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76 #define CYGNUM_HAL_INTERRUPT_DMA3 10
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77 #define CYGNUM_HAL_INTERRUPT_EXT0 11
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78 #define CYGNUM_HAL_INTERRUPT_EXT1 12
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79 #define CYGNUM_HAL_INTERRUPT_EXT2 13
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80 #define CYGNUM_HAL_INTERRUPT_EXT3 14
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81 #define CYGNUM_HAL_INTERRUPT_EXT4 15
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82 #define CYGNUM_HAL_INTERRUPT_VAR_TIMER 16
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83 #define CYGNUM_HAL_INTERRUPT_FIXED_TIMER 17
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84 #define CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER 18
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85
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86 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER
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87
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88 //--------------------------------------------------------------------------
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89 // Interrupt controller access
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90
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91 externC void hal_ppc40x_interrupt_mask(int);
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92 externC void hal_ppc40x_interrupt_unmask(int);
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93 externC void hal_ppc40x_interrupt_acknowledge(int);
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94 externC void hal_ppc40x_interrupt_configure(int, int, int);
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95 externC void hal_ppc40x_interrupt_set_level(int, int);
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96
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97 #define HAL_INTERRUPT_MASK( _vector_ ) \
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98 hal_ppc40x_interrupt_mask( _vector_ )
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99 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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100 hal_ppc40x_interrupt_unmask( _vector_ )
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101 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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102 hal_ppc40x_interrupt_acknowledge( _vector_ )
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103 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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104 hal_ppc40x_interrupt_configure( _vector_, _level_, _up_ )
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105 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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106 hal_ppc40x_interrupt_set_level( _vector_, _level_ )
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107
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108 //--------------------------------------------------------------------------
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109 // Clock control
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110
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111 externC void hal_ppc40x_clock_initialize(cyg_uint32);
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112 externC void hal_ppc40x_clock_read(cyg_uint32 *);
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113 externC void hal_ppc40x_clock_reset(cyg_uint32, cyg_uint32);
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114 externC void hal_ppc40x_delay_us(int);
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115
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116 #define CYGHWR_HAL_CLOCK_DEFINED
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117 #define HAL_CLOCK_INITIALIZE( _period_ ) hal_ppc40x_clock_initialize( _period_ )
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118 #define HAL_CLOCK_RESET( _vec_, _period_ ) hal_ppc40x_clock_reset( _vec_, _period_ )
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119 #define HAL_CLOCK_READ( _pvalue_ ) hal_ppc40x_clock_read( _pvalue_ )
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120 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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121 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
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122 #endif
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123
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124 #define HAL_DELAY_US(n) hal_ppc40x_delay_us(n)
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125 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_VAR_TIMER
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126
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127 //-----------------------------------------------------------------------------
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128 // Symbols used by assembly code
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129 #define CYGARC_VARIANT_DEFS \
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130 DEFINE(CYGNUM_HAL_VECTOR_TIMERS, CYGNUM_HAL_VECTOR_TIMERS); \
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131 DEFINE(CYGNUM_HAL_INTERRUPT_VAR_TIMER,CYGNUM_HAL_INTERRUPT_VAR_TIMER);
134
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132
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133 //-----------------------------------------------------------------------------
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134 #endif // ifndef CYGONCE_VAR_INTR_H
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135 // End of var_intr.h