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annotate packages/hal/arm/cl7211/current/include/hal_cache.h @ 32:5af43b635655 ecos-sw-1999-08-18

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Merge from eCos master repository on 1999-08-18-15:20:01-BST
author jlarmour
date Wed, 18 Aug 1999 15:33:44 +0000
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg, gthomas
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36 // Contributors: nickg, gthomas
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37 // Date: 1998-09-28
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/hal_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <cyg/infra/cyg_type.h>
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51 #include <cyg/hal/hal_mmu.h>
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52
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53 //-----------------------------------------------------------------------------
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54 // Cache dimensions
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55
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56 #define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes
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57 #define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line
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58 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
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59 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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60
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61 #define HAL_CACHE_UNIFIED // Let programs know the caches are combined
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62
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63 //-----------------------------------------------------------------------------
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64 // Global control of caches
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65
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66 // Note: the 'mrc' doesn't seem to work.
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67 #if 0
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68 // Enable the data cache
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69 // mrc MMU_CP,0,r1,MMU_Control,c0
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70 // orr r1,r1,#MMU_Control_C|MMU_Control_B
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71 // mcr MMU_CP,0,r1,MMU_Control,c0
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72
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73 #define HAL_UCACHE_ENABLE() \
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74 { \
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75 asm volatile ("mrc p15,0,r1,c1,c0;" \
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76 "orr r1,r1,#0x000C;" \
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77 "mcr p15,0,r1,c1,c0;" \
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78 : \
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79 : \
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80 : "r1" /* Clobber list */ \
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81 ); \
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82 \
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83 }
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84
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85 // Disable the data cache
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86 #define HAL_UCACHE_DISABLE() \
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87 { \
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88 asm volatile ("mrc p15,0,r1,c1,c0;" \
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89 "bic r1,r1,#0x000C;" \
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90 "mcr p15,0,r1,c1,c0;" \
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91 : \
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92 : \
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93 : "r1" /* Clobber list */ \
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94 ); \
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95 \
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96 }
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97 #else
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98 #define HAL_UCACHE_ENABLE() \
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99 { \
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100 asm volatile ("mov r1,#0x7D;" \
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101 "mcr p15,0,r1,c1,c0;" \
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102 : \
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103 : \
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104 : "r1" /* Clobber list */ \
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105 ); \
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106 \
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107 }
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108
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109 // Disable the data cache
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110 #define HAL_UCACHE_DISABLE() \
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111 { \
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112 asm volatile ("mov r1,#0x71;" \
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113 "mcr p15,0,r1,c1,c0;" \
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114 : \
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115 : \
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116 : "r1" /* Clobber list */ \
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117 ); \
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118 \
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119 }
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120 #endif
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121
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122 // Is the cache turned on?
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123 #define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
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124
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125 // Invalidate the entire cache
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126 // mcr MMU_CP,0,r1,MMU_InvalidateCache,c0
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127 #define HAL_UCACHE_INVALIDATE_ALL() \
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128 { \
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129 asm volatile ("mcr p15,0,r1,c7,c0,0;" ); \
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130 \
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131 }
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132
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133 // Synchronize the contents of the cache with memory.
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134 #define HAL_UCACHE_SYNC() \
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135 { \
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136 cyg_uint32 *ROM = (cyg_uint32 *)0xE0000000; \
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137 int i; \
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138 volatile cyg_uint32 val; \
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139 for (i = 0; i < HAL_UCACHE_SETS; i++) { \
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140 val = *ROM; \
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141 ROM += HAL_UCACHE_LINE_SIZE; \
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142 } \
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143 }
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144
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145 // Purge contents of data cache
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146 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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147
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148 // Set the data cache refill burst size
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149 //#define HAL_UCACHE_BURST_SIZE(_size_)
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150
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151 // Set the data cache write mode
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152 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
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153
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154 //#define HAL_UCACHE_WRITETHRU_MODE 0
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155 //#define HAL_UCACHE_WRITEBACK_MODE 1
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156
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157 // Load the contents of the given address range into the data cache
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158 // and then lock the cache so that it stays there.
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159 //#define HAL_UCACHE_LOCK(_base_, _size_)
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160
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161 // Undo a previous lock operation
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162 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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163
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164 // Unlock entire cache
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165 //#define HAL_UCACHE_UNLOCK_ALL()
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166
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167 //-----------------------------------------------------------------------------
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168 // Data cache line control
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169
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170 // Allocate cache lines for the given address range without reading its
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171 // contents from memory.
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172 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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173
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174 // Write dirty cache lines to memory and invalidate the cache entries
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175 // for the given address range.
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176 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC()
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177
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178 // Invalidate cache lines in the given range without writing to memory.
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179 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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180
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181 // Write dirty cache lines to memory for the given address range.
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182 #define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC()
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183
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184 // Preread the given range into the cache with the intention of reading
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185 // from it later.
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186 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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187
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188 // Preread the given range into the cache with the intention of writing
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189 // to it later.
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190 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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191
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192 // Allocate and zero the cache lines associated with the given range.
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193 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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194
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195 //-----------------------------------------------------------------------------
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196 // Global control of data cache
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197
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198 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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199 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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200 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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201 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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202
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203 // Enable the data cache
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204 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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205
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206 // Disable the data cache
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207 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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208
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209 // Invalidate the entire cache
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210 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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211
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212 // Synchronize the contents of the cache with memory.
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213 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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214
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215 // Query the state of the data cache
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216 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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217
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218 // Set the data cache refill burst size
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219 //#define HAL_DCACHE_BURST_SIZE(_size_)
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220
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221 // Set the data cache write mode
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222 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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223
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224 //#define HAL_DCACHE_WRITETHRU_MODE 0
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225 //#define HAL_DCACHE_WRITEBACK_MODE 1
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226
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227 // Load the contents of the given address range into the data cache
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228 // and then lock the cache so that it stays there.
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229 //#define HAL_DCACHE_LOCK(_base_, _size_)
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230
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231 // Undo a previous lock operation
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232 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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233
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234 // Unlock entire cache
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235 //#define HAL_DCACHE_UNLOCK_ALL()
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236
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237 //-----------------------------------------------------------------------------
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238 // Data cache line control
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239
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240 // Allocate cache lines for the given address range without reading its
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241 // contents from memory.
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242 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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243
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244 // Write dirty cache lines to memory and invalidate the cache entries
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245 // for the given address range.
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246 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ )
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247
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248 // Invalidate cache lines in the given range without writing to memory.
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249 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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250
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251 // Write dirty cache lines to memory for the given address range.
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252 #define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ )
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253
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254 // Preread the given range into the cache with the intention of reading
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255 // from it later.
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256 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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257
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258 // Preread the given range into the cache with the intention of writing
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259 // to it later.
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260 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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261
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262 // Allocate and zero the cache lines associated with the given range.
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263 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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264
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265 //-----------------------------------------------------------------------------
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266 // Global control of Instruction cache - use Data cache controls since they
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267 // are not separatable.
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268
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269 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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270 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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271 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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272 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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273
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274 // Enable the instruction cache
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275 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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276
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277 // Disable the instruction cache
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278 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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279
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280 // Invalidate the entire cache
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281 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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282
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283 // Synchronize the contents of the cache with memory.
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284 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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285
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286 // Set the instruction cache refill burst size
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287 //#define HAL_ICACHE_BURST_SIZE(_size_)
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288
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289 // Load the contents of the given address range into the instruction cache
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290 // and then lock the cache so that it stays there.
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291 //#define HAL_ICACHE_LOCK(_base_, _size_)
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292
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293 // Undo a previous lock operation
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294 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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295
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296 // Unlock entire cache
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297 //#define HAL_ICACHE_UNLOCK_ALL()
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298
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299 //-----------------------------------------------------------------------------
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300 // Instruction cache line control
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301
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302 // Invalidate cache lines in the given range without writing to memory.
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303 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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304
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305 //-----------------------------------------------------------------------------
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306 #endif // ifndef CYGONCE_HAL_CACHE_H
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307 // End of hal_cache.h