Mercurial > flash_v2

annotate packages/hal/sh/edk/current/include/platform.inc @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
parents 435cced73e2f
children 0c2b7be0d798
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1 #ifndef CYGONCE_HAL_PLATFORM_INC
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2 #define CYGONCE_HAL_PLATFORM_INC
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3 ##=============================================================================
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4 ##
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5 ## platform.inc
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6 ##
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7 ## SH/EDK7708 board assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.0 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://sourceware.cygnus.com/ecos
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17 #
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18 # Software distributed under the License is distributed on an
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): jskov
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37 ## Contributors:jskov
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38 ## Date: 2000-02-02
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39 ## Purpose: SH/EDK7708 board definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the SH/EDK7708 board.
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42 ## Usage:
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43 ## #include <cyg/hal/platform.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #include <cyg/hal/sh_regs.h>
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54 #include <cyg/hal/sh_offsets.inc>
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55
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56 #------------------------------------------------------------------------------
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57 # Hardware initialization.
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58
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59 .macro hal_hardware_init
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60 // Set up the Bus State Controller
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61 mova BSC_settings_table,r0
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62 mov r0,r3
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63 1: mov.w @r3+,r0 // Address (or zero)
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64 cmp/eq #0,r0
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65 bt 2f
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66 mov.w @r3+,r1 // data
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67 bra 1b
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68 mov.w r1,@r0 // delay slot
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69
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70 .align 2
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71 BSC_settings_table:
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72 # These are the settings set by the Hitachi ROM Monitor.
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73
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74 # BCR2: Bus size of areas 1-6 to 32 bits
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75 .word CYGARC_REG_BCR2
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76 .word 0x3ffc
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77 # BCR1: Areas 2 and 3 are SDRAM
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78 .word CYGARC_REG_BCR1
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79 .word 0x080c
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80 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
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81 .word CYGARC_REG_BCR2
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82 .word 0x3ffc
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83 # WCR1: 3 wait-state cycles inserted for all areas
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84 .word CYGARC_REG_WCR1
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85 .word 0x3fff
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86 # WCR2: extra wait states and full pitch for burst
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87 .word CYGARC_REG_WCR2
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88 .word 0xffd7
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89 # MCR: RAS/CAS & burst timing area 2/3
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90 .word CYGARC_REG_MCR
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91 .word 0x963c
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92 # RTCNT: refresh counter (needs a5 in top byte to accept write)
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93 .word CYGARC_REG_RTCNT
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94 .word (0xa500 | 0x0000)
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95 # RTCOR: refresh time constant (needs a5 in top byte to accept write)
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96 .word CYGARC_REG_RTCOR
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97 .word (0xa500 | 0x003b)
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98 # RFCR: refresh count register (needs a4 in top byte to accept write)
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99 .word CYGARC_REG_RFCR
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100 .word (0xa400 | 0x0000)
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101 # RTCSR: refresh timer control (needs a5 in top byte to accept write)
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102 .word CYGARC_REG_RTCSR
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103 .word (0xa500 | 0x0008)
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104
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105 # Set SDMR to 0x220
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106 .word 0xd880
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107 .word 0
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108
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109 # Table end
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110 .word 0
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111
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112 .align 2
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113 2:
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114 .endm
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115
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116 #------------------------------------------------------------------------------
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117 # Monitor initialization.
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118
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119 #ifndef CYGPKG_HAL_SH_MON_DEFINED
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120
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121 #if !defined(CYG_HAL_STARTUP_RAM) || \
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122 ( defined(CYG_HAL_STARTUP_RAM) && \
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123 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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124
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125 # If we are not starting up from RAM, or we are starting in
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126 # RAM and NOT using a ROM monitor, initialize the VSR table.
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127
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128 .macro hal_mon_init
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129 mov.l $_hal_vsr_table_p,r3
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130 # Write exception vectors
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131 mov.l $_cyg_hal_default_exception_vsr_p,r4
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132 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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133 1: mov.l r4,@r3
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134 add #4,r3
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135 dt r5
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136 bf 1b
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137 # Write interrupt vector
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138 mov.l $_cyg_hal_default_interrupt_vsr_p,r4
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139 mov.l r4,@r3
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140 bra 2f
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141 nop
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142 .align 2
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143
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144 $_cyg_hal_default_exception_vsr_p:
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145 .long _cyg_hal_default_exception_vsr
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146 $_cyg_hal_default_interrupt_vsr_p:
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147 .long _cyg_hal_default_interrupt_vsr
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148
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149 .extern _hal_vsr_table
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150 $_hal_vsr_table_p:
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151 .long _hal_vsr_table
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152
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153 2:
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154 .endm
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155
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156 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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157
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158 # Initialize the VSR table entries
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159 # We only take control of the interrupt vector,
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160 # the rest are left to the ROM for now...
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161
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162 .macro hal_mon_init
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163 # Write interrupt vector
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164 mov.l $_hal_vsr_table_p,r3
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165 mov.l $_cyg_hal_default_interrupt_vsr_p,r4
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166 mov.l r4,@r3
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167 bra 2f
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168 nop
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169 .align 2
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170
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171 $_cyg_hal_default_interrupt_vsr_p:
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172 .long _cyg_hal_default_interrupt_vsr
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173
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174 .extern _hal_vsr_table
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175 $_hal_vsr_table_p:
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176 .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4
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177
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178 2:
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179 .endm
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180
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181 #else
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182
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183 .macro hal_mon_init
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184 .endm
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185
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186 #endif
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187
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188
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189 #define CYGPKG_HAL_SH_MON_DEFINED
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190
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191 #endif // CYGPKG_HAL_SH_MON_DEFINED
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192
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193 #endif // CYGONCE_HAL_PLATFORM_INC