Mercurial > flash_v2
annotate packages/kernel/current/tests/kcache2.c @ 191:678094f34118
Merge from eCos master repository on 2001-10-19-06:43:02-BST
| author | jlarmour |
|---|---|
| date | Fri, 19 Oct 2001 07:02:26 +0000 |
| parents | 6b5f480c6929 |
| children | 67850532eebb |
| rev | line source |
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| 2 | 1 /*================================================================= |
| 2 // | |
| 3 // kcache2.c | |
| 4 // | |
| 5 // Cache feature/timing tests | |
| 6 // | |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.1 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.redhat.com/ |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 2 | 30 //####COPYRIGHTEND#### |
| 31 //========================================================================== | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 34 // Author(s): jskov, based on kcache1.c by dsm | |
| 35 // Contributors: jskov | |
| 36 // Date: 1998-12-10 | |
| 37 // Description: Tests some of the more exotic cache macros. | |
| 38 //####DESCRIPTIONEND#### | |
| 39 */ | |
| 40 | |
| 41 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL | |
| 42 | |
| 43 #include <cyg/kernel/kapi.h> | |
| 44 | |
| 45 #include <cyg/infra/testcase.h> | |
| 46 | |
| 47 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK | |
| 48 #ifdef CYGFUN_KERNEL_API_C | |
| 49 | |
| 50 #include <cyg/infra/diag.h> | |
| 51 #include <cyg/hal/hal_cache.h> | |
| 52 | |
| 53 // ------------------------------------------------------------------------- | |
| 54 | |
| 55 #define NTHREADS 1 | |
| 56 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL | |
| 57 | |
| 58 // The following are defaults for loop variables. Note they will be overriden | |
| 59 // on simulator targets, where detected - there is no point testing a cache | |
| 60 // which doesn't exist :-). | |
| 61 | |
| 62 #define TEST_DZERO_LOOPS 5000 // default number of loops for test_dzero() | |
| 63 #define TIME_ILOCK_LOOPS 10000 // default number of loops for time_ilock() | |
| 64 #define TIME_DLOCK_LOOPS 10000 // default number of loops for time_dlock() | |
| 65 | |
| 66 | |
| 67 static cyg_handle_t thread[NTHREADS]; | |
| 68 | |
| 69 static cyg_thread thread_obj[NTHREADS]; | |
| 70 static char stack[NTHREADS][STACKSIZE]; | |
| 71 | |
| 72 #define MAXSIZE 1<<18 | |
| 73 | |
| 74 volatile char m[MAXSIZE]; | |
| 75 | |
| 76 // ------------------------------------------------------------------------- | |
| 77 // Test of data cache zero. | |
| 78 // o Timing comparison with instructions doing the same amount of work. | |
| 79 // o Check that area cleared with the DCACHE_ZERO macro contains zeros. | |
| 80 #ifdef HAL_DCACHE_ZERO | |
| 81 static void test_dzero(void) | |
| 82 { | |
| 83 register cyg_uint32 k, i; | |
| 84 cyg_tick_count_t count0, count1; | |
| 85 cyg_ucount32 t; | |
| 86 volatile cyg_uint32* aligned_p; | |
| 87 volatile cyg_uint32* p; | |
| 88 register CYG_INTERRUPT_STATE oldints; | |
| 89 cyg_ucount32 test_dzero_loops = TEST_DZERO_LOOPS; | |
| 90 | |
| 91 CYG_TEST_INFO("Data cache zero"); | |
| 92 | |
| 93 if (cyg_test_is_simulator) | |
| 94 test_dzero_loops=10; | |
| 95 | |
| 96 aligned_p = (volatile cyg_uint32*) | |
| 97 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) | |
| 98 & ~(HAL_DCACHE_LINE_SIZE-1)); | |
| 99 | |
| 100 // Time with conventional instructions. | |
| 101 HAL_DISABLE_INTERRUPTS(oldints); | |
| 102 HAL_DCACHE_SYNC(); | |
| 103 HAL_DCACHE_DISABLE(); | |
| 104 HAL_DCACHE_SYNC(); | |
| 105 HAL_DCACHE_INVALIDATE_ALL(); | |
| 106 HAL_DCACHE_ENABLE(); | |
| 107 HAL_RESTORE_INTERRUPTS(oldints); | |
| 108 count0 = cyg_current_time(); | |
| 109 for (k = 0; k < test_dzero_loops; k++) { | |
| 110 p = aligned_p; | |
| 111 for (i = 0; i < HAL_DCACHE_SETS; i++) { | |
| 112 #if (16 == HAL_DCACHE_LINE_SIZE) | |
| 113 *p++ = 0; | |
| 114 *p++ = 0; | |
| 115 *p++ = 0; | |
| 116 *p++ = 0; | |
| 117 #else | |
| 118 #error "Not defined for this cache line size." | |
| 119 #endif | |
| 120 } | |
| 121 | |
| 122 HAL_DISABLE_INTERRUPTS(oldints); | |
| 123 HAL_DCACHE_SYNC(); | |
| 124 HAL_DCACHE_DISABLE(); | |
| 125 HAL_DCACHE_SYNC(); | |
| 126 HAL_DCACHE_INVALIDATE_ALL(); | |
| 127 HAL_DCACHE_ENABLE(); | |
| 128 HAL_RESTORE_INTERRUPTS(oldints); | |
| 129 } | |
| 130 count1 = cyg_current_time(); | |
| 131 t = count1 - count0; | |
| 132 diag_printf("time with instructions: %d\n", t); | |
| 133 | |
| 134 // Initialize the area with non-zero so we can check whether | |
| 135 // the macro cleared the area properly. | |
| 136 p = aligned_p; | |
| 137 for (i = 0; | |
| 138 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32); | |
| 139 i++) { | |
| 140 *p++ = 0xdeadbeef; | |
| 141 } | |
| 142 | |
| 143 // Time with DCACHE_ZERO. | |
| 144 HAL_DISABLE_INTERRUPTS(oldints); | |
| 145 HAL_DCACHE_SYNC(); | |
| 146 HAL_DCACHE_DISABLE(); | |
| 147 HAL_DCACHE_SYNC(); | |
| 148 HAL_DCACHE_INVALIDATE_ALL(); | |
| 149 HAL_DCACHE_ENABLE(); | |
| 150 HAL_RESTORE_INTERRUPTS(oldints); | |
| 151 count0 = cyg_current_time(); | |
| 152 for (k = 0; k < test_dzero_loops; k++) { | |
| 153 HAL_DCACHE_ZERO(aligned_p, HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); | |
| 154 | |
| 155 HAL_DISABLE_INTERRUPTS(oldints); | |
| 156 HAL_DCACHE_SYNC(); | |
| 157 HAL_DCACHE_DISABLE(); | |
| 158 HAL_DCACHE_SYNC(); | |
| 159 HAL_DCACHE_INVALIDATE_ALL(); | |
| 160 HAL_DCACHE_ENABLE(); | |
| 161 HAL_RESTORE_INTERRUPTS(oldints); | |
| 162 } | |
| 163 count1 = cyg_current_time(); | |
| 164 t = count1 - count0; | |
| 165 diag_printf("time with HAL_DCACHE_ZERO: %d\n", t); | |
| 166 | |
| 167 // Verify that the area was actually cleared. | |
| 168 { | |
| 169 cyg_uint32 d; | |
| 170 | |
| 171 d = 0; | |
| 172 p = aligned_p; | |
| 173 for (i = 0; | |
| 174 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32); | |
| 175 i++) { | |
| 176 d |= *p++; | |
| 177 } | |
| 178 | |
| 179 CYG_TEST_CHECK(0 == d, "region not properly cleared"); | |
| 180 } | |
| 181 | |
| 182 } | |
| 183 #endif | |
| 184 | |
| 185 // ------------------------------------------------------------------------- | |
| 186 // Test of data cache write hint. | |
| 187 // Just check that the macro compiles. | |
| 188 #ifdef HAL_DCACHE_WRITE_HINT | |
| 189 static void test_dwrite_hint(void) | |
| 190 { | |
| 191 register cyg_uint32 k; | |
| 192 register CYG_INTERRUPT_STATE oldints; | |
| 193 | |
| 194 CYG_TEST_INFO("Data cache write hint"); | |
| 195 | |
| 196 HAL_DISABLE_INTERRUPTS(oldints); | |
| 197 HAL_DCACHE_SYNC(); | |
| 198 HAL_DCACHE_DISABLE(); | |
| 199 HAL_DCACHE_SYNC(); | |
| 200 HAL_DCACHE_INVALIDATE_ALL(); | |
| 201 HAL_DCACHE_ENABLE(); | |
| 202 HAL_RESTORE_INTERRUPTS(oldints); | |
| 203 | |
| 204 HAL_DCACHE_WRITE_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE); | |
| 205 for (k = 0; k < 20; k++); | |
| 206 m[HAL_DCACHE_LINE_SIZE*2] = 42; | |
| 207 } | |
| 208 #endif | |
| 209 | |
| 210 // ------------------------------------------------------------------------- | |
| 211 // Test of data cache read hint. | |
| 212 // Just check that the macro compiles. | |
| 213 #ifdef HAL_DCACHE_READ_HINT | |
| 214 static void test_dread_hint(void) | |
| 215 { | |
| 216 register char c; | |
| 217 register cyg_uint32 k; | |
| 218 register CYG_INTERRUPT_STATE oldints; | |
| 219 | |
| 220 CYG_TEST_INFO("Data cache read hint"); | |
| 221 | |
| 222 HAL_DISABLE_INTERRUPTS(oldints); | |
| 223 HAL_DCACHE_SYNC(); | |
| 224 HAL_DCACHE_DISABLE(); | |
| 225 HAL_DCACHE_SYNC(); | |
| 226 HAL_DCACHE_INVALIDATE_ALL(); | |
| 227 HAL_DCACHE_ENABLE(); | |
| 228 HAL_RESTORE_INTERRUPTS(oldints); | |
| 229 | |
| 230 HAL_DCACHE_READ_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE); | |
| 231 for (k = 0; k < 20; k++); | |
| 232 c = m[HAL_DCACHE_LINE_SIZE*2]; | |
| 233 } | |
| 234 #endif | |
| 235 | |
| 236 // ------------------------------------------------------------------------- | |
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237 // Test of data cache line store |
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238 // o No semantic requirement. |
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239 // o Check that flushed data is written to memory. |
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240 // o Simple invocation check of macro. |
| 2 | 241 #ifdef HAL_DCACHE_STORE |
| 242 static void test_dstore(void) | |
| 243 { | |
| 244 volatile cyg_uint8* aligned_p; | |
| 245 cyg_int32 i; | |
| 246 register CYG_INTERRUPT_STATE oldints; | |
| 247 | |
| 248 CYG_TEST_INFO("Data cache store region"); | |
| 249 | |
| 250 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) | |
| 251 m[i] = 0; | |
| 252 | |
| 253 HAL_DISABLE_INTERRUPTS(oldints); | |
| 254 HAL_DCACHE_SYNC(); | |
| 255 HAL_DCACHE_DISABLE(); | |
| 256 HAL_DCACHE_SYNC(); | |
| 257 HAL_DCACHE_INVALIDATE_ALL(); | |
| 258 HAL_DCACHE_ENABLE(); | |
| 259 HAL_RESTORE_INTERRUPTS(oldints); | |
| 260 | |
| 261 aligned_p = (volatile cyg_uint8*) | |
| 262 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) | |
| 263 & ~(HAL_DCACHE_LINE_SIZE-1)); | |
| 264 | |
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265 HAL_DISABLE_INTERRUPTS(oldints); |
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266 |
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267 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used! |
| 2 | 268 |
| 269 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE); | |
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270 |
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271 HAL_RESTORE_INTERRUPTS(oldints); |
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272 |
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273 CYG_TEST_CHECK(42 == aligned_p[0], |
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274 "memory didn't contain flushed data"); |
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275 |
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276 HAL_DCACHE_INVALIDATE_ALL(); // Discard... |
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277 |
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278 CYG_TEST_CHECK(42 == aligned_p[0], |
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279 "memory didn't contain flushed data after invalidate all"); |
| 2 | 280 } |
| 281 #endif | |
| 282 | |
| 283 // ------------------------------------------------------------------------- | |
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284 // Test of data cache total flush (sync). |
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285 // o No semantic requirement. |
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286 // o Check that flushed data is written to memory. |
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287 // o Simple invocation check of macro. |
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288 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory |
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289 static void test_dsync(void) |
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290 { |
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291 volatile cyg_uint8* aligned_p; |
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292 cyg_int32 i; |
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293 register CYG_INTERRUPT_STATE oldints; |
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294 |
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295 CYG_TEST_INFO("Data cache sync all"); |
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296 |
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297 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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298 m[i] = 0; |
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299 |
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300 HAL_DISABLE_INTERRUPTS(oldints); |
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301 HAL_DCACHE_SYNC(); |
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302 HAL_DCACHE_DISABLE(); |
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303 HAL_DCACHE_SYNC(); |
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304 HAL_DCACHE_INVALIDATE_ALL(); |
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305 HAL_DCACHE_ENABLE(); |
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306 HAL_RESTORE_INTERRUPTS(oldints); |
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307 |
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308 aligned_p = (volatile cyg_uint8*) |
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309 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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310 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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311 |
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312 HAL_DISABLE_INTERRUPTS(oldints); |
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313 |
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314 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used! |
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315 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1]; |
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316 |
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317 HAL_DCACHE_SYNC(); |
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318 |
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319 HAL_RESTORE_INTERRUPTS(oldints); |
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320 |
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321 CYG_TEST_CHECK(42 == aligned_p[0], |
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322 "memory didn't contain flushed data"); |
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323 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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324 "memory didn't contain flushed data next block"); |
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325 |
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326 HAL_DCACHE_INVALIDATE_ALL(); |
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327 |
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328 CYG_TEST_CHECK(42 == aligned_p[0], |
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329 "memory didn't contain flushed data after invalidate"); |
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330 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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331 "memory didn't contain flushed data next block after invalidate"); |
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332 |
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333 HAL_DCACHE_DISABLE(); |
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334 |
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335 CYG_TEST_CHECK(42 == aligned_p[0], |
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336 "memory didn't contain flushed data after disable"); |
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337 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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338 "memory didn't contain flushed data next block after disable"); |
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339 |
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340 HAL_DCACHE_ENABLE(); |
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341 } |
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342 #endif // HAL_DCACHE_LINE_SIZE |
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343 |
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344 // ------------------------------------------------------------------------- |
| 2 | 345 // Test of data cache line flush. |
| 346 // o Requires write-back cache. | |
| 347 // o Check that flushed data is written to memory. | |
| 348 // o Simple range check of macro. | |
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349 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test: |
| 2 | 350 #ifdef HAL_DCACHE_FLUSH |
| 351 static void test_dflush(void) | |
| 352 { | |
| 353 volatile cyg_uint8* aligned_p; | |
| 354 cyg_int32 i; | |
| 355 register CYG_INTERRUPT_STATE oldints; | |
| 356 | |
| 357 CYG_TEST_INFO("Data cache flush region"); | |
| 358 | |
| 359 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) | |
| 360 m[i] = 0; | |
| 361 | |
| 362 HAL_DISABLE_INTERRUPTS(oldints); | |
| 363 HAL_DCACHE_SYNC(); | |
| 364 HAL_DCACHE_DISABLE(); | |
| 365 HAL_DCACHE_SYNC(); | |
| 366 HAL_DCACHE_INVALIDATE_ALL(); | |
| 367 HAL_DCACHE_ENABLE(); | |
| 368 HAL_RESTORE_INTERRUPTS(oldints); | |
| 369 | |
| 370 aligned_p = (volatile cyg_uint8*) | |
| 371 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) | |
| 372 & ~(HAL_DCACHE_LINE_SIZE-1)); | |
| 373 | |
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374 HAL_DISABLE_INTERRUPTS(oldints); |
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375 |
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376 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used! |
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377 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1]; |
| 2 | 378 |
| 379 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE); | |
| 380 | |
| 381 HAL_DCACHE_DISABLE(); | |
| 382 | |
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383 HAL_RESTORE_INTERRUPTS(oldints); |
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384 |
| 2 | 385 CYG_TEST_CHECK(42 == aligned_p[0], |
| 386 "memory didn't contain flushed data"); | |
| 387 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE], | |
| 388 "flushed beyond region"); | |
| 389 | |
| 390 HAL_DCACHE_ENABLE(); | |
| 391 } | |
| 392 #endif | |
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393 #endif |
| 2 | 394 |
| 395 // ------------------------------------------------------------------------- | |
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396 // Test of data cache disable (which does NOT force contents out to RAM) |
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397 // o Requires write-back cache [so NOT invoked unconditionally] |
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398 // o Check that dirty data is not written to memory and is invalidated |
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399 // in the cache. |
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400 // o Simple invocation check of macro. |
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401 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test: |
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402 static void test_ddisable(void) |
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403 { |
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404 volatile cyg_uint8* aligned_p; |
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405 cyg_int32 i; |
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406 register CYG_INTERRUPT_STATE oldints; |
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407 |
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408 CYG_TEST_INFO("Data cache gross disable"); |
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409 |
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410 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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411 m[i] = 0; |
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412 |
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413 HAL_DISABLE_INTERRUPTS(oldints); |
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414 HAL_DCACHE_SYNC(); |
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415 HAL_DCACHE_DISABLE(); |
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416 HAL_DCACHE_SYNC(); |
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417 HAL_DCACHE_INVALIDATE_ALL(); |
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418 HAL_DCACHE_ENABLE(); |
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419 HAL_RESTORE_INTERRUPTS(oldints); |
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420 |
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421 aligned_p = (volatile cyg_uint8*) |
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422 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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423 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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424 |
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425 HAL_DISABLE_INTERRUPTS(oldints); |
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426 |
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427 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used! |
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428 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43; |
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429 |
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430 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1]; |
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431 |
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432 HAL_DCACHE_DISABLE(); |
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433 |
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434 HAL_RESTORE_INTERRUPTS(oldints); |
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435 |
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436 CYG_TEST_CHECK(0 == aligned_p[0] && |
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437 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], |
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438 "cache/memory contained invalidated data"); |
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439 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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440 "next block contained invalidated data"); |
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441 |
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442 HAL_DCACHE_ENABLE(); |
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443 } |
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444 #endif // def HAL_DCACHE_QUERY_WRITE_MODE |
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445 |
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446 // ------------------------------------------------------------------------- |
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447 // Test of data cache total invalidate. |
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448 // o Requires write-back cache. |
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449 // o Check that invalidated data is not written to memory and is invalidated |
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450 // in the cache. |
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451 // o Simple invocation check of macro. |
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452 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test: |
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453 #ifdef HAL_DCACHE_INVALIDATE_ALL |
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454 static void test_dinvalidate_all(void) |
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455 { |
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456 volatile cyg_uint8* aligned_p; |
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457 cyg_int32 i; |
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458 register CYG_INTERRUPT_STATE oldints; |
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459 |
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460 CYG_TEST_INFO("Data cache invalidate all"); |
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461 |
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462 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) |
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463 m[i] = 0; |
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464 |
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465 HAL_DISABLE_INTERRUPTS(oldints); |
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466 HAL_DCACHE_SYNC(); |
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467 HAL_DCACHE_DISABLE(); |
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468 HAL_DCACHE_SYNC(); |
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469 HAL_DCACHE_INVALIDATE_ALL(); |
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470 HAL_DCACHE_ENABLE(); |
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471 HAL_RESTORE_INTERRUPTS(oldints); |
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472 |
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473 aligned_p = (volatile cyg_uint8*) |
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474 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) |
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475 & ~(HAL_DCACHE_LINE_SIZE-1)); |
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476 |
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477 HAL_DISABLE_INTERRUPTS(oldints); |
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478 |
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479 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used! |
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480 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43; |
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481 |
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482 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1]; |
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483 |
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484 HAL_DCACHE_INVALIDATE_ALL(); |
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485 |
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486 HAL_RESTORE_INTERRUPTS(oldints); |
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487 |
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488 CYG_TEST_CHECK(0 == aligned_p[0] && |
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489 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], |
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490 "cache/memory contained invalidated data"); |
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491 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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492 "next block contained invalidated data"); |
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493 } |
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494 #endif |
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495 #endif // def HAL_DCACHE_QUERY_WRITE_MODE |
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496 |
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497 // ------------------------------------------------------------------------- |
| 2 | 498 // Test of data cache line invalidate. |
| 499 // o Requires write-back cache. | |
| 500 // o Check that invalidated data is not written to memory and is invalidated | |
| 501 // in the cache. | |
| 502 // o Simple range check of macro. | |
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503 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test: |
| 2 | 504 #ifdef HAL_DCACHE_INVALIDATE |
| 505 static void test_dinvalidate(void) | |
| 506 { | |
| 507 volatile cyg_uint8* aligned_p; | |
| 508 cyg_int32 i; | |
| 509 register CYG_INTERRUPT_STATE oldints; | |
| 510 | |
| 511 CYG_TEST_INFO("Data cache invalidate region"); | |
| 512 | |
| 513 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++) | |
| 514 m[i] = 0; | |
| 515 | |
| 516 HAL_DISABLE_INTERRUPTS(oldints); | |
| 517 HAL_DCACHE_SYNC(); | |
| 518 HAL_DCACHE_DISABLE(); | |
| 519 HAL_DCACHE_SYNC(); | |
| 520 HAL_DCACHE_INVALIDATE_ALL(); | |
| 521 HAL_DCACHE_ENABLE(); | |
| 522 HAL_RESTORE_INTERRUPTS(oldints); | |
| 523 | |
| 524 aligned_p = (volatile cyg_uint8*) | |
| 525 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2]) | |
| 526 & ~(HAL_DCACHE_LINE_SIZE-1)); | |
| 527 | |
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528 HAL_DISABLE_INTERRUPTS(oldints); |
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529 |
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530 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used! |
| 2 | 531 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43; |
| 532 | |
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533 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1]; |
| 2 | 534 |
| 535 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE); | |
| 536 | |
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537 HAL_RESTORE_INTERRUPTS(oldints); |
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538 |
| 2 | 539 CYG_TEST_CHECK(0 == aligned_p[0] && |
| 540 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], | |
| 541 "cache/memory contained invalidated data"); | |
| 542 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE], | |
| 543 "invalidated beyond range"); | |
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544 |
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545 HAL_DCACHE_SYNC(); |
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546 HAL_DCACHE_DISABLE(); |
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547 |
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548 CYG_TEST_CHECK(0 == aligned_p[0] && |
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549 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1], |
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550 "cache/memory contained invalidated data after SYNC/DIS"); |
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551 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE], |
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552 "invalidated beyond range after SYNC/DIS"); |
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553 |
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554 HAL_DCACHE_ENABLE(); |
| 2 | 555 } |
| 556 #endif | |
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557 #endif // def HAL_DCACHE_QUERY_WRITE_MODE |
| 2 | 558 |
| 559 // ------------------------------------------------------------------------- | |
| 560 // Test of instruction cache locking. | |
| 561 // o Time difference between repeatedly executing a bunch of instructions | |
| 562 // with and without locking. | |
| 563 #ifdef HAL_ICACHE_LOCK | |
| 564 static void iloop(unsigned long* start, unsigned long* end) | |
| 565 { | |
| 566 register char c; | |
| 567 register CYG_INTERRUPT_STATE oldints; | |
| 568 | |
| 569 label_start: | |
| 570 // Invalidating shouldn't affect locked lines. | |
| 571 HAL_DISABLE_INTERRUPTS(oldints); | |
| 572 HAL_ICACHE_DISABLE(); | |
| 573 HAL_ICACHE_INVALIDATE_ALL(); | |
| 574 HAL_ICACHE_ENABLE(); | |
| 575 HAL_RESTORE_INTERRUPTS(oldints); | |
| 576 | |
| 577 c = m[HAL_DCACHE_LINE_SIZE*0]; | |
| 578 c = m[HAL_DCACHE_LINE_SIZE*1]; | |
| 579 c = m[HAL_DCACHE_LINE_SIZE*2]; | |
| 580 c = m[HAL_DCACHE_LINE_SIZE*3]; | |
| 581 c = m[HAL_DCACHE_LINE_SIZE*4]; | |
| 582 c = m[HAL_DCACHE_LINE_SIZE*5]; | |
| 583 c = m[HAL_DCACHE_LINE_SIZE*6]; | |
| 584 c = m[HAL_DCACHE_LINE_SIZE*7]; | |
| 585 c = m[HAL_DCACHE_LINE_SIZE*8]; | |
| 586 c = m[HAL_DCACHE_LINE_SIZE*9]; | |
| 587 c = m[HAL_DCACHE_LINE_SIZE*10]; | |
| 588 c = m[HAL_DCACHE_LINE_SIZE*11]; | |
| 589 c = m[HAL_DCACHE_LINE_SIZE*12]; | |
| 590 c = m[HAL_DCACHE_LINE_SIZE*13]; | |
| 591 c = m[HAL_DCACHE_LINE_SIZE*14]; | |
| 592 c = m[HAL_DCACHE_LINE_SIZE*15]; | |
| 593 c = m[HAL_DCACHE_LINE_SIZE*16]; | |
| 594 c = m[HAL_DCACHE_LINE_SIZE*17]; | |
| 595 c = m[HAL_DCACHE_LINE_SIZE*18]; | |
| 596 c = m[HAL_DCACHE_LINE_SIZE*19]; | |
| 597 c = m[HAL_DCACHE_LINE_SIZE*20]; | |
| 598 c = m[HAL_DCACHE_LINE_SIZE*21]; | |
| 599 c = m[HAL_DCACHE_LINE_SIZE*22]; | |
| 600 c = m[HAL_DCACHE_LINE_SIZE*23]; | |
| 601 c = m[HAL_DCACHE_LINE_SIZE*24]; | |
| 602 c = m[HAL_DCACHE_LINE_SIZE*25]; | |
| 603 c = m[HAL_DCACHE_LINE_SIZE*26]; | |
| 604 c = m[HAL_DCACHE_LINE_SIZE*27]; | |
| 605 c = m[HAL_DCACHE_LINE_SIZE*28]; | |
| 606 c = m[HAL_DCACHE_LINE_SIZE*29]; | |
| 607 c = m[HAL_DCACHE_LINE_SIZE*30]; | |
| 608 c = m[HAL_DCACHE_LINE_SIZE*31]; | |
| 609 c = m[HAL_DCACHE_LINE_SIZE*32]; | |
| 610 c = m[HAL_DCACHE_LINE_SIZE*33]; | |
| 611 c = m[HAL_DCACHE_LINE_SIZE*34]; | |
| 612 c = m[HAL_DCACHE_LINE_SIZE*35]; | |
| 613 c = m[HAL_DCACHE_LINE_SIZE*36]; | |
| 614 c = m[HAL_DCACHE_LINE_SIZE*37]; | |
| 615 c = m[HAL_DCACHE_LINE_SIZE*38]; | |
| 616 c = m[HAL_DCACHE_LINE_SIZE*39]; | |
| 617 c = m[HAL_DCACHE_LINE_SIZE*40]; | |
| 618 c = m[HAL_DCACHE_LINE_SIZE*41]; | |
| 619 c = m[HAL_DCACHE_LINE_SIZE*42]; | |
| 620 c = m[HAL_DCACHE_LINE_SIZE*43]; | |
| 621 c = m[HAL_DCACHE_LINE_SIZE*44]; | |
| 622 c = m[HAL_DCACHE_LINE_SIZE*45]; | |
| 623 c = m[HAL_DCACHE_LINE_SIZE*46]; | |
| 624 c = m[HAL_DCACHE_LINE_SIZE*47]; | |
| 625 c = m[HAL_DCACHE_LINE_SIZE*48]; | |
| 626 c = m[HAL_DCACHE_LINE_SIZE*49]; | |
| 627 c = m[HAL_DCACHE_LINE_SIZE*50]; | |
| 628 c = m[HAL_DCACHE_LINE_SIZE*51]; | |
| 629 c = m[HAL_DCACHE_LINE_SIZE*52]; | |
| 630 c = m[HAL_DCACHE_LINE_SIZE*53]; | |
| 631 c = m[HAL_DCACHE_LINE_SIZE*54]; | |
| 632 c = m[HAL_DCACHE_LINE_SIZE*55]; | |
| 633 c = m[HAL_DCACHE_LINE_SIZE*56]; | |
| 634 c = m[HAL_DCACHE_LINE_SIZE*57]; | |
| 635 c = m[HAL_DCACHE_LINE_SIZE*58]; | |
| 636 c = m[HAL_DCACHE_LINE_SIZE*59]; | |
| 637 c = m[HAL_DCACHE_LINE_SIZE*60]; | |
| 638 c = m[HAL_DCACHE_LINE_SIZE*61]; | |
| 639 c = m[HAL_DCACHE_LINE_SIZE*62]; | |
| 640 c = m[HAL_DCACHE_LINE_SIZE*63]; | |
| 641 | |
| 642 label_end: | |
| 643 | |
| 644 *start = (unsigned long) &&label_start; | |
| 645 *end = (unsigned long) &&label_end; | |
| 646 } | |
| 647 | |
| 648 static void time_ilock(void) | |
| 649 { | |
| 650 register cyg_ucount32 k; | |
| 651 cyg_tick_count_t count0, count1; | |
| 652 cyg_ucount32 t; | |
| 653 unsigned long start, end; | |
| 654 register cyg_ucount32 time_ilock_loops = TIME_ILOCK_LOOPS; | |
| 655 | |
| 656 CYG_TEST_INFO("Instruction cache lock"); | |
| 657 | |
| 658 if (cyg_test_is_simulator) | |
| 659 time_ilock_loops = 10; | |
| 660 | |
| 661 count0 = cyg_current_time(); | |
| 662 for (k = 0; k < time_ilock_loops; k++) { | |
| 663 iloop(&start, &end); | |
| 664 } | |
| 665 count1 = cyg_current_time(); | |
| 666 t = count1 - count0; | |
| 667 diag_printf("time without lock: %d\n", t); | |
| 668 | |
| 669 HAL_ICACHE_LOCK(start, end-start); | |
| 670 | |
| 671 count0 = cyg_current_time(); | |
| 672 for (k = 0; k < time_ilock_loops; k++) { | |
| 673 iloop(&start, &end); | |
| 674 } | |
| 675 count1 = cyg_current_time(); | |
| 676 t = count1 - count0; | |
| 677 diag_printf("time with lock: %d\n", t); | |
| 678 | |
| 679 HAL_ICACHE_UNLOCK(start, end-start); | |
| 680 } | |
| 681 #endif // ifdef HAL_ICACHE_LOCK | |
| 682 | |
| 683 // ------------------------------------------------------------------------- | |
| 684 // Test of data cache locking. | |
| 685 // o Time difference between repeatedly accessing a memory region | |
| 686 // with and without locking. | |
| 687 #ifdef HAL_DCACHE_LOCK | |
| 688 static void dloop(void) | |
| 689 { | |
| 690 register cyg_uint32 j; | |
| 691 register char c; | |
| 692 register CYG_INTERRUPT_STATE oldints; | |
| 693 | |
| 694 HAL_DISABLE_INTERRUPTS(oldints); | |
| 695 HAL_DCACHE_SYNC(); | |
| 696 HAL_DCACHE_DISABLE(); | |
| 697 HAL_DCACHE_SYNC(); | |
| 698 HAL_DCACHE_INVALIDATE_ALL(); | |
| 699 HAL_DCACHE_ENABLE(); | |
| 700 HAL_RESTORE_INTERRUPTS(oldints); | |
| 701 for (j = 0; j < HAL_DCACHE_SETS; j++) { | |
| 702 c = m[HAL_DCACHE_LINE_SIZE*j]; | |
| 703 } | |
| 704 } | |
| 705 | |
| 706 static void time_dlock(void) | |
| 707 { | |
| 708 register cyg_ucount32 k; | |
| 709 cyg_tick_count_t count0, count1; | |
| 710 cyg_ucount32 t; | |
| 711 register cyg_ucount32 time_dlock_loops = TIME_DLOCK_LOOPS; | |
| 712 | |
| 713 CYG_TEST_INFO("Data cache lock"); | |
| 714 | |
| 715 if (cyg_test_is_simulator) | |
| 716 time_dlock_loops = 10; | |
| 717 | |
| 718 count0 = cyg_current_time(); | |
| 719 for (k = 0; k < time_dlock_loops; k++) { | |
| 720 dloop(); | |
| 721 } | |
| 722 count1 = cyg_current_time(); | |
| 723 t = count1 - count0; | |
| 724 diag_printf("time without lock: %d\n", t); | |
| 725 | |
| 726 HAL_DCACHE_LOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); | |
| 727 | |
| 728 count0 = cyg_current_time(); | |
| 729 for (k = 0; k < time_dlock_loops; k++) { | |
| 730 dloop(); | |
| 731 } | |
| 732 count1 = cyg_current_time(); | |
| 733 t = count1 - count0; | |
| 734 diag_printf("time with lock: %d\n", t); | |
| 735 | |
| 736 HAL_DCACHE_UNLOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE); | |
| 737 } | |
| 738 #endif // ifdef HAL_DCACHE_LOCK | |
| 739 | |
| 740 // ------------------------------------------------------------------------- | |
| 741 static void entry0( cyg_addrword_t data ) | |
| 742 { | |
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743 int numtests = 0; |
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744 #ifdef HAL_DCACHE_QUERY_WRITE_MODE |
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745 int wmode; |
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746 #endif |
| 2 | 747 #ifdef HAL_DCACHE_LOCK |
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748 time_dlock(); numtests++; |
| 2 | 749 #endif |
| 750 #ifdef HAL_ICACHE_LOCK | |
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751 time_ilock(); numtests++; |
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752 #endif |
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753 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory |
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754 test_dsync(); numtests++; |
| 2 | 755 #endif |
| 756 #ifdef HAL_DCACHE_STORE | |
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757 test_dstore(); numtests++; |
| 2 | 758 #endif |
| 759 #ifdef HAL_DCACHE_READ_HINT | |
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760 test_dread_hint(); numtests++; |
| 2 | 761 #endif |
| 762 #ifdef HAL_DCACHE_WRITE_HINT | |
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763 test_dwrite_hint(); numtests++; |
| 2 | 764 #endif |
| 765 #ifdef HAL_DCACHE_ZERO | |
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766 test_dzero(); numtests++; |
| 2 | 767 #endif |
| 768 | |
| 769 // The below tests only work on a copy-back cache. | |
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770 #ifdef HAL_DCACHE_QUERY_WRITE_MODE |
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771 HAL_DCACHE_QUERY_WRITE_MODE( wmode ); |
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772 |
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773 if ( HAL_DCACHE_WRITEBACK_MODE == wmode ) { |
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774 test_ddisable(); numtests++; |
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775 #ifdef HAL_DCACHE_INVALIDATE |
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776 test_dinvalidate_all(); numtests++; |
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777 #endif |
| 2 | 778 #ifdef HAL_DCACHE_FLUSH |
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779 test_dflush(); numtests++; |
| 2 | 780 #endif |
| 781 #ifdef HAL_DCACHE_INVALIDATE | |
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782 test_dinvalidate(); numtests++; |
| 2 | 783 #endif |
| 784 } | |
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785 #endif // def HAL_DCACHE_QUERY_WRITE_MODE |
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786 if ( numtests ) { |
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787 CYG_TEST_PASS_FINISH("End of test"); |
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788 } |
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789 else { |
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790 CYG_TEST_NA( "No applicable cache tests" ); |
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791 } |
| 2 | 792 } |
| 793 | |
| 794 // ------------------------------------------------------------------------- | |
| 795 | |
| 796 void kcache2_main( void ) | |
| 797 { | |
| 798 CYG_TEST_INIT(); | |
| 799 | |
| 800 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache2", | |
| 801 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]); | |
| 802 cyg_thread_resume(thread[0]); | |
| 803 | |
| 804 cyg_scheduler_start(); | |
| 805 } | |
| 806 | |
| 807 // ------------------------------------------------------------------------- | |
| 808 | |
| 809 externC void | |
| 810 cyg_start( void ) | |
| 811 { | |
| 812 kcache2_main(); | |
| 813 } | |
| 814 | |
| 815 // ------------------------------------------------------------------------- | |
| 816 | |
| 817 #else // def CYGFUN_KERNEL_API_C | |
| 818 #define N_A_MSG "Kernel C API layer disabled" | |
| 819 #endif // def CYGFUN_KERNEL_API_C | |
| 820 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK | |
| 821 #define N_A_MSG "Kernel real-time clock disabled" | |
| 822 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK | |
| 823 | |
| 824 #ifdef N_A_MSG | |
| 825 externC void | |
| 826 cyg_start( void ) | |
| 827 { | |
| 828 CYG_TEST_INIT(); | |
| 829 CYG_TEST_NA( N_A_MSG ); | |
| 830 } | |
| 831 #endif // N_A_MSG | |
| 832 | |
| 833 // ------------------------------------------------------------------------- | |
| 834 /* EOF kcache2.c */ |
