Mercurial > flash_v2
annotate packages/hal/powerpc/arch/current/src/hal_misc.c @ 18:7253dcc42a09 ecos-sw-1999-06-25
Merge from eCos master repository on 1999-06-25-15:31:50-BST
| author | jlarmour |
|---|---|
| date | Fri, 25 Jun 1999 08:28:05 +0000 |
| parents | 4f2df4ab82c8 |
| children | 5af43b635655 |
| rev | line source |
|---|---|
| 2 | 1 //========================================================================== |
| 0 | 2 // |
| 3 // hal_misc.c | |
| 4 // | |
| 5 // HAL miscellaneous functions | |
| 6 // | |
| 2 | 7 //========================================================================== |
| 0 | 8 //####COPYRIGHTBEGIN#### |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 // by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. |
| 26 // All Rights Reserved. | |
| 0 | 27 // ------------------------------------------- |
| 28 // | |
| 29 //####COPYRIGHTEND#### | |
| 2 | 30 //========================================================================== |
| 0 | 31 //#####DESCRIPTIONBEGIN#### |
| 32 // | |
| 2 | 33 // Author(s): nickg, jskov |
| 34 // Contributors: nickg, jskov, | |
| 35 // jlarmour | |
| 36 // Date: 1999-02-20 | |
| 37 // Purpose: HAL miscellaneous functions | |
| 38 // Description: This file contains miscellaneous functions provided by the | |
| 39 // HAL. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 2 | 43 //=========================================================================== |
| 0 | 44 |
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45 #include <pkgconf/system.h> |
| 0 | 46 #include <pkgconf/hal.h> |
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47 #include CYGBLD_HAL_TARGET_H |
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48 #include CYGBLD_HAL_PLATFORM_H |
| 0 | 49 |
| 2 | 50 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
| 51 #include <cyg/hal/ppc_regs.h> // SPR definitions | |
| 52 | |
| 0 | 53 #include <cyg/infra/cyg_type.h> |
| 54 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 55 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 2 | 56 #include <cyg/infra/diag.h> // diag_printf |
| 0 | 57 |
| 58 #include <cyg/hal/hal_arch.h> // HAL header | |
| 2 | 59 #include <cyg/hal/hal_cache.h> // HAL cache |
| 60 #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ | |
| 61 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 62 # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions | |
| 63 #endif | |
| 0 | 64 |
| 65 //--------------------------------------------------------------------------- | |
| 2 | 66 // Functions used during initialization. |
| 0 | 67 |
| 2 | 68 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
| 69 cyg_bool cyg_hal_stop_constructors; | |
| 70 #endif | |
| 71 | |
| 72 typedef void (*pfunc) (void); | |
| 73 extern pfunc __CTOR_LIST__[]; | |
| 74 extern pfunc __CTOR_END__[]; | |
| 0 | 75 |
| 2 | 76 void |
| 77 cyg_hal_invoke_constructors (void) | |
| 78 { | |
| 79 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG | |
| 80 static pfunc *p = &__CTOR_END__[-1]; | |
| 81 | |
| 82 cyg_hal_stop_constructors = 0; | |
| 83 for (; p >= __CTOR_LIST__; p--) { | |
| 84 (*p) (); | |
| 85 if (cyg_hal_stop_constructors) { | |
| 86 p--; | |
| 87 break; | |
| 0 | 88 } |
| 89 } | |
| 2 | 90 #else |
| 91 pfunc *p; | |
| 92 | |
| 93 for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) | |
| 94 (*p) (); | |
| 95 #endif | |
| 0 | 96 } |
| 97 | |
| 98 // Override any __eabi the compiler might generate. We don't want | |
| 99 // constructors to be called twice. | |
| 100 void __eabi (void) {} | |
| 101 | |
| 102 //--------------------------------------------------------------------------- | |
| 103 // First level C exception handler. | |
| 104 | |
| 105 externC void __handle_exception (void); | |
| 106 | |
| 107 externC HAL_SavedRegisters *_hal_registers; | |
| 108 | |
| 2 | 109 void |
| 110 cyg_hal_exception_handler(HAL_SavedRegisters *regs) | |
| 0 | 111 { |
| 112 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 113 | |
| 114 // Set the pointer to the registers of the current exception | |
| 115 // context. At entry the GDB stub will expand the | |
| 116 // HAL_SavedRegisters structure into a (bigger) register array. | |
| 117 _hal_registers = regs; | |
| 118 | |
| 119 __handle_exception(); | |
| 120 | |
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121 |
| 2 | 122 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ |
| 123 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 124 int vector = regs->vector>>8; | |
| 0 | 125 |
| 126 // We should decode the vector and pass a more appropriate | |
| 127 // value as the second argument. For now we simply pass a | |
| 128 // pointer to the saved registers. We should also divert | |
| 129 // breakpoint and other debug vectors into the debug stubs. | |
| 130 | |
| 2 | 131 if (vector==CYGNUM_HAL_VECTOR_PROGRAM) { |
| 132 int srr1; | |
| 133 CYGARC_MFSPR(CYGARC_REG_SRR1, srr1); // get srr1 | |
| 134 | |
| 135 switch ((srr1 >> 17) & 0xf) { | |
| 136 case 1: | |
| 137 vector = CYGNUM_HAL_EXCEPTION_TRAP; | |
| 138 break; | |
| 139 case 2: | |
| 140 vector = CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION; | |
| 141 break; | |
| 142 case 4: | |
| 143 vector = CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION; | |
| 144 break; | |
| 145 case 8: | |
| 146 vector = CYGNUM_HAL_EXCEPTION_FPU; | |
| 147 break; | |
| 148 default: | |
| 149 CYG_FAIL("Unknown PROGRAM exception!!"); | |
| 150 } | |
| 151 } | |
| 152 cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs ); | |
| 0 | 153 |
| 154 #else | |
| 155 | |
| 156 CYG_FAIL("Exception!!!"); | |
| 157 | |
| 158 #endif | |
| 159 | |
| 160 return; | |
| 161 } | |
| 162 | |
| 163 //--------------------------------------------------------------------------- | |
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164 // Default ISRs |
| 0 | 165 |
| 2 | 166 externC cyg_uint32 |
| 167 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 0 | 168 { |
| 2 | 169 diag_printf("Interrupt: %d\n", vector); |
| 170 | |
| 0 | 171 CYG_FAIL("Spurious Interrupt!!!"); |
| 172 return 0; | |
| 173 } | |
| 174 | |
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175 // The decrementer default ISR has to do nothing. The reason is that |
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176 // decrementer interrupts cannot be disabled - if a kernel configuration |
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177 // does not use the RTC, but does use external interrupts, the decrementer |
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178 // underflow could cause a CYG_FAIL (as above) even though the user did |
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179 // not expect any decrementer interrupts to happen. |
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180 externC cyg_uint32 |
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181 hal_default_decrementer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
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182 { |
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183 return 0; |
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184 } |
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185 |
| 0 | 186 //--------------------------------------------------------------------------- |
| 187 // Idle thread action | |
| 188 | |
| 2 | 189 void |
| 190 hal_idle_thread_action( cyg_uint32 count ) | |
| 0 | 191 { |
| 192 } | |
| 193 | |
| 194 //--------------------------------------------------------------------------- | |
| 2 | 195 // Use MMU resources to map memory regions. |
| 196 // Takes and returns an int used to ID the MMU resource to use. This ID | |
| 197 // is increased as resources are used and should be used for subsequent | |
| 198 // invocations. | |
| 199 static int | |
| 200 hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, | |
| 201 cyg_int32 size, cyg_uint8 flags) | |
| 202 { | |
| 203 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 204 { | |
| 205 // Use BATs to map the memory. | |
| 206 cyg_uint32 ubat, lbat; | |
| 207 | |
| 208 ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; | |
| 209 lbat = (phys & LBAT_BRPNMASK); | |
| 210 if (flags & CYGARC_MEMDESC_CI) | |
| 211 lbat |= LBAT_I; | |
| 212 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 213 lbat |= LBAT_G; | |
| 214 | |
| 215 // There are 4 BATs, size is programmable. | |
| 216 while (id < 4 && size > 0) { | |
| 217 cyg_uint32 blk_size = 128*1024; | |
| 218 cyg_uint32 bl = 0; | |
| 219 while (blk_size < 256*1024*1024 && blk_size < size) { | |
| 220 blk_size *= 2; | |
| 221 bl = (bl << 1) | 1; | |
| 222 } | |
| 223 ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); | |
| 224 | |
| 225 switch (id) { | |
| 226 case 0: | |
| 227 CYGARC_MTSPR (IBAT0U, ubat); | |
| 228 CYGARC_MTSPR (IBAT0L, lbat); | |
| 229 CYGARC_MTSPR (DBAT0U, ubat); | |
| 230 CYGARC_MTSPR (DBAT0L, lbat); | |
| 231 break; | |
| 232 case 1: | |
| 233 CYGARC_MTSPR (IBAT1U, ubat); | |
| 234 CYGARC_MTSPR (IBAT1L, lbat); | |
| 235 CYGARC_MTSPR (DBAT1U, ubat); | |
| 236 CYGARC_MTSPR (DBAT1L, lbat); | |
| 237 break; | |
| 238 case 2: | |
| 239 CYGARC_MTSPR (IBAT2U, ubat); | |
| 240 CYGARC_MTSPR (IBAT2L, lbat); | |
| 241 CYGARC_MTSPR (DBAT2U, ubat); | |
| 242 CYGARC_MTSPR (DBAT2L, lbat); | |
| 243 break; | |
| 244 case 3: | |
| 245 CYGARC_MTSPR (IBAT3U, ubat); | |
| 246 CYGARC_MTSPR (IBAT3L, lbat); | |
| 247 CYGARC_MTSPR (DBAT3U, ubat); | |
| 248 CYGARC_MTSPR (DBAT3L, lbat); | |
| 249 break; | |
| 250 } | |
| 251 | |
| 252 size -= blk_size; | |
| 253 id++; | |
| 254 } | |
| 255 } | |
| 256 #endif | |
| 257 | |
| 258 | |
| 259 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 260 { | |
| 261 // The MPC8xx CPUs do not have BATs. Fortunately we don't | |
| 262 // currently use the MMU, so we can simulate BATs by using the | |
| 263 // TLBs. | |
| 264 | |
| 265 cyg_uint32 epn, rpn, ctr, twc; | |
| 266 int max_tlbs; | |
| 267 | |
| 268 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 269 // There are 32 TLBs. | |
| 270 max_tlbs = 32; | |
| 271 #endif | |
| 272 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 273 // There are 8 TLBs. | |
| 274 max_tlbs = 8; | |
| 275 #endif | |
| 276 | |
| 277 epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; | |
| 278 rpn = ((phys & MI_RPN_RPNMASK) | |
| 279 | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V); | |
| 280 if (flags & CYGARC_MEMDESC_CI) | |
| 281 rpn |= MI_RPN_CI; | |
| 282 | |
| 283 twc = MI_TWC_PS8MB | MI_TWC_V; | |
| 284 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 285 twc |= MI_TWC_G; | |
| 286 | |
| 287 // Ignore attempts to use more than max_tlbs. | |
| 288 while (id < max_tlbs && size > 0) { | |
| 289 ctr = id << MI_CTR_INDX_SHIFT; | |
| 290 | |
| 291 // Instruction TLB. | |
| 292 CYGARC_MTSPR (MI_TWC, twc); | |
| 293 CYGARC_MTSPR (MI_CTR, ctr); | |
| 294 CYGARC_MTSPR (MI_EPN, epn); | |
| 295 CYGARC_MTSPR (MI_RPN, rpn); | |
| 296 | |
| 297 // Data TLB. | |
| 298 { | |
| 299 cyg_uint32 drpn; | |
| 300 | |
| 301 // Need to mark data page as changed or an exception | |
| 302 // will be generated on first write to the page. | |
| 303 drpn = rpn | MD_RPN_CHANGED; | |
| 304 | |
| 305 CYGARC_MTSPR (MD_TWC, twc); | |
| 306 CYGARC_MTSPR (MD_CTR, ctr); | |
| 307 CYGARC_MTSPR (MD_EPN, epn); | |
| 308 CYGARC_MTSPR (MD_RPN, drpn); | |
| 309 } | |
| 310 | |
| 311 // Move to next 8MB block. | |
| 312 size -= 8*1024*1024; | |
| 313 epn += 8*1024*1024; | |
| 314 rpn += 8*1024*1024; | |
| 315 id++; | |
| 316 } | |
| 317 } | |
| 318 #endif | |
| 319 | |
| 320 return id; | |
| 321 } | |
| 322 | |
| 323 | |
| 324 // Initialize MMU to a sane (NOP) state. | |
| 325 static void | |
| 326 hal_clear_MMU (void) | |
| 327 { | |
| 328 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 329 { | |
| 330 cyg_uint32 ubat, lbat; | |
| 331 | |
| 332 // Initialize BATs with 0 -- VS&VP are unset, making all matches fail | |
| 333 ubat = 0; | |
| 334 lbat = 0; | |
| 335 | |
| 336 CYGARC_MTSPR (IBAT0U, ubat); | |
| 337 CYGARC_MTSPR (IBAT0L, lbat); | |
| 338 CYGARC_MTSPR (DBAT0U, ubat); | |
| 339 CYGARC_MTSPR (DBAT0L, lbat); | |
| 340 CYGARC_MTSPR (IBAT1U, ubat); | |
| 341 CYGARC_MTSPR (IBAT1L, lbat); | |
| 342 CYGARC_MTSPR (DBAT1U, ubat); | |
| 343 CYGARC_MTSPR (DBAT1L, lbat); | |
| 344 CYGARC_MTSPR (IBAT2U, ubat); | |
| 345 CYGARC_MTSPR (IBAT2L, lbat); | |
| 346 CYGARC_MTSPR (DBAT2U, ubat); | |
| 347 CYGARC_MTSPR (DBAT2L, lbat); | |
| 348 CYGARC_MTSPR (IBAT3U, ubat); | |
| 349 CYGARC_MTSPR (IBAT3L, lbat); | |
| 350 CYGARC_MTSPR (DBAT3U, ubat); | |
| 351 CYGARC_MTSPR (DBAT3L, lbat); | |
| 352 } | |
| 353 #endif | |
| 354 | |
| 355 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 356 { | |
| 357 // Initialize TLBs with 0, Valid bits unset. | |
| 358 | |
| 359 cyg_uint32 ctr; | |
| 360 int id; | |
| 361 int max_tlbs; | |
| 362 | |
| 363 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 364 // There are 32 TLBs. | |
| 365 max_tlbs = 32; | |
| 366 #endif | |
| 367 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 368 // There are 8 TLBs. | |
| 369 max_tlbs = 8; | |
| 370 #endif | |
| 371 | |
| 372 CYGARC_MTSPR (M_CASID, 0); | |
| 373 | |
| 374 for (id = 0; id < max_tlbs; id++) { | |
| 375 ctr = id << MI_CTR_INDX_SHIFT; | |
| 376 | |
| 377 // Instruction TLBs. | |
| 378 CYGARC_MTSPR (MI_TWC, 0); | |
| 379 CYGARC_MTSPR (MI_CTR, ctr); | |
| 380 CYGARC_MTSPR (MI_EPN, 0); | |
| 381 CYGARC_MTSPR (MI_RPN, 0); | |
| 382 // Data TLBs. | |
| 383 CYGARC_MTSPR (MD_TWC, 0); | |
| 384 CYGARC_MTSPR (MD_CTR, ctr); | |
| 385 CYGARC_MTSPR (MD_EPN, 0); | |
| 386 CYGARC_MTSPR (MD_RPN, 0); | |
| 387 } | |
| 388 } | |
| 389 #endif | |
| 390 } | |
| 391 | |
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392 // NB this demands that the platform HAL has provided an |
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393 // externC cyg_memdesc_t cyg_hal_mem_map[]; |
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394 // as detailed in hal_cache.h: |
| 2 | 395 externC void hal_MMU_init (void) |
| 396 { | |
| 397 int id = 0; | |
| 398 int i = 0; | |
| 399 | |
| 400 hal_clear_MMU (); | |
| 401 | |
| 402 while (cyg_hal_mem_map[i].size) { | |
| 403 id = hal_map_memory (id, | |
| 404 cyg_hal_mem_map[i].virtual_addr, | |
| 405 cyg_hal_mem_map[i].physical_addr, | |
| 406 cyg_hal_mem_map[i].size, | |
| 407 cyg_hal_mem_map[i].flags); | |
| 408 i++; | |
| 409 } | |
| 410 } | |
| 411 | |
| 412 //--------------------------------------------------------------------------- | |
| 413 // Initial cache enabling | |
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414 |
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415 // These are "indirected" to make it easier to support other platform |
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416 // variants in the future: |
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417 |
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418 #ifdef CYGPKG_HAL_POWERPC_COGENT |
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419 # define CYGPRI_INIT_CACHES 1 |
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420 # ifdef CYG_HAL_STARTUP_RAM |
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421 # define CYGPRI_ENABLE_CACHES 1 |
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422 # endif |
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423 #endif |
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424 |
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425 |
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426 // Do not enable caches for the FADS port pro tem; the memory mapping is |
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427 // not set up. |
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428 |
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parents:
16
diff
changeset
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429 // Do not enable caches for the simulator, it just slows it down. |
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7253dcc42a09
Merge from eCos master repository on 1999-06-25-15:31:50-BST
jlarmour
parents:
16
diff
changeset
|
430 |
| 2 | 431 externC void |
| 432 hal_enable_caches(void) | |
| 433 { | |
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18
7253dcc42a09
Merge from eCos master repository on 1999-06-25-15:31:50-BST
jlarmour
parents:
16
diff
changeset
|
434 #ifdef CYGPRI_INIT_CACHES |
| 2 | 435 // Initialize caches. |
| 436 HAL_ICACHE_UNLOCK_ALL(); | |
| 437 HAL_DCACHE_UNLOCK_ALL(); | |
| 438 HAL_ICACHE_INVALIDATE_ALL(); | |
| 439 HAL_DCACHE_INVALIDATE_ALL(); | |
| 440 | |
| 441 // Enable caches. | |
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18
7253dcc42a09
Merge from eCos master repository on 1999-06-25-15:31:50-BST
jlarmour
parents:
16
diff
changeset
|
442 #ifdef CYGPRI_ENABLE_CACHES |
| 2 | 443 // Cogent board doesn't support burst access to the ROM and on the |
| 444 // MPC8xx caches require burst. | |
| 445 HAL_ICACHE_ENABLE(); | |
| 446 HAL_DCACHE_ENABLE(); | |
| 447 #endif | |
| 448 #endif | |
| 449 | |
| 450 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 451 // Disable serialization | |
| 452 { | |
| 453 cyg_uint32 ictrl; | |
| 454 CYGARC_MFSPR (ICTRL, ictrl); | |
| 455 ictrl |= ICTRL_NOSERSHOW; | |
| 456 CYGARC_MTSPR (ICTRL, ictrl); | |
| 457 } | |
| 458 #endif | |
| 459 } | |
| 460 | |
| 461 //--------------------------------------------------------------------------- | |
| 0 | 462 // End of hal_misc.c |