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annotate packages/hal/powerpc/ppc40x/current/include/var_cache.h @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children e0c0827131d1
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //=============================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): nickg
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37 // Contributors:nickg, jskov
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38 // Date: 2000-04-02
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39 // Purpose: Variant cache control API
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40 // Description: The macros defined here provide the HAL APIs for handling
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41 // cache control operations on the PPC60x variant CPUs.
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42 // Usage: Is included via the architecture cache header:
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43 // #include <cyg/hal/hal_cache.h>
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44 // ...
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal.h>
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51 #include <cyg/infra/cyg_type.h>
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52
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53 #include <cyg/hal/ppc_regs.h>
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54
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55 #include <cyg/hal/plf_cache.h>
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56
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57
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58 //-----------------------------------------------------------------------------
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59 // Cache dimensions
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60
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61 // Data cache
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62 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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63 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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64 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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65
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66 // Instruction cache
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67 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
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68 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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69 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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70
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71 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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72 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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73
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74 //-----------------------------------------------------------------------------
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75 // Global control of data cache
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76
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77 // Enable the data cache - this is implicit whenever the MMU is turned on
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78 #define HAL_DCACHE_ENABLE()
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79
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80 // Disable the data cache
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81 #define HAL_DCACHE_DISABLE()
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82
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83 // Invalidate the entire cache
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84 #define HAL_DCACHE_INVALIDATE_ALL() \
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85 CYG_MACRO_START \
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86 int _i_, _ix_, _indx_; \
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87 _indx_ = 0; \
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88 _ix_ = HAL_DCACHE_SIZE/2; \
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89 for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
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90 /* asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); */ \
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91 /* asm volatile ("dcbf %1,%0;" :: "r"(_indx_), "r"(_ix_)); */\
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92 asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
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93 _indx_ += HAL_DCACHE_LINE_SIZE; \
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94 } \
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95 CYG_MACRO_END
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96
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97 // Synchronize the contents of the cache with memory.
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98 #define HAL_DCACHE_SYNC() \
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99 CYG_MACRO_START \
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100 int _indx_; \
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101 for (_indx_ = 0; _indx_ < HAL_DCACHE_SIZE; _indx_ += HAL_DCACHE_LINE_SIZE) { \
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102 asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); \
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103 } \
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104 CYG_MACRO_END
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105
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106 // Query the state of the data cache
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107 #define HAL_DCACHE_IS_ENABLED(_state_) \
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108 CYG_MACRO_START \
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109 (_state_) = 1; \
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110 CYG_MACRO_END
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111
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112 // Set the data cache refill burst size
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113 //#define HAL_DCACHE_BURST_SIZE(_size_)
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114
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115 // Set the data cache write mode
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116 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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117
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118 //#define HAL_DCACHE_WRITETHRU_MODE 0
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119 //#define HAL_DCACHE_WRITEBACK_MODE 1
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120
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121 // Load the contents of the given address range into the data cache
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122 // and then lock the cache so that it stays there.
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123 //#define HAL_DCACHE_LOCK(_base_, _size_)
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124
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125 // Undo a previous lock operation
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126 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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127
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128 // Unlock entire cache
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129 #define HAL_DCACHE_UNLOCK_ALL()
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130
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131 //-----------------------------------------------------------------------------
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132 // Data cache line control
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133
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134 // Allocate cache lines for the given address range without reading its
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135 // contents from memory.
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136 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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137
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138 // Write dirty cache lines to memory and invalidate the cache entries
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139 // for the given address range.
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140 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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141
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142 // Invalidate cache lines in the given range without writing to memory.
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143 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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144
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145 // Write dirty cache lines to memory for the given address range.
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146 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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147
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148 // Preread the given range into the cache with the intention of reading
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149 // from it later.
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150 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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151
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152 // Preread the given range into the cache with the intention of writing
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153 // to it later.
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154 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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155
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156 // Allocate and zero the cache lines associated with the given range.
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157 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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158
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159 //-----------------------------------------------------------------------------
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160 // Global control of Instruction cache
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161
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162 // Enable the instruction cache
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163 #define HAL_ICACHE_ENABLE()
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164
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165 // Disable the instruction cache
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166 #define HAL_ICACHE_DISABLE()
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167
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168 // Invalidate the entire cache
136
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169 #define HAL_ICACHE_INVALIDATE_ALL() \
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170 CYG_MACRO_START \
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171 int _i_, _indx_; \
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172 _indx_ = 0; \
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173 for (_i_ = 0; _i_ < HAL_ICACHE_SETS; _i_++) { \
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174 asm volatile ("iccci 0,%0;" :: "r"(_indx_)); \
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175 _indx_ += HAL_ICACHE_LINE_SIZE; \
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176 } \
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177 CYG_MACRO_END
134
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178
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179 // Synchronize the contents of the cache with memory.
136
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180 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
134
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181
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182 // Query the state of the instruction cache
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183 #define HAL_ICACHE_IS_ENABLED(_state_) \
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184 CYG_MACRO_START \
136
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185 (_state_) = 1; \
134
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186 CYG_MACRO_END
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187
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188 // Set the instruction cache refill burst size
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189 //#define HAL_ICACHE_BURST_SIZE(_size_)
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190
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191 // Load the contents of the given address range into the instruction cache
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192 // and then lock the cache so that it stays there.
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193 //#define HAL_ICACHE_LOCK(_base_, _size_)
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194
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195 // Undo a previous lock operation
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196 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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197
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198 // Unlock entire cache
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199 #define HAL_ICACHE_UNLOCK_ALL()
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200
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201 //-----------------------------------------------------------------------------
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202 // Instruction cache line control
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203
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204 // Invalidate cache lines in the given range without writing to memory.
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205 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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206
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207 //-----------------------------------------------------------------------------
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208 #endif // ifndef CYGONCE_VAR_CACHE_H
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209 // End of var_cache.h