Mercurial > flash_v2

annotate packages/hal/sh/arch/current/src/sh_stub.c @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 289bf90c6a9b
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1 //==========================================================================
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2 //
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3 // sh_stub.c
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4 //
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5 // GDB Stub code for SH
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors: jskov, Ben Lee, Steve Chamberlain
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36 // Date: 1999-05-18
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37 // Description: GDB Stub support for sh CPU.
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38 //
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39 //####DESCRIPTIONEND####
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40 //
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41 //===========================================================================
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42
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43 #include <stddef.h>
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44
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45 #include <pkgconf/hal.h>
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46
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47 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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48
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49 #include <cyg/hal/sh_regs.h>
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50
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51 #include <cyg/hal/hal_stub.h>
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52 #include <cyg/hal/hal_arch.h>
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53 #include <cyg/hal/hal_intr.h>
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54
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55 #ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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56 #include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
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57 #endif
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58
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59 /* Given a trap value TRAP, return the corresponding signal. */
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60
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61 int
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62 __computeSignal(unsigned int trap_number)
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63 {
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64 switch( trap_number ) {
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65 case CYGNUM_HAL_EXCEPTION_TRAP:
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66 case CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP:
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67 return SIGTRAP;
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68
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69 case CYGNUM_HAL_EXCEPTION_POWERON:
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70 case CYGNUM_HAL_EXCEPTION_RESET:
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71 // Reset - given that the CPU resets if it gets confused we
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72 // want to treat it as an interupt so the developer has a
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73 // chance to find out what happened (as opposed to SIGTERM).
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74 return SIGINT;
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75
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76 case CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS:
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77 case CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE:
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78 case CYGNUM_HAL_EXCEPTION_INITIAL_WRITE:
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79 case CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS:
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80 case CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE:
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81 return SIGSEGV;
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82
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83 case CYGNUM_HAL_EXCEPTION_DATA_ACCESS:
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84 case CYGNUM_HAL_EXCEPTION_DATA_WRITE:
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85 return SIGBUS;
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86
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87 case CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION:
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88 case CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION:
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89 return SIGILL;
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90
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91 default:
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92 return SIGTERM;
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93 }
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94 }
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95
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96 /* Return the trap number corresponding to the last-taken trap. */
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97
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98 int
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99 __get_trap_number(void)
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100 {
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101 // The vector is not not part of the GDB register set so get it
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102 // directly from the save context.
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103 return _hal_registers->event;
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104 }
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105
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106 /* Set the currently-saved pc register value to PC. This also updates NPC
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107 as needed. */
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108
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109 void
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110 set_pc(target_register_t pc)
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111 {
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112 put_register(PC, pc);
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113 }
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114
121
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115 #ifdef CYGARC_SH_MOD_UBC
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116
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117 // This implementation of the single-stepper relies on the User Break
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118 // Controller which may not be available on all cores.
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119
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120 // Note: This should be enhanced to coorperate with either two regular
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121 // breakpoints or watchpoints. Requires GDB to be aware of the stub's
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122 // ability though, so for now just use channel A without further
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123 // considerations.
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124
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125 /* Set things up so that the next user resume will execute one instruction.
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126 This may be done by setting breakpoints or setting a single step flag
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127 in the saved user registers, for example. */
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128
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129 void __single_step (void)
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130 {
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131 // The address of the instruction to execute.
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132 HAL_WRITE_UINT32(CYGARC_REG_BARA, get_register(PC));
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133 // Match entire address.
134
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134 #if (CYGARC_SH_MOD_UBC == 1)
121
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135 HAL_WRITE_UINT8(CYGARC_REG_BAMRA, CYGARC_REG_BAMRA_BARA_UNMASKED);
128
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136 #else
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137 HAL_WRITE_UINT32(CYGARC_REG_BAMRA, 0xffffffff);
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138 #endif
121
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139 // Stop after instruction at matching address has executed.
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140 HAL_WRITE_UINT16(CYGARC_REG_BRCR, CYGARC_REG_BRCR_PCBA);
136
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141
121
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142 // Stop on IFETCH/READ
134
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143 #if (CYGARC_SH_MOD_UBC == 3)
136
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144 HAL_WRITE_UINT16(CYGARC_REG_BBRA,
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145 CYGARC_REG_BBRA_CPU|CYGARC_REG_BBRA_IFETCH|CYGARC_REG_BBRA_READ);
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146 #else
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147 HAL_WRITE_UINT16(CYGARC_REG_BBRA,
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148 CYGARC_REG_BBRA_IFETCH|CYGARC_REG_BBRA_READ);
128
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149 #endif
121
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150 }
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151
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152 /* Clear the single-step state. */
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153
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154 void __clear_single_step (void)
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155 {
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156 // Don't stop on any condition
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157 HAL_WRITE_UINT16(CYGARC_REG_BBRA, 0);
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158 // Clear status flags
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159 HAL_WRITE_UINT16(CYGARC_REG_BRCR, 0);
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160 }
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161
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162 #else // CYGARC_SH_MOD_UBC
76
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163
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164 /*----------------------------------------------------------------------
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165 * Single-step support, copied from gdb/sh-stub.c, written by Ben Lee
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166 * and Steve Chamberlain. Extended to handle braf, bsrf, bt/s and bf/s.
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167 */
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168
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169 #define COND_BRx_MASK 0xfb00
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170 #define UCOND_DBR_MASK 0xe000
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171 #define UCOND_RBR_MASK 0xf0df
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172 #define TRAPA_MASK 0xff00
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173
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174 #define COND_DISP 0x00ff
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175 #define UCOND_DISP 0x0fff
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176 #define UCOND_REG 0x0f00
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177
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178 #define BFx_INSTR 0x8b00
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179 #define BTx_INSTR 0x8900
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180 #define BRA_INSTR 0xa000
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181 #define BSR_INSTR 0xb000
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182 #define JMP_INSTR 0x402b
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183 #define JSR_INSTR 0x400b
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184 #define RTS_INSTR 0x000b
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185 #define RTE_INSTR 0x002b
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186 #define TRAPA_INSTR 0xc300
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187 #define BxxF_INSTR 0x0003
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188
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189 #define SSTEP_INSTR 0xc3ff
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190
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191 #define T_BIT_MASK 0x0001
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192
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193 typedef struct {
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194 short *memAddr;
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195 short oldInstr;
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196 } stepData;
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197
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198 static stepData instrBuffer;
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199 static char stepped;
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200
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201 /* Set things up so that the next user resume will execute one instruction.
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202 This may be done by setting breakpoints or setting a single step flag
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203 in the saved user registers, for example. */
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204
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205 void __single_step (void)
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206 {
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207 short *instrMem;
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208 int displacement;
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209 int reg;
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210 unsigned short opcode;
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211
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212 cyg_uint32 pc = get_register(PC);
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213 cyg_uint32 sr = get_register(SR);
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214
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215 instrMem = (short *) pc;
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216
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217 opcode = *instrMem;
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218 stepped = 1;
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219
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220 if ((opcode & UCOND_RBR_MASK) == BxxF_INSTR) {
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221 reg = (char) ((opcode & UCOND_REG) >> 8);
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222 displacement = get_register(reg);
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223 instrMem = (short *) (pc + displacement + 4);
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224 /*
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225 * Remember PC points to second instr.
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226 * after PC of branch ... so add 4
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227 */
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228 } else if ((opcode & COND_BRx_MASK) == BTx_INSTR) {
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229 if (sr & T_BIT_MASK) {
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230 displacement = (opcode & COND_DISP) << 1;
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231 if (displacement & 0x80) {
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232 displacement |= 0xffffff00;
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233 }
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234 /*
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235 * Remember PC points to second instr.
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236 * after PC of branch ... so add 4
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237 */
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238 instrMem = (short *) (pc + displacement + 4);
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239 } else {
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240 instrMem += 1;
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241 }
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242 } else if ((opcode & COND_BRx_MASK) == BFx_INSTR) {
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243 if (sr & T_BIT_MASK) {
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244 instrMem += 1;
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245 } else {
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246 displacement = (opcode & COND_DISP) << 1;
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247 if (displacement & 0x80)
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248 displacement |= 0xffffff00;
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249 /*
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250 * Remember PC points to second instr.
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251 * after PC of branch ... so add 4
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252 */
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253 instrMem = (short *) (pc + displacement + 4);
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254 }
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255 } else if ((opcode & UCOND_DBR_MASK) == BRA_INSTR) {
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256 displacement = (opcode & UCOND_DISP) << 1;
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257 if (displacement & 0x0800) {
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258 displacement |= 0xfffff000;
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259 }
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260
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261 /*
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262 * Remember PC points to second instr.
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263 * after PC of branch ... so add 4
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264 */
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265 instrMem = (short *) (pc + displacement + 4);
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266 } else if ((opcode & UCOND_RBR_MASK) == JSR_INSTR) {
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267 reg = (char) ((opcode & UCOND_REG) >> 8);
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268 instrMem = (short *) get_register(reg);
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269 } else if (opcode == RTS_INSTR) {
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270 instrMem = (short *) get_register(PR);
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271 } else if (opcode == RTE_INSTR) {
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272 instrMem = (short *) get_register(SP);
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273 } else if ((opcode & TRAPA_MASK) == TRAPA_INSTR) {
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274 instrMem += 1; // skip traps
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275 } else {
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276 instrMem += 1;
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277 }
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278
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279 instrBuffer.memAddr = instrMem;
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280 instrBuffer.oldInstr = *instrMem;
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281 *instrMem = SSTEP_INSTR;
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282 }
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283
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284 /* Clear the single-step state. */
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285
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286 void __clear_single_step (void)
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287 {
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288 /* Undo the effect of a previous doSStep. If we single stepped,
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289 restore the old instruction. */
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290
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291 if (stepped) {
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292 short *instrMem;
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293 instrMem = instrBuffer.memAddr;
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294 *instrMem = instrBuffer.oldInstr;
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295 }
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296 stepped = 0;
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297 }
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298
121
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299 #endif // CYGARC_SH_MOD_UBC
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300
76
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301
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302 void __install_breakpoints (void)
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303 {
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304 /* NOP since single-step HW exceptions are used instead of
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305 breakpoints. */
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306 }
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307
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308 void __clear_breakpoints (void)
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309 {
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310 }
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311
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312
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313 /* If the breakpoint we hit is in the breakpoint() instruction, return a
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314 non-zero value. */
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315
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316 int
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317 __is_breakpoint_function ()
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318 {
115
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319 return get_register(PC) == (target_register_t)&_breakinst;
76
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320 }
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321
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322
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323 /* Skip the current instruction. Since this is only called by the
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324 stub when the PC points to a breakpoint or trap instruction,
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325 we can safely just skip 2. */
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326 void __skipinst (void)
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327 {
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328 put_register(PC, get_register (PC) + 2);
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329 }
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330
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331 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS